2802 results about "Memory controller" patented technology

The invention discloses a memory fault repairing method and device, equipment, a medium and a computer program product, and relates to the technical field of computers.The memory fault repairing method includes the steps that memory error information sent by a memory controller is obtained, a fault target memory page can be positioned, and a standby memory page is obtained from a standby memory pool; the memory address mapping table is updated, the physical address of the target memory page with the fault is mapped to the physical address of the standby memory page, the repairing process does not depend on triggering of a system management interrupt mechanism, memory repairing in the system running stage is achieved, the system downtime caused by memory fault repairing is shortened, and therefore the memory repairing efficiency is improved. The problem of high delay in memory fault processing can be solved, and the technical effect of improving the memory fault repairing efficiency is achieved.

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

The invention provides a modularized integrated circuit unit and a distributed storage unit access method and system, and the modularized integrated circuit unit comprises at least one memory controller which sends a storage address access request to a storage unit; the at least one storage unit provides unified memory access for the storage address access request, and the storage unit comprises a local storage unit and a virtual far-end storage unit; the at least one computing unit initiates a storage address access request; and the at least one internet-on-chip is used for interleaving the storage address indicated by the storage address access request, generating interleaved storage address distribution, determining a corresponding target storage unit, and storing the target storage unit by setting a local storage unit and a virtual far-end storage unit. Uniform address access and load balancing of the distributed storage units on the modularized integrated circuit units are achieved through the address interleaving technology and the virtual storage mapping, the resource utilization rate is increased, and the performance and usability of the distributed storage system are improved.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system that includes DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and send the precharge command to at least one DRAM bank of the particular DRAM group.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data, and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block and 2) control the memory device to perform a write operation in the determined write mode.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The embodiment of the invention provides a memory testing system and method, and relates to the technical field of embedded system hardware manufacturing. According to the memory test system disclosed by the invention, the physical layer interface of the memory controller is calibrated, the input / output interface of the memory bus is trained, and the optimized parameters are generated, so that the memory data of the memory unit (including memory particles) can be collected under the optimal condition corresponding to the optimized parameters. And then, carrying out a pressure test on the storage unit based on the optimized parameters, and recording fault information and abnormal information of the storage unit according to a pressure test result. Therefore, the memory test system provided by the invention not only can cover the test of the memory particles, but also can cover the test of the memory controller, and can ensure the stability and reliability of the whole memory unit.

Provided are a universal flash storage (UFS) device for preventing a replay attack, a method of operating the same, and a UFS system. The UFS device including: a memory including a replay protection memory block (RPMB) region, the RPMB region including one or more index fields storing a second write failure index; and a memory controller including at least one controller memory storing one or more instructions, wherein the memory controller is configured to execute the one or more instructions to cause the UFS device to: receive, from an external device, an RPMB write request including a first write failure index, meta information, and a first message authentication code generated based on the first write failure index and the meta information, and determine whether to perform an authentication operation on the external device based on the first write failure index and the second write failure index.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

The subject application relates to separate command address (SCA) protocol-based memory controllers. For instance, a method may include receiving, by a separate command address (SCA)-based memory controller, a plurality of commands, scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues, converting the scheduled plurality of commands into SCA-based commands, selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution, and executing in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module, the memory module is provided with a plurality of chips, each chip is provided with a plurality of planes, and each plane is provided with a plurality of entity blocks. The method comprises the following steps: acquiring a chip enabling number of a memory module; selecting a target allocation method from a plurality of allocation methods according to the chip enabled number, the plurality of allocation methods including a first allocation method based on a plurality of chips and a second allocation method based on a plurality of planes; and dividing the plurality of entity blocks into a plurality of super blocks based on a target allocation method. Thus, the allocation strategy of the super blocks is optimized through the target allocation method, the utilization rate of the entity blocks in the memory module is improved, and meanwhile the garbage collection efficiency is improved.

The present disclosure relates to systems and methods implemented on a memory controller for detecting and mitigating memory attacks (e.g., row hammer attacks). For example, a memory controller may engage a counting mode in which activation counts for memory sub-banks are tracked. For example, a memory controller may engage a counting mode in which activation counts for memory rows of memory sub-banks are maintained. Under certain conditions, the memory controller may transition from the counting mode to a sampling mode to mitigate potential row hammer attacks. The memory controller may consider various conditions in determining whether to continue detecting and mitigating potential row hammer attacks in the sampling mode and / or transitioning back to the counting mode. By selectively transitioning between the different operating modes, the memory controller may reduce periods of time when the memory hardware is vulnerable to attacks.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and / or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Embodiments of the present application provide a memory device, a memory system, a memory controller, and an operation method. The memory device comprises: storage units each having multiple storage bits, wherein a preset number of storage units form a codeword, and the multiple storage bits respectively correspond to multiple pages, at least some pages correspond to multiple levels, the multiple levels include a first level and a second level, and a read voltage of the second level is less than that of the first level; and a peripheral circuit of the memory device, configured to: acquire a predicted valley voltage of the first level on the basis of a corresponding first result under a target read voltage of the first level, wherein the first result comprises the number of flipped bits of at least one codeword in two read results; acquire a predicted valley voltage of the second level on the basis of the predicted valley voltage of the first level; and use the predicted valley voltage of the first level and the predicted valley voltage of the second level to perform a first read operation on the at least one codeword.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

A sub-block-based storage device includes a memory device configured to include a plurality of memory blocks, a work memory storing instructions, and a memory controller communicatively coupled with the memory device and the work memory and configured to manage the plurality of memory blocks. Each block of the plurality of memory blocks includes a plurality of sub-blocks having different capacities. The memory controller is configured to execute the instructions to manage used sub-blocks which store valid data from among the plurality of sub-blocks, manage free sub-blocks which are empty from among the plurality of sub-blocks, select a garbage collection source block from the used sub-blocks, select candidate destination blocks by comparing a size of valid data stored in the garbage collection source block and each of sizes of the free sub-blocks, and select a garbage collection destination block from the candidate destination blocks.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

Memory controller commands to be sent to a memory device may be prioritized based one or more factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read) are prioritized over other types of commands (e.g., write). The policy may be modified so when deciding which bank to open, the bank with the oldest read command is opened. While continuing to issue commands per this modified FRFCFS policy, the controller may keep track of banks whose pages are ready to receive their respective read commands. Once a number of ready banks meets or exceeds a threshold, issuance of write commands are paused and read commands for the ready banks are issued.

Disclosed in some examples are improvements to memory controllers on distributed memory systems that include a fine-grained data mover component that offloads management of memory commands accessing multiple smaller values to the memory controller. The fine-grained data mover (FGDM) may provide low host processing overhead that enables performance improvements for small task offloads. Work requests (“data mover calls”) may be sent by hosts to the FGDM without OS system calls. The FGDM is a virtually addressed data movement engine architected to transfer data at high transfer rates even during situations where the host has many small data movement requests and where the source and / or destination addresses are not memory controller friendly.

A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.