2042 results about "Memory controller" patented technology

This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module, the memory module is provided with a plurality of chips, each chip is provided with a plurality of planes, and each plane is provided with a plurality of entity blocks. The method comprises the following steps: acquiring a chip enabling number of a memory module; selecting a target allocation method from a plurality of allocation methods according to the chip enabled number, the plurality of allocation methods including a first allocation method based on a plurality of chips and a second allocation method based on a plurality of planes; and dividing the plurality of entity blocks into a plurality of super blocks based on a target allocation method. Thus, the allocation strategy of the super blocks is optimized through the target allocation method, the utilization rate of the entity blocks in the memory module is improved, and meanwhile the garbage collection efficiency is improved.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

Embodiments of the present application provide a memory device, a memory system, a memory controller, and an operation method. The memory device comprises: storage units each having multiple storage bits, wherein a preset number of storage units form a codeword, and the multiple storage bits respectively correspond to multiple pages, at least some pages correspond to multiple levels, the multiple levels include a first level and a second level, and a read voltage of the second level is less than that of the first level; and a peripheral circuit of the memory device, configured to: acquire a predicted valley voltage of the first level on the basis of a corresponding first result under a target read voltage of the first level, wherein the first result comprises the number of flipped bits of at least one codeword in two read results; acquire a predicted valley voltage of the second level on the basis of the predicted valley voltage of the first level; and use the predicted valley voltage of the first level and the predicted valley voltage of the second level to perform a first read operation on the at least one codeword.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The present application relates to the technical field of computers, and provides a memory data access method and apparatus, an electronic device and a readable storage medium. The method comprises: acquiring failure information of a memory component; configuring an address space mapping scheme for the failure information; in response to an initial memory access instruction sent by a processor, extracting a memory access address in the initial memory access instruction; on the basis of the memory access address and the address space mapping scheme, acquiring a plurality of target addresses corresponding to the memory access address, wherein target memory access instructions have one-to-one correspondence to the target addresses; executing the target memory access instructions by means of a memory controller so as to write split data, which is obtained after splitting write data sent by the processor, into the target addresses; and splicing read data read from the target addresses, and then returning to the processor.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

The invention discloses a method for accelerating secure metadata access in a secure memory system, a memory controller and a system, and belongs to the field of secure memory systems, and the method comprises the following steps: when a page table item corresponding to a logic page where data accessed by a processor is located does not hit a TLB, obtaining the page table item from a memory page table, extracting a physical page address from the page table item, and storing the physical page address in a memory; a counter corresponding to a physical page where the data to be accessed is located and a father node of the counter in the integrity tree are prefetched through the physical page address; adding a replacement dirty block address in a miss request sent by the last level of cache, after receiving the miss request containing a field of the replacement dirty block address, executing conventional memory reading and decryption, positioning a counter corresponding to the replacement dirty block address, and performing prefetching by using an idle memory bandwidth; in addition to the secure metadata cache, the prefetching queue is maintained to temporarily store the prefetched metadata. The cache hit rate of the security metadata in the security memory system can be improved, and the performance overhead caused by the cache miss can be reduced.

A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

Techniques for memory tagging based on data transformations in a computing system are described. In certain examples, a computing system includes a memory; an execution circuitry to execute an instruction to generate a memory request, comprising a location and a first tag, to read a data line from the memory; and a memory controller circuit to: retrieve data at the location from the memory request, unmask the data using the first tag from the memory request to generate first unmasked data, unmask the data using a second set of one or more tags to generate a corresponding second set of unmasked data, determine that the first unmasked data is random data, determine that the corresponding second set of unmasked data is random data, and send the first unmasked data for the memory request in response to the first unmasked data being the random data, and the corresponding second set of unmasked data being the random data.

The invention relates to a non-volatile memory erase scheme. Methods, systems, and devices provide techniques for erasing data in a memory device. The memory device includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines forming a subset of word lines in the memory block. The memory device further includes a memory controller configured to perform: receiving an erase command for erasing data in the memory block; and in response to receiving the erase command, causing one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different periods such that when data erase begins at a first word line segment, data erase does not start at another word line segment.

The invention discloses a data processing method and system, electronic equipment and a medium, and relates to the technical field of storage. The output end of the memory controller unit is connected with the plurality of cache unit groups through a plurality of channels, and the channels are in one-to-one correspondence with the cache unit groups, so that a multi-channel architecture is constructed. When data processing is carried out based on a multi-channel architecture, after a memory address space is divided into different channels in advance, after a request sent by a request sender is received, a channel hit by a request address is determined according to a division result obtained after the memory address space is divided into the different channels in advance, and the channel hit by the request address is determined. And finally, in the memory connected with the channel hit by the request address, responding to the request based on the request address to realize data processing. And secondly, the memory address space is divided into different channels in advance, so that the multiple channels can process different read-write requests at the same time, the requirement for high-speed data processing is met, idle resources are avoided, and the resource utilization rate is increased.

The embodiment of the invention provides a memory controller, an error address positioning method and a computing system. The memory controller comprises an algorithm control circuit, a data generation circuit, a data comparison circuit and a monitoring circuit, and the algorithm control circuit is configured to generate control information for memory testing based on preset steps of a test algorithm; the data generation circuit is configured to generate test data used for being written into the memory to be tested and expected data obtained after the test data is read; the data comparison circuit is configured to detect whether target data read from the to-be-detected memory is consistent with expected data or not; and the monitoring circuit is configured to respond to the inconsistency of the read target data and the expected data, send a mark for stopping the memory test to the algorithm control circuit so as to stop the memory test and record a test address corresponding to an error and corresponding command data, so that stop and quick positioning are realized when the error occurs, and the repair efficiency is improved.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled with the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M target read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model. The peripheral circuit may be configured to determine a target valley voltage based on the predicted valley voltage. The target valley voltage may be configured as a read voltage for a read operation on the at least one code word.

Examples disclose a memory system and operating method thereof and computer-readable storage medium. An example memory system includes a memory controller and a memory coupled to the memory controller. The memory includes multiple memory blocks, a memory block includes multiple physical pages. The memory controller is configured to: determine at least one source memory block from the multiple memory blocks; in response to the bitmap type associated with a first source memory block from the at least one source memory block being a first bitmap, write valid data stored in the first source memory block into the first target memory block from the multiple memory blocks; in response to the valid data being written into the first target memory block, erase the source memory block.

A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2N states corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.

A storage device includes a main cell array including a plurality of main memory cells connected to a plurality of main wordlines, and a redundancy cell array including a plurality of redundancy memory cells connected to a plurality of redundancy wordlines. The redundancy wordlines are configured to replace a fail wordline including a fail memory cell among the main wordlines. The storage device further includes a repair information memory that stores repair-need-wordline information including matching information for the redundancy wordlines. The matching information is determined by identifying the fail word lines among the main wordlines, and selecting a repair-need-wordline having more fail bits than a specified fail bit criteria. A memory controller performs a read or write operation on a redundancy wordline corresponding to the repair-need-wordline when a request for the main cell array is identified as targeting the repair-need-wordline based on the repair-need-wordline information.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

In some implementations, a memory system may receive multiple memory requests associated with a memory, wherein the memory is associated with multiple memory ranks, and wherein each memory request, of the multiple memory requests, includes a memory address indicating a memory rank, of the multiple memory ranks, that is to be accessed for that memory request. The memory system may group the multiple memory requests based on the multiple memory ranks. The memory system may transmit, to a memory controller associated with the memory, a scheduled set of memory requests, wherein the scheduled set of memory requests includes memory requests selected from one or more groups of memory requests associated with one or more scheduled memory ranks of the multiple memory ranks.

A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.