1143 results about "Memory controller" patented technology

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

The invention discloses a method for accelerating secure metadata access in a secure memory system, a memory controller and a system, and belongs to the field of secure memory systems, and the method comprises the following steps: when a page table item corresponding to a logic page where data accessed by a processor is located does not hit a TLB, obtaining the page table item from a memory page table, extracting a physical page address from the page table item, and storing the physical page address in a memory; a counter corresponding to a physical page where the data to be accessed is located and a father node of the counter in the integrity tree are prefetched through the physical page address; adding a replacement dirty block address in a miss request sent by the last level of cache, after receiving the miss request containing a field of the replacement dirty block address, executing conventional memory reading and decryption, positioning a counter corresponding to the replacement dirty block address, and performing prefetching by using an idle memory bandwidth; in addition to the secure metadata cache, the prefetching queue is maintained to temporarily store the prefetched metadata. The cache hit rate of the security metadata in the security memory system can be improved, and the performance overhead caused by the cache miss can be reduced.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.

A memory apparatus includes a memory device, a memory controller and a memory physical layer interface. The memory physical layer interface comprises a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit. The tap reset circuit generates a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset a DFE taps of the multi-tap DFE receiver during the gap interval between the read bursts. The tap reset circuit resets the plurality of DFE taps using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval. The tap reset circuit resets the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval. The second predetermined interval is greater than the first predetermined interval.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention discloses a memory controller, a memory address processing method thereof and a computing system.The method comprises the steps that a reverse mapping table between a system physical address area and an available DRAM physical address area is obtained through bad area data based on a DRAM, and during running, the memory controller sends a system physical address sent by a processor to the DRAM physical address area according to the reverse mapping table; the method comprises the following steps: dynamically remapping to a DRAM physical address of a non-failure unit, and generating a corresponding control signal for accessing the DRAM, thereby shielding a DRAM physical region containing a failure storage unit, providing a continuous and complete system physical address space for an upper layer, improving the effective utilization rate of the DRAM and the operation stability of a computing system, and improving the reliability of the computing system on the premise of not changing the memory access mode of a processor. And the risk that the whole memory is unavailable due to local storage failure is reduced.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

There is provided a storage device which includes a plurality of nonvolatile memory devices, and a memory controller connected in common to the plurality of nonvolatile memory devices through first signal lines and connected in common to the plurality of nonvolatile memory devices through second signal lines. Each of the plurality of nonvolatile memory devices receives a command and an address through the first signal lines and communicates data bits with the memory controller through the second signal lines. While the command and the address are not received through the first signal lines, the plurality of nonvolatile memory devices exchange information through the first signal lines without control of the memory controller.

Cache, cache management method, and electronic device. The cache includes: multiple cache lines, a first read request queue and a second read request queue; a first read request queue is configured for storing and sending a first read request to a memory controller; the first read request is configured for requesting data from memory and storing the data in the memory controller; the number of the first read requests stored in the first read request queue is greater than that of the multiple cache lines; the second read request queue is configured for storing and sending a second read request to memory controller; and the second read request corresponds one-to-one with the first read request, and the second read request is used to request data corresponding to the first read request from the memory controller when a cache line corresponding to the first read request is idle

A semiconductor package includes a substrate, a platform die provided on the substrate, a memory die provided on the platform die, and a processor die provided on the platform die and provided adjacent to the memory die, wherein the platform die includes a memory controller configured to control data communication between the memory die and the processor die.

According to the memory controller and the microcontroller chip provided by the invention, on the basis of a memory controller architecture with an ECC (Error Correction Code) verification logic module, an intelligent copying control module is additionally added, and when a CPU (Central Processing Unit) reads corresponding contents in a first memory, the corresponding contents in the first memory are copied; according to the method, the soft failure position can be accurately identified through the ECC verification logic module, errors of 1 bit or 2 bit or several bits can be corrected, and when the error correction capability range of ECC verification is exceeded, the error correction requirements of the soft failure position and the system can be corrected by the intelligent copy control module according to the conditions of different ECC verification errors and the condition of the soft failure position. Different error correction modes are selected to process the soft failure in the first memory, and it is not necessary to generate reset to destroy coherent execution of a program when the error correction capability range of ECC verification is exceeded every time, so that quick correction of soft failure errors is realized under different soft failure conditions, the system operation coherence is improved, and the error correction efficiency is improved. And high reliability of system operation is considered, and various reliability demand scenes are covered.

A storage device includes a memory device and a memory controller to control the memory device by communicating with the memory device through a channel. The memory device includes a plurality of memory chips sharing the channel and each of the plurality of memory chips includes a transmission driver and an adaptive body bias generator. A target memory chip selected by the memory controller, among the plurality of memory chips, includes a first adaptive body bias generator and a first transmission driver. The first adaptive body bias generator applies a first body bias to the first transmission driver in a write mode in which the target memory chip receives a write data from the memory controller and applies a second body bias in a read mode in which the target memory chip transmits a read data to the memory controller.

A method for error correction includes reading, by a memory controller, a first-level codeword from a memory device, the first-level codeword having user data and first-level parity data. The method includes decoding, by the memory controller responsive to determining the first-level codeword contains errors, the first-level codeword using a first-level low-density parity-check (LDPC) decoder employing a first-level H matrix having a portion with reduced column weights to reduce an average row weight for the first-level H matrix. Responsive to the first-level LDPC decoder failing to correct the errors in the first-level codeword, the memory controller decodes a second-level codeword using a second-level LDPC decoder employing a second-level H matrix that includes a portion with increased column weights to increase an average row weight of a second-level of the second-level H matrix. The second-level codeword having the user data, the first-level parity data and second-level parity data.

Apparatuses and techniques for reporting multiple events associated with mitigating usage-based disturbance are described. In an example aspect, a memory device can report to a memory controller various events associated with mitigating usage-based disturbance. This includes notifying the memory controller of events associated with a first event category and alerting the memory controller of events associated with a second event category. For events associated with the first event category, there can be a smaller risk of an alert condition occurring if the memory controller does not take action. For events associated with the second event category, there can be a larger risk of an alert condition occurring if the memory controller does not take action. By reporting these multiple events by category, the memory device empowers the memory controller to take appropriate action and efficiently manage available resources for mitigating usage-based-disturbance.

A storage device includes a memory device that includes a plurality of memory cells, and a memory controller that controls the memory device. The memory device includes a memory cell array that includes the plurality of memory cells, a control logic circuit that writes data to the memory cell array or reads data from the memory cell array in response to a command received from the memory controller, and a page buffer that stores sensing data sensed from the plurality of memory cells. The control logic circuit includes an error detecting circuit that detects an error of first data stored in first memory cells of the memory cell array, and the control logic circuit writes the first data to second memory cells of the memory cell array, based on an error comparison result obtained by comparing the error of the first data with a preset value.

A memory device includes a stacked memory, a plurality of conductive vias, and a memory controller. The stacked memory includes a plurality of memory chips. Each memory chip includes at least one memory cell array, a chip identification device, and a signal path switch. The chip identification device is coupled to the at least one memory cell array. The signal path switch is coupled to the chip identification device. The conductive vias penetrate through the stacked memory. The memory controller is coupled to the stacked memory.

Embodiments of the present disclosure relate to a memory system and an operating method thereof. The memory system can include a memory device and a memory controller configured to, when receiving a flush command indicating data to be cached in a data cache is flushed to the memory device from a host, flush first data to be cached in the data cache to the memory device, a size of the first data being less than a size of a reference write unit, write first parity associated with the first data to a parity storage block, update a value of a parity location pointer indicating a location where the first parity is written, and set a parity write flag indicating whether parity at a location pointed to by the parity location pointer is valid.

A system and method reduce bootup latency in systems that run Auto operating systems (Auto OS). When, or just prior to, the system controller initiating suspend-to-disk (S2D) process entry, the system controller causes a memory controller to determine the percentage of volatile memory that is currently occupied and compares that percentage of occupancy to a predetermined threshold (TH) percentage. If the percentage of occupancy exceeds the predetermined TH percentage, then the memory controller tags apps that are occupying volatile memory as either background apps or foreground apps, terminates the background apps, clears volatile memory of any instructions and data associated with the terminated background apps, takes a snapshot of the state of volatile memory after the terminated background apps and associated data have been cleared, and saves the snapshot to a designated storage location in nonvolatile memory before entering hibernate mode.

The embodiment of the invention provides a memory system, an operation method thereof and electronic equipment. The memory system includes: a nonvolatile memory device including a plurality of pages; the preset number of pages form a storage group; the memory controller is coupled with the nonvolatile memory device and is configured to determine a reading voltage of the to-be-read data according to a first duration of a target storage group where the to-be-read data is located in a process of performing a reading operation on the nonvolatile memory device; the first duration is the time difference between the moment when the last write-in is completed in the target storage group and the reading operation starting moment.

The present disclosure provides an integrated circuit comprising a memory controller configured to transmit information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correcting code algorithm, and to generate an interrupt signal in the event of detection of at least one error in the information and a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in the information by the error detection circuit.

Various aspects relate to a memory module including: a memory interface; a non-volatile storage device for persistently storing data; a non-volatile memory device providing a write first in first out, FIFO, buffer in hardware, the write FIFO buffer being configured to receive, via the memory interface, and to store packets associated with one or more atomic transactions, wherein each of the one or more atomic transactions includes a respective plurality of packets and indicates corresponding data to be written to the memory module; a memory controller configured to write the corresponding data of an atomic transaction of the one or more atomic transactions to the memory module in the case that the write FIFO buffer stores the respective plurality of packets of the atomic transaction.

Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.

Based on the WAF (Write Amplification Factor) value, the efficiency of writing data to non-volatile memory is improved, extending the lifespan of the non-volatile memory. [Solution] The image forming apparatus includes an image forming unit, a non-volatile memory (flash memory) for storing data, a memory controller for controlling the writing of data to the non-volatile memory, a storage device (SSD) including a storage unit that holds size information of the first data written to the non-volatile memory by the memory controller, and a main controller that outputs the second data to be written to the non-volatile memory to the memory controller. The main controller suspends the writing of the second data to the non-volatile memory if the size of the second data to be written to the non-volatile memory is less than or equal to a preset minimum size, and writes the two or more suspended second data to the non-volatile memory as a single second data if the combined size exceeds the minimum size.

A memory system includes a plurality of memory devices each including a memory cell region and an error correction circuit; and a memory controller configured to independently provide an off mode signal and an off address to the plurality of memory devices, wherein, during a read operation, each of the plurality of memory devices controls the error correction circuit to selectively perform an error correction operation on an exclusion area in the memory cell region defined by the off address, according to the off mode signal.

The application relates to the chip technical field and discloses a partition unit, a partition, a chip, a network-on-chip implementation method and a medium. The partition unit comprises the following steps: obtaining an operation type and an access address corresponding to a memory access request through a secondary cache, and forwarding the memory access request to a control module of a directory corresponding to the access address when the operation type is a partial write operation; writing request data corresponding to the memory access request into a small-capacity cache through the control module, reading a target partition unit corresponding to the partition unit from a state recording module, generating a listening request according to the memory access request and sending the listening request to the target partition unit, receiving listening data fed back by the target partition unit, merging the listening data and the request data to generate complete data, and writing the complete data into a memory controller. Hardware support for cache consistency can be provided in an artificial intelligence chip with a multi-core architecture, and a network-on-chip implementation scheme supporting cache consistency is provided.

The embodiment of the invention provides a memory device, a memory system, a memory controller and an operation method, and the memory device comprises a memory unit array which comprises a plurality of memory units, and a preset number of memory units form a code word; the peripheral circuit is coupled with the storage unit array and is configured to generate a first boundary voltage and a second boundary voltage according to a first result corresponding to the at least one code word under the target reading voltage; adjusting the target reading voltage for at least one time, and obtaining a corresponding first result under the adjusted target reading voltage after each adjustment; in the adjustment process, the current voltage adjustment direction is changed according to the fact that the target reading voltage after one-time adjustment exceeds the range limited by the first boundary voltage and the second boundary voltage; according to the condition that a first result corresponding to the adjusted target reading voltage meets a preset condition, target valley voltage is determined, and the target valley voltage is used as the reading voltage when the reading operation is executed on the at least one code word.

A memory system includes a non-volatile memory having a plurality of blocks, and a memory controller. The memory controller is configured to set one of writing modes including a first mode of writing a single bit of data per memory cell and a second mode of writing multi bits of data per memory cell as a data writing mode for each of one or more blocks, upon receiving information indicating a size of write data to be written into the non-volatile memory from a host device, determine whether the size exceeds a size of a first free space of the non-volatile memory usable for data writing in the first writing mode, and upon determining that the size of the write data exceeds the size of the first free space, write at least a part of the write data into the non-volatile memory in the second writing mode.

A method for managing data in a non-volatile memory system includes generating, by a randomizer integrated on a die of a memory device, padding data to close a memory block for a data write operation. The padding data is random data. The method includes programming, by a media controller of the memory device, the padding data into specified memory pages in a data block within the memory device. The data block stores user data for the data write operation and the padding data. The method includes executing, by a memory controller and by the media controller, a data integrity scan on a selected memory page of the specified memory pages of the data block. Execution of the data integrity scan includes re-generating, by the randomizer, the padding data and comparing the re-generated padding data with stored padding data sensed from the selected memory page to identify mismatch data.