1441 results about "Interface circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

Methods, apparatus, systems, and articles of manufacture are disclosed for device authentication in a dedicated private network. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to utilize the machine readable instructions to generate first credentials associated with a first network based on second credentials associated with a second network, the first credentials including first location data corresponding to a dedicated private network (DPN), cause a mobile device to program a programmable subscriber identity module (SIM) of the mobile device based on the first credentials, and permit the mobile device to access the DPN based on a determination that second location data corresponding to the mobile device and included with the programmable SIM corresponds to the first location data.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive data from a remote entity for handling by a computing system. The machine-readable instructions further include instructions to instantiate a first TEE and a second TEE. The machine-readable instructions further include instructions to generate log data corresponding to predefined activities of the computing system and to generate system record data of a system log of the computing system at predetermined times. The machine-readable instructions further include instructions to generate first audit data by the first TEE and second audit data by the second TEE. The machine-readable instructions further include instructions to transmit the first and the second audit data to a detection system for data aggregation and anomaly detection.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes interface circuitry, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to generate potential actions to, if implemented, re-assign a client device in the wireless network from a first base station device in the wireless network to another base station device in the wireless network, wherein the re-assignment is to cause the first base station device to stop communications with the client device and is to cause the another base station device to begin communications with the client device; execute a first machine learning model to predict which of the potential actions would satisfy a quality of service (QoS) threshold; execute a second machine learning model to select one of the potential actions predicted to satisfy the QoS threshold; and implement the selected action within the wireless network.

A voltage conversion system includes user interface circuitry disposed on the voltage conversion system. The user interface circuitry is configured to input at least one electrical parameter based on user input. At least one parameter of the at least one electrical parameter comprises a plurality of adjustable values and corresponds to a conductor resistance of electrical conductors coupled to the voltage conversion system. Each adjustable value of the at least one parameter corresponds to a range of two or more values. The voltage conversion system includes conversion circuitry configured to generate an adjusted direct current (DC) voltage from an input DC voltage based on the at least one electrical parameter.

The invention relates to the technical field of encoder communication interface circuits, in particular to a multi-protocol encoder communication interface circuit based on hardware configuration, which comprises a core control and protocol processing module, a hardware configuration and mode recognition module, an RS-485 differential driving and receiving module and an interface protection circuit module. In the invention, the problems that the hardware cost is high, the PCB layout is complicated, the overall size of the system is increased, the types of connectors are diversified and the wiring difficulty is increased due to the fact that an independent physical interface circuit needs to be independently designed for each protocol such as BISS and Tamagawa or a special integrated chip with a solidified factory function is adopted in the existing scheme are thoroughly solved; and meanwhile, the problems that chips need to be replaced or hardware needs to be redesigned and the configuration flexibility is poor in the protocol updating of an existing scheme are solved, the time sequence conflict risk existing in software dynamic switching protocols is avoided, and the defects that a traditional circuit is poor in surge resistance, signal crosstalk is caused and debugging and maintenance are complex are overcome.

A system and method for communicating road condition data. The system and method includes a plurality of inter-changeable housings, including a sensor housing comprising a sensor configured to generate sensor data; a data processing housing comprising a processor configured to receive the sensor data and vehicle-originated data, and apply one or more layers of a machine learning architecture to the sensor data and the vehicle-originated data to generate at least a portion of vehicle instruction data; and a wireless communication housing comprising a wireless interface circuit configured to receive the vehicle-originated data and to transmit the vehicle instruction data generated by the processor.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.

A hardware accelerator includes accelerator processing circuitry to perform a delegated task on behalf of a processor; a control interface circuit to exchange control signals with the processor to configure the accelerator processing circuit to perform the delegated task; a fault state register storage device for storing fault state information, the fault state register storage device being readable by the processor based on an accelerator register read request received from the processor via the control interface circuit; and a control circuit to: detect a failure indication received from the processor via the control interface circuit, the failure indication indicating that a failure accelerator triggered memory access request issued to the processor via the control interface circuit and specifying a target virtual address has encountered an address translation failure; and in response to detecting the fault indication, setting fault state information in the fault state register storage device to indicate information about a memory access request triggered by the fault accelerator encountering the address translation fault.

The invention is applicable to the technical field of automation control, and provides a voltage simulation test system and method of an electromagnetic valve and terminal equipment, the system comprises a parallel interface circuit and a voltage simulation device, and a bidirectional silicon controlled rectifier in the parallel interface circuit is connected in parallel to two ends of a coil of the electromagnetic valve and is used for adjusting an analog voltage value output by the voltage simulation device. The voltage simulation device comprises a power supply adaptive circuit and a control chip; the input end of the power supply self-adaptive circuit is connected with the control chip, the output end of the power supply self-adaptive circuit is connected with the parallel interface circuit, a power supply mode is determined according to the field power supply state of the field circuit where the electromagnetic valve is located, and the power supply mode is sent to the control chip; and the control chip generates a pulse width modulation driving signal according to the power supply mode, and controls the parallel interface circuit according to the pulse width modulation driving signal to perform voltage simulation test on the electromagnetic valve. The system can safely and accurately carry out the voltage simulation test on the premise of not cutting off the original field circuit where the electromagnetic valve is located.

A hardware accelerator comprises accelerator processing circuitry to perform a delegated task on behalf of a processor; control interface circuitry to exchange control signals with the processor to configure the accelerator processing circuitry to perform the delegated task; fault status register storage to store fault status information, the fault status register storage being readable by the processor based on an accelerator register read request received from the processor via the control interface circuitry; and control circuitry to: detect a fault indication received from the processor via the control interface circuitry indicating that a faulting accelerator-triggered memory access request, issued via the control interface circuitry to the processor and specifying a target virtual address, has encountered an address translation fault; and in response to detecting the fault indication, set fault status information in the fault status register storage to indicate information about the faulting accelerator-triggered memory access request that encountered the address translation fault.

The invention relates to the technical field of interface circuits, in particular to a multi-mode switching detection circuit for a Type-C interface, which is used for realizing peripheral type identification and automatic switching between a USB host mode and a DP input mode on a single Type-C interface. The circuit comprises an interface detection unit connected with a Type-C female seat interface, a voltage comparison unit, a main control processor chip, a mode discrimination unit and a control output unit. The voltage comparison unit carries out resistance voltage division and threshold comparison on CC pin voltage, two levels are formed at a detection node and sent to the main control processor chip, and USB equipment and DP source equipment are distinguished by the mode judgment unit. The control output unit controls the USB host power supply control circuit and the DP input chip power supply circuit, establishes a USB data channel in a USB host mode, and establishes a DP-to-video channel in a DP input mode. The circuit realizes rapid peripheral identification and mode automatic switching based on hardware, and is simple in structure, low in cost, high in response speed and high in system stability.

Systems, apparatus, articles of manufacture, and methods are disclosed for virtual execution environments and interface circuitry in time-sensitive networking. An example compute device includes interface circuitry, machine-readable instructions, and at least one programmable circuit to be programmed by the machine-readable instructions. The example at least one programmable circuit is to be programmed execute a first application for a time-sensitive network (TSN) in a first virtual execution environment (VEE) and execute a second application for the TSN in a second VEE. Additionally, the example at least one programmable circuit is to cause first real-time traffic to be sent from the first application to the interface circuitry based on a first schedule and cause second real-time traffic to be sent from the second application to the interface circuitry based on a second schedule such that transmission of the first real-time traffic does not occur at the same time as transmission of the second real-time traffic.

The invention discloses a CAN bus activity detection and wake-up circuit and method, and belongs to the technical field of CAN bus communication, the CAN bus activity detection and wake-up circuit comprises a CAN bus interface circuit, a signal detection and processing circuit and a controller, the input end of the CAN bus interface circuit is connected with a CAN bus; the signal detecting and processing circuit comprises a voltage comparator, the non-inverting input end and the inverting input end of the voltage comparator respectively receive a CANH signal and a CANL signal which are electrically isolated by the CAN bus interface circuit, and the output end of the voltage comparator is connected to a wake-up pin of the controller; the controller is used for monitoring the level state of the wake-up pin, and when the level of the wake-up pin is in an effective state, the electronic equipment is controlled to be switched from the sleep mode to the normal working mode. By introducing an electrical isolation and voltage difference detection mechanism, the problem of false wake-up caused by common-mode interference or bus noise in the prior art is solved, and reliable wake-up under low power consumption is realized.

The invention provides a data processing and output circuit and method for a high-energy particle detection pixel sensor chip, and relates to the technical field of high-energy particle detection, and the method comprises the steps that each data processing unit receives ADC output of multiple channels, and carries out the validity discrimination of the received original data of each channel in a polling mode; effective case information in each data processing unit is summarized through a data integration circuit, and the effective case information is cached into a sparse signal output buffer; the data output interface circuit receives the information in the sparse signal output buffer, judges whether effective information needing to be output exists or not, and reads formatted data if the effective information exists. According to the invention, the output signal of the quantization circuit is discriminated so as to distinguish an effective case and a noise background, only pixel data containing an effective particle hit event is subjected to position correlation and coding, pixels not containing the effective hit event are skipped, and whether the data output interface outputs data to the outside is determined according to whether the effective case exists or not.

An interface circuit includes a first coupler and a first low-pass filter. The first coupler is configured to superimpose a first communication signal on a first power line transmitting a first power supply voltage of a square wave, or extract a first communication signal from a first power line transmitting a first power supply voltage of a square wave on which the first communication signal is superimposed. The first low-pass filter is inserted into the first power line and is connected to the first coupler. The first low-pass filter includes a first inductor at each of both ends of the first low-pass filter.

A system including a mobile communication device configured to communicate with a secure element is disclosed herein. The mobile communication device is equipped with a secure element for improving an authorization process, comprising interface circuitry configured to communicate with a trusted authority, and processing circuitry configured to control the interface circuitry and to receive a signal from the trusted authority. The signal comprises information indicative of a user binding to the secure element.

The invention provides a calibration system and method for a fluxgate current sensor, the system comprises a power supply module, a test tool module and a current clamp clamped on the input hole wall of the fluxgate current sensor, the power supply module is connected with the test tool module, and the test tool module is connected with the current clamp; the test tool module comprises a control circuit, a current source circuit, a multipath controller circuit and an interface circuit, the control circuit is respectively connected with the current source circuit and the multipath controller circuit, and the current source circuit is connected with the current clamp through a calibration interface in the interface circuit; and the multi-path controller circuit is used for being connected with a fluxgate current sensor through a sensor communication interface in the interface circuit. According to the invention, the problems of easy overload of power supply, high current source cost of large current and high precision and the like of the vehicle-mounted fluxgate current sensor in test calibration due to the characteristics (such as small internal resistance of a magnetic probe coil and large starting current) are solved.

A semiconductor memory device includes a physical region, a direct access region and a power manager. The direct access region interfaces with an external test device directly. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage and a power supply voltage, and provides the internal power supply voltage to the direct access region. The power manager provides the second power supply voltage to the physical region. The direct access region includes a test interface circuit and the test interface circuit, in a direct access mode, generates an internal clock signal based on an external clock signal, generates an internal test clock signal by latching a test control signal received from the external test device based on the internal clock signal and provides the internal test control signal to the physical region.

The present disclosure provides controllers, hosts, methods of operating a controller, and methods of operating a host. An example controller includes a controller processor, an interface circuit and a buffer. The interface circuit is coupled to the buffer. Wherein the buffer is configured to buffer log information generated during the running of the firmware by the controller processor. The interface circuit is configured to: obtain the log information generated during the running of the firmware from the buffer, output the log information to a host.

An integrated circuit (IC) package including a first chiplet, a second chiplet, and a communication interface circuit coupling the first and second chiplets is disclosed. The communication interface circuit comprises main lanes wherein a first portion of which communicates information from the first chiplet to the second chiplet (i.e., first direction) and wherein a second portion of which communicates information from the second chiplet to the first chiplet (i.e., second direction). The communication interface circuit also comprises a plurality of redundant lanes wherein each of the redundant lanes are dynamically configurable to communicate in one of a first and a second direction.

An interface circuit according to the present invention comprises: a source clock reception circuit that receives a source clock; and a plurality of reception lanes that each receive reception data. Each of the plurality of reception lanes includes: a data line that transmits the reception data; a sampling clock line that transmits a sampling clock generated on the basis of the source clock; a sampler circuit that samples the reception data on the basis of the sampling clock; and an eye-monitoring circuit that includes a TDC circuit and is provided in parallel with the sampler circuit with respect to the data line and the sampling clock line. On the basis of a reference clock generated on the basis of the source clock, the TDC circuit monitors a TDC input signal generated on the basis of the reception data or the sampling clock and generates characteristic information of the reference clock and the reception data.

Aspects described herein include devices and methods for an envelope tracking power supply. In some aspects, the envelope tracking power supply includes an envelope signal input port, an output power port, an input interface circuit coupled to the envelope signal input port, sensing and conditioning circuitry, and amplifier circuitry coupled between the input interface circuit and the sensing and conditioning circuitry, the amplifier circuitry having one or more control inputs. The envelope tracking power supply additionally includes switcher circuitry coupled to the output of the sensing and conditioning circuitry, and the output power port, and the supply further includes output filter circuitry coupled to the output power port and machine learning circuitry configured to receive state tracking data for performance of a transmit power amplifier (PA) that receives power via the output power port.

The invention provides a multi-protocol configurable interface circuit. The multi-protocol configurable interface circuit comprises a plurality of channel modules, a plurality of counter modules, an input / output module and a configuration register, the channel module comprises a state machine, a shift register and a cache module. The configuration register obtains configuration information through the system bus, and the configuration information comprises which protocol is selected. The counter module generates a shift signal required by a shift register in the channel module according to the configuration information; the input and output module selects the corresponding pins according to the configuration information and determines the function of each pin; and the channel module determines the mode of each channel and the required state of the state machine according to the configuration information to complete data transmission of the selected protocol. According to the invention, a hardware design which focuses on realizing clock and data transmission by matching a state machine state transition and a shift register with a cache module is adopted, so that software intervention and CPU occupation are reduced, and the overall efficiency is improved; hardware resources are reduced, and hardware flexibility is improved.

A system with an interface for remote memory. In some embodiments, the system includes: an interface circuit having: a first interface, configured to be connected to a processing circuit; and a second interface, configured to be connected to memory, the first interface including a cache coherent interface, and the second interface being different from the first interface.

An apparatus comprising processing circuitry configured to generate an instruction for configuring a hardware accelerator to perform a task. The instruction comprises a predefined set of fields comprising a control field indicative of a selected set of fields of the predefined set of fields to be provided to the hardware accelerator to configure the hardware accelerator to perform the task. The apparatus comprises accelerator control interface circuitry configured to exchange messages, each with a size less than or equal to a predefined size, with the hardware accelerator. To configure the hardware accelerator to perform the task, the accelerator control interface circuitry is configured to send the selected set of fields to the hardware accelerator, using a set of command messages with a combined size greater than the predefined size. The application further relates to a hardware accelerator.