2863 results about "Interface circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

An apparatus for end-to-end text-to-speech synthesis is provided. The apparatus comprises input interface circuitry configured to receive first input data indicative of a phoneme and second input data indicative of a first target duration for the phoneme. The apparatus further comprises processing circuitry configured to, using a trained machine-learning model, map the phoneme to a state using an encoder sub-model of the trained machine-learning model, estimate a second target duration for the phoneme based on the state and determine an attention weight based on the first target duration and the second target duration. The processing circuitry is further configured to map the state to audio data based on the attention weight using a decoder sub-model of the trained machine-learning model, wherein the audio data are indicative of an audio waveform representing speech.

Methods and apparatus to determine machine learning (ML) configurations for classifying malware are disclosed. An example server comprises interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a computing parameter associated with a computing device, the computing device communicatively coupled to the server, select a ML model to deploy on the computing device based on the computing parameter, determine a configuration of the ML model based on the computing parameter, deploy the ML model to the computing device, and cause the deployed ML model to classify a sample as clean or malicious, the sample received at the computing device.

Systems, apparatus, articles of manufacture, and methods to self-guardrail large language model responses are disclosed. An example apparatus includes interface circuitry, instructions, and programmable circuitry to at least one of execute or instantiate the instructions to access a first response message provided by a first large language model, the first response message generated based on an initial prompt, cause a second large language model to determine the first response message is inappropriate, modify the initial prompt to create a modified prompt, and provide the modified prompt to the first large language model to trigger generation of a second response message.

Systems, apparatus, articles of manufacture, and methods to utilize cached generative artificial intelligence responses are disclosed. An example apparatus includes interface circuitry to access a request to a generative artificial intelligence model, computer readable instructions, and programmable circuitry to at least one of execute or instantiate the instructions to replace a named entity within the request with a generic tag to generate a modified request, tokenize the modified request to create an array of tokens, detect a similar prior request based on the array of tokens, and after detection of the similar prior request, cause output of a cached response to the request without execution of the generative artificial intelligence model.

The invention discloses a high-integration-level matrix type magnetic sensing chip structure and circuit and a manufacturing method thereof, and belongs to the technical field of semiconductor devices, the chip structure comprises a plurality of matrix elements, a switch matrix and a rear-end interface circuit, and each matrix element comprises a cross-shaped horizontal Hall element and a switch device; the switch matrix is composed of switch devices in matrix elements; the cross-shaped horizontal Hall element matrix is an N * M Hall matrix element formed by an integrated 1 * M Hall element matrix in each row; according to the invention, the structure and the circuit of the matrix type magnetic sensing chip which can be used for statically and dynamically measuring multi-dimensional magnetic field distribution in real time in severe environments such as high temperature, high pressure and high radiation are innovated and manufactured; dynamic and static measurement in a multi-dimensional magnetic field space can be achieved, error compensation is carried out through a circuit, it is ensured that the chip can stably work in the high-temperature, high-pressure and high-radiation environment, and it can be ensured that the chip has high linearity, sensitivity and accuracy.

A system and method, including a vehicle having at least one network zone; a converged network device (CND) interposed between the at least one network zone and at least one of an external communication portal or a first external device, the CND including a policy manager circuit structured to interpret a policy comprising a network regulation description, wherein the policy is communicated to the CND from a second external device; a configuration circuit structured to configure a gatekeeper interface circuit in response to the policy; and the gatekeeper interface circuit, wherein the gatekeeper interface circuit is structured to regulate communications between end points of the at least one network zone and the at least one of the external communication portal or the first external device.

A system and method, including a vehicle having a first network zone and a second network zone of a different type than the first network zone; a policy manager circuit structured to interpret a policy comprising an external data routing description and an external data service description; a configuration circuit structured to configure a gatekeeper interface circuit in response to the external data routing description and the external data service description; the gatekeeper interface circuit interposed between the first network zone and at least one external communication portal selectively couplable to an external device; and wherein the gatekeeper interface circuit is structured to regulate communications between end points of the first network zone and the at least one external communication portal, and to regulate communications between end points of the second network zone and the at least one external communication portal.

Systems, apparatus, articles of manufacture, and methods are disclosed to evict tokens from a key value cache. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: determine score history values for tokens based on attention scores associated with the tokens, wherein a token is a numerical representation of text, after a number of tokens present in the key value cache exceeds a threshold number of tokens, compute group importance scores for groups of tokens based on score history values of the tokens in the groups of tokens, identify low-ranked groups of tokens having lowest group importance scores, the low-ranked groups of tokens associated with an eviction range in the key value cache, and remove an identified low-ranked group of tokens from the eviction range of the key value cache.

An example system includes a vehicle having a first network zone and a second network zone of a different type than the first network zone and a converged network device (CND) interposed between the first network zone and the second network zone. The CND includes a policy manager circuit structured to interpret a policy comprising a network regulation description and an external communication permission value; a configuration circuit structured to configure at least one network interface circuit in response to the policy and to configure at least one gatekeeper interface circuit in response to the policy; the at least one network interface circuit structured to regulate communications between end points of the first and second network zone; and the gatekeeper interface circuit configured to regulate communications between end points of at least one of the first network zone or the second network zone and an external device.

An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to sparsify a base model of a foundation model to generate a sparse base model, apply a neural low-rank adapter search to the sparse base model, and output a fine-tuned base model based on application of the neural low-rank adapter search to the sparse base model.

The invention belongs to the field of circuits, and particularly relates to an analog front-end circuit for capacitance detection and a current calibration method, the analog front-end circuit comprises a driving circuit, a to-be-detected capacitor, a chip signal input and output interface circuit, a current amplification circuit or charge amplification circuit, an integrating circuit and an analog-to-digital converter which are connected in sequence; the leakage current measurement and calibration controller is used for receiving a signal of the analog-to-digital converter and outputting a control signal for calibrating the leakage current to the current calibration circuit; the output end of the current calibration circuit is connected with the input end of the integrating circuit, and the current calibration circuit is used for adjusting the output of the current calibration circuit to calibrate the magnitude of the current input into the integrating circuit when receiving the control signal for calibrating the leakage current. According to the application, the leakage current measurement and calibration controller is arranged at the output end of the integrating circuit, the leakage current of the analog front-end circuit is measured, and the control signal is output to adjust the output of the current calibration circuit, so that the magnitude of the current input into the integrating circuit is calibrated, and errors caused by imbalance of the leakage current and the current of the amplifying circuit can be compensated.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

Methods, apparatus, systems, and articles of manufacture are disclosed for device authentication in a dedicated private network. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to utilize the machine readable instructions to generate first credentials associated with a first network based on second credentials associated with a second network, the first credentials including first location data corresponding to a dedicated private network (DPN), cause a mobile device to program a programmable subscriber identity module (SIM) of the mobile device based on the first credentials, and permit the mobile device to access the DPN based on a determination that second location data corresponding to the mobile device and included with the programmable SIM corresponds to the first location data.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

The invention discloses an air blowing and suction integrated fan and a control method thereof, and relates to the technical field of fans. The fan comprises fan blades, a shell, a control motor and a ventilation baffle. The control motor is in control connection with the ventilation baffle, and the control motor is used for switching air blowing and suction modes of the fan by changing the angle of the ventilation baffle; an air suction opening and an air blowing opening are formed in the shell; the exhaust inlet and the blow-off nozzle are blocked and separated by a clapboard; the shell and the ventilation baffle plate divide the air suction opening into an inner air suction opening and an outer air suction opening; the air blowing opening is divided into an inner air blowing opening and an outer air blowing opening through the shell and the ventilation baffle. The inner air suction opening and the inner air blowing opening are communicated with an automobile seat ventilation system; the outer air suction opening and the outer air blowing opening are communicated with the outside atmosphere; the fan circuit module comprises a fan interface circuit sub-module, a voltage reduction sub-module, a PWM sub-module, an overvoltage protection sub-module, a fan driving sub-module, a control motor driving sub-module, an MCU sub-module and a fan driving feedback sub-module. Switching of the air blowing mode and the air suction mode of the fan can be achieved.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to obtain a first set of data formats. The first set of data formats comprises data formats that are available to an attestation environment of a confidential computing environment for generation of attestation evidence of a confidential computing environment. The machine-readable instructions further comprise instructions to obtain a second set of data formats. The second set of data formats comprises data formats of attestation evidence that are available to an attestation verifier. The machine-readable instructions further comprise instructions to determine an optimal data format for attestation evidence of a confidential computing environment based on the first set of data formats and the second set of data formats and to generate attestation evidence of the confidential computing environment in the determined optimal data format.

Systems, apparatus, articles of manufacture, and methods are disclosed for aliasing scopes in access tokens. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to detect a request to create an identity to access an online resource, the message including at least one scope assignment associated with a user of the computing device, determine that an alias has not been created for the at least one scope assignment, the alias to represent two more scopes assigned to the user, and generate the alias for the scope assignment, the alias having less characters than the scope assignment.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

Embodiments are directed to an integrated circuit with multiple dies connected in a die-to-die (D2D) configuration. The integrated circuit can include a first die and a second die connected to the first die via a D2D interface circuit in the D2D configuration forming a D2D structure with the first die. The D2D interface can connect a first plurality of superlanes of the first die with a second plurality of superlanes of the second die for streaming data between the first die and the second die along a first direction or a second direction orthogonal to the first direction.

A communication interface circuit supporting a communication link change and a method of operating the same, the communication interface circuit including: a protocol layer circuit generating packet data based on input data; and a physical layer circuit that encodes the packet data to output a transmission state, and drives a data channel including a plurality of three-phase line links based on the transmission state, where the physical layer circuit may include an encoder that encodes the packet data to output the transmission state. The encoder calculates a transmission state based on a preorder state output from the encoder within a previous unit interval, a symbol mapped to the packet data, and a control code, and wherein the control code indicates a coding change based on a coupling relationship of the plurality of three-phase line links. A communication interface circuit stably transmits data.

The invention discloses a charging pile testing system and method based on energy feedback and photovoltaic energy storage, and belongs to the technical field of charging pile testing. The system comprises a power grid power supply interface module, a photovoltaic assembly module, an energy storage module, a charging pile interface circuit module, a multi-mode test load module, an energy feedback module, a central control module and a data acquisition and analysis module. According to the system, the technical effects of efficient energy feedback, intelligent collaborative management of light storage and charging and multi-mode dynamic scheduling in the charging pile testing process are achieved.

Disclosed in the present invention is a high-dynamic capacitive digital microphone system based on electrostatic force feedback. The system comprises an MEMS microphone and an interface circuit chip thereof, wherein the interface circuit chip comprises a charge pump, an analog front end, an analog-to-digital conversion circuit, an amplitude detection module, an amplitude adjustment control module and a pulse density modulation module. In the present invention, the characteristic of the sensitivity being able to be adjusted by means of changing a bias voltage by a capacitive sensor is used, and a charge pump with an adjustable output voltage is used to provide electrostatic force feedback, thereby further expanding the adjustable range of a front-end gain, and also reducing requirements for the noise performance of a readout circuit. Therefore, the system in the present application has the characteristics of high dynamic range and high-precision quantization.

An example device includes a vehicle having a network comprising a plurality of end points, and a controller including: an interface circuit structured to interpret a customization sequence description and a trigger condition description, wherein the customization sequence description comprises a specific order of actions, and the trigger condition description comprises one or more environmental, location-based, or time-based conditions; a sequence management circuit structured to provide a trigger detection plan and a sequence execution plan in response to the customization sequence description and the trigger condition description; and a sequence execution circuit structured to determine a trigger event value in response to the trigger detection plan, and to provide a customization command in response to the trigger event value and the sequence execution plan. At least one end point is responsive to the customization command to implement an automated vehicle response based on the customization sequence description and detected conditions.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes memory control circuitry for controlling at least one memory die of a first memory type. A die-to-die (D2D) interface circuit couples to a host IC chiplet. The D2D interface circuit includes input / output (I / O) circuitry for coupling to multiple signaling lanes for transferring information packets with the host IC chiplet.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive data from a remote entity for handling by a computing system. The machine-readable instructions further include instructions to instantiate a first TEE and a second TEE. The machine-readable instructions further include instructions to generate log data corresponding to predefined activities of the computing system and to generate system record data of a system log of the computing system at predetermined times. The machine-readable instructions further include instructions to generate first audit data by the first TEE and second audit data by the second TEE. The machine-readable instructions further include instructions to transmit the first and the second audit data to a detection system for data aggregation and anomaly detection.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

A display driving circuit includes a pixel circuit array including a plurality of pixel circuits arranged in a matrix, each of the plurality of pixel circuits storing received pixel data and providing a driving current corresponding to the pixel data to an emission device, an interface circuit configured to receive a partial update command and partial update data from a host, a row driving circuit configured to provide write clock signals to first pixel circuits included in one or more update row of the pixel circuit array, based on a update area signal generated based on update area information included in the partial update command, and a data driving circuit configured to provide update pixel data to each of the update pixel circuits among the first pixel circuits, based on the partial update data.