2122 results about "Interface circuits" patented technology

An interface circuit includes a reference voltage generation circuit to generate a reference voltage, a differential voltage signal generation circuit to convert send data input in sending data into a pair of differential voltage signals and output the pair of differential voltage signals based on the reference voltage generated by the reference voltage generation circuit, a receiver to convert a pair of differential voltage signals input in receiving data and output received data, and a receiver test circuit to perform a sensitivity test of the receiver, the receiver test circuit having a resistance circuit to generate a pair of differential voltage signals having a potential difference being necessary for the sensitivity test of the receiver.

An apparatus for end-to-end text-to-speech synthesis is provided. The apparatus comprises input interface circuitry configured to receive first input data indicative of a phoneme and second input data indicative of a first target duration for the phoneme. The apparatus further comprises processing circuitry configured to, using a trained machine-learning model, map the phoneme to a state using an encoder sub-model of the trained machine-learning model, estimate a second target duration for the phoneme based on the state and determine an attention weight based on the first target duration and the second target duration. The processing circuitry is further configured to map the state to audio data based on the attention weight using a decoder sub-model of the trained machine-learning model, wherein the audio data are indicative of an audio waveform representing speech.

Methods and apparatus to determine machine learning (ML) configurations for classifying malware are disclosed. An example server comprises interface circuitry, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to determine a computing parameter associated with a computing device, the computing device communicatively coupled to the server, select a ML model to deploy on the computing device based on the computing parameter, determine a configuration of the ML model based on the computing parameter, deploy the ML model to the computing device, and cause the deployed ML model to classify a sample as clean or malicious, the sample received at the computing device.

Systems, apparatus, articles of manufacture, and methods to utilize cached generative artificial intelligence responses are disclosed. An example apparatus includes interface circuitry to access a request to a generative artificial intelligence model, computer readable instructions, and programmable circuitry to at least one of execute or instantiate the instructions to replace a named entity within the request with a generic tag to generate a modified request, tokenize the modified request to create an array of tokens, detect a similar prior request based on the array of tokens, and after detection of the similar prior request, cause output of a cached response to the request without execution of the generative artificial intelligence model.

The invention provides an artificial intelligence-based interface circuit design method, which comprises the following steps of: S1, acquiring an RTL code for describing a logic structure of a digital circuit, and generating a digital circuit layout according to the RTL code by utilizing a preset neural network model; s2, acquiring a preset process library and design parameters of the analog circuit, and generating an analog circuit layout by using a preset neural network model according to the process library and the design parameters of the analog circuit; and S3, fusing the digital circuit layout and the analog circuit layout by using a preset neural network model to obtain the layout of the interface circuit.

Methods, apparatus, systems, and articles of manufacture are disclosed for device authentication in a dedicated private network. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to utilize the machine readable instructions to generate first credentials associated with a first network based on second credentials associated with a second network, the first credentials including first location data corresponding to a dedicated private network (DPN), cause a mobile device to program a programmable subscriber identity module (SIM) of the mobile device based on the first credentials, and permit the mobile device to access the DPN based on a determination that second location data corresponding to the mobile device and included with the programmable SIM corresponds to the first location data.

The invention relates to the technical field of computer hardware and network communication, in particular to a high-speed I / O (input / output) virtualization server based on an FPGA (field programmable gate array) and a remote forwarding method.The high-speed I / O virtualization server comprises an FPGA chip, a network processing unit, an I / O protocol processing unit, a protocol conversion and scheduling unit, a time sequence and transaction management unit and a data buffering and flow control unit are integrated in the FPGA chip; the optical fiber Ethernet interface module comprises a physical layer interface and an MAC layer processing and network configuration interface; the local I / O interface module comprises a USB interface circuit, a serial port interface circuit, a PCIe interface circuit and an interface expansion connector; the power supply and monitoring module comprises a multi-path power supply management system, a state monitoring and diagnosis system and an LED indication system; according to the self-adaptive Baud rate detection circuit, the Baud rate can be accurately locked under the condition that data with less than two characters is received, the number of data bits, the type of a check bit and the length of a stop bit are automatically identified, and compared with a traditional microcontroller scheme, the self-adaptive Baud rate detection circuit has higher precision and higher detection speed.

A storage device includes a non-volatile memory and a storage controller, wherein the storage controller includes a cache memory storing some of data stored in the non-volatile memory, an interface circuit receiving, from a first external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory, provide a second request including the source address to the external storage device, and receive, from the external storage device in response to the second request, a response including first data corresponding to the source address, an address translation circuit generating a physical address of a first type based on the destination address, and a cache controller updating a cache area indicated by the physical address of the first type based on the cache update information.

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

Embodiments are directed to an integrated circuit with multiple dies connected in a die-to-die (D2D) configuration. The integrated circuit can include a first die and a second die connected to the first die via a D2D interface circuit in the D2D configuration forming a D2D structure with the first die. The D2D interface can connect a first plurality of superlanes of the first die with a second plurality of superlanes of the second die for streaming data between the first die and the second die along a first direction or a second direction orthogonal to the first direction.

The invention discloses a charging pile testing system and method based on energy feedback and photovoltaic energy storage, and belongs to the technical field of charging pile testing. The system comprises a power grid power supply interface module, a photovoltaic assembly module, an energy storage module, a charging pile interface circuit module, a multi-mode test load module, an energy feedback module, a central control module and a data acquisition and analysis module. According to the system, the technical effects of efficient energy feedback, intelligent collaborative management of light storage and charging and multi-mode dynamic scheduling in the charging pile testing process are achieved.

Disclosed in the present invention is a high-dynamic capacitive digital microphone system based on electrostatic force feedback. The system comprises an MEMS microphone and an interface circuit chip thereof, wherein the interface circuit chip comprises a charge pump, an analog front end, an analog-to-digital conversion circuit, an amplitude detection module, an amplitude adjustment control module and a pulse density modulation module. In the present invention, the characteristic of the sensitivity being able to be adjusted by means of changing a bias voltage by a capacitive sensor is used, and a charge pump with an adjustable output voltage is used to provide electrostatic force feedback, thereby further expanding the adjustable range of a front-end gain, and also reducing requirements for the noise performance of a readout circuit. Therefore, the system in the present application has the characteristics of high dynamic range and high-precision quantization.

An example device includes a vehicle having a network comprising a plurality of end points, and a controller including: an interface circuit structured to interpret a customization sequence description and a trigger condition description, wherein the customization sequence description comprises a specific order of actions, and the trigger condition description comprises one or more environmental, location-based, or time-based conditions; a sequence management circuit structured to provide a trigger detection plan and a sequence execution plan in response to the customization sequence description and the trigger condition description; and a sequence execution circuit structured to determine a trigger event value in response to the trigger detection plan, and to provide a customization command in response to the trigger event value and the sequence execution plan. At least one end point is responsive to the customization command to implement an automated vehicle response based on the customization sequence description and detected conditions.

It is provided an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive data from a remote entity for handling by a computing system. The machine-readable instructions further include instructions to instantiate a first TEE and a second TEE. The machine-readable instructions further include instructions to generate log data corresponding to predefined activities of the computing system and to generate system record data of a system log of the computing system at predetermined times. The machine-readable instructions further include instructions to generate first audit data by the first TEE and second audit data by the second TEE. The machine-readable instructions further include instructions to transmit the first and the second audit data to a detection system for data aggregation and anomaly detection.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

A display driving circuit includes a pixel circuit array including a plurality of pixel circuits arranged in a matrix, each of the plurality of pixel circuits storing received pixel data and providing a driving current corresponding to the pixel data to an emission device, an interface circuit configured to receive a partial update command and partial update data from a host, a row driving circuit configured to provide write clock signals to first pixel circuits included in one or more update row of the pixel circuit array, based on a update area signal generated based on update area information included in the partial update command, and a data driving circuit configured to provide update pixel data to each of the update pixel circuits among the first pixel circuits, based on the partial update data.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

A communication device that accommodates a radio terminal in a radio access network, the communication device includes an interface circuit configured to communicate with a second communication device, a storage configured to store control information that includes a first profile that represents a function provided by the communication device and a communication parameter that corresponds to the first profile, and processor circuitry configured to edit the control information, wherein the interface circuit transmits the first profile to the second communication device, and receives a second profile, the processor circuitry edits the control information based on the second profile, the interface circuit transmits the edited control information to the second communication device, and when the second communication device determines that a communication parameter related to the function provided by the second communication device is supported by the communication device, the communication device starts a communication service.

The invention relates to the technical field of communication data acquisition, in particular to a self-adaptive interface circuit of a communication interface and a regulation and control method, and the self-adaptive interface circuit comprises three communication interface transmitting ends, three communication interface receiving ends, an RS232 bus judgment circuit and a TTL (Transistor-Transistor Logic) level-RS485 bus judgment circuit, according to the method, the highest priority judgment is carried out based on a logic sequence, and if the RS232 bus judgment circuit judges that the bus is an RS232 bus, RS232 communication is carried out; if it is judged that the bus is not the RS232 bus, the RS232 communication is forbidden, and second priority judgment is carried out; second priority judgment is carried out through a TTL level-RS485 bus judgment circuit, and if a TTL level is judged, TTL level communication is carried out and RS485 communication is forbidden; and if the TTL level is judged to be non-TTL level, the bus is an RS485 bus. Automatic compatibility of three communication interfaces (RS485, RS232 and TTL levels) is realized, manual participation is not needed, the types of the communication interfaces do not need to be concerned about for a control side, and the universality and interchangeability of the photovoltaic inverter are improved.

The invention discloses a multi-port charging selection circuit and method.According to the multi-port charging selection circuit, a switch switching module, a PD protocol module and a main control module are arranged in an interface module with a multi-interface circuit, and the main control module conducts charging according to signals of the interface module; the switch switching module is controlled to enable any interface circuit of the interface module to be connected with the PD protocol module; therefore, any interface circuit is selected from the interface modules to be connected with the PD protocol module, rapid charging is achieved, multiplexing of the PD protocol module is achieved, resources of the PD protocol module are saved, the size and internal space design of the electric equipment are reduced, the structure of the electric equipment is simplified, the circuit setting complexity is reduced, and the power utilization efficiency is improved. And thus, the stability and the use safety of the electric equipment are improved.

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes interface circuitry, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to generate potential actions to, if implemented, re-assign a client device in the wireless network from a first base station device in the wireless network to another base station device in the wireless network, wherein the re-assignment is to cause the first base station device to stop communications with the client device and is to cause the another base station device to begin communications with the client device; execute a first machine learning model to predict which of the potential actions would satisfy a quality of service (QoS) threshold; execute a second machine learning model to select one of the potential actions predicted to satisfy the QoS threshold; and implement the selected action within the wireless network.

The invention provides a protocol interface circuit switching method for data acquisition and transmission of an unmanned ship, which belongs to the technical field of protocol interface circuit switching, and is characterized in that a multiplexing analog switch circuit and a standardized level conversion chip circuit are integrated in a circuit for data acquisition and transmission of the unmanned ship to realize seamless switching of communication ports among RS232, RS485 and TTL (Transistor-Transistor Logic); on the premise that navigation and operation of the unmanned ship do not need to be interrupted, a proper communication standard and a proper data transmission path are dynamically selected according to actual requirements. A multiplexing analog switch and a standardized level conversion chip are integrated in the circuit, so that seamless rapid switching among the RS232, the RS485 and the TTL can be realized. On the premise that navigation and operation of the unmanned ship do not need to be interrupted, a proper communication standard and a proper data transmission path can be dynamically selected according to actual requirements.

The invention relates to the field of fan control, in particular to a fan wired integrated control system. The control panel is provided with a plurality of cooling fans, the independent control box is electrically connected with the control panel through a cable, the control box comprises a multi-path RD signal processing module, a dial switch array, a state indication module, a fault output interface, a programmable speed regulation module and the like, and the control box is further provided with an RS485 communication interface and the like. A physical switch of the dial switch array correspondingly controls the state monitoring function of the cooling fan, the double-color LED array indicates the running state of the fan, and a fault output interface is uploaded to an upper computer through an interface circuit when the fan breaks down. Effective control and state monitoring of the fan are achieved, the state of the fan can be adjusted according to actual requirements, the effects of electrical isolation, rapid fault response and the like are achieved, meanwhile, the communication rate is adjustable, and the system adapts to different application scenes.

A logic die and a semiconductor device including the same are provided. The semiconductor device includes a logic die including a memory controller, an interface circuit, and a plurality of TSVs arranged in a TSV region. A plurality of memory dies are vertically stacked on the logic die and connected to the plurality of TSVs. The memory controller operates in a first voltage domain, and the plurality of memory dies operate in a second voltage domain. The interface circuit includes a plurality of TSV circuit blocks connected to the plurality of TSVs. Each TSV circuit block is configured to switch a voltage level of a signal transmitted via a corresponding TSV between a first voltage level in a first voltage domain and a second voltage level in a second voltage domain.

A voltage conversion system includes user interface circuitry disposed on the voltage conversion system. The user interface circuitry is configured to input at least one electrical parameter based on user input. At least one parameter of the at least one electrical parameter comprises a plurality of adjustable values and corresponds to a conductor resistance of electrical conductors coupled to the voltage conversion system. Each adjustable value of the at least one parameter corresponds to a range of two or more values. The voltage conversion system includes conversion circuitry configured to generate an adjusted direct current (DC) voltage from an input DC voltage based on the at least one electrical parameter.

The invention relates to the technical field of encoder communication interface circuits, in particular to a multi-protocol encoder communication interface circuit based on hardware configuration, which comprises a core control and protocol processing module, a hardware configuration and mode recognition module, an RS-485 differential driving and receiving module and an interface protection circuit module. In the invention, the problems that the hardware cost is high, the PCB layout is complicated, the overall size of the system is increased, the types of connectors are diversified and the wiring difficulty is increased due to the fact that an independent physical interface circuit needs to be independently designed for each protocol such as BISS and Tamagawa or a special integrated chip with a solidified factory function is adopted in the existing scheme are thoroughly solved; and meanwhile, the problems that chips need to be replaced or hardware needs to be redesigned and the configuration flexibility is poor in the protocol updating of an existing scheme are solved, the time sequence conflict risk existing in software dynamic switching protocols is avoided, and the defects that a traditional circuit is poor in surge resistance, signal crosstalk is caused and debugging and maintenance are complex are overcome.

A system and method for communicating road condition data. The system and method includes a plurality of inter-changeable housings, including a sensor housing comprising a sensor configured to generate sensor data; a data processing housing comprising a processor configured to receive the sensor data and vehicle-originated data, and apply one or more layers of a machine learning architecture to the sensor data and the vehicle-originated data to generate at least a portion of vehicle instruction data; and a wireless communication housing comprising a wireless interface circuit configured to receive the vehicle-originated data and to transmit the vehicle instruction data generated by the processor.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.