11861results about "Electronic switching" patented technology

The invention discloses a self-adaptive nanosecond driving protection method for a high-voltage IGBT power module. The method comprises the steps that data such as high-voltage side voltage, collector current, grid voltage and junction temperature are collected and preprocessed, and standardized feature vectors are obtained; extracting statistical features, frequency domain features and trend features to obtain a comprehensive feature vector; density clustering is carried out based on historical fault data, and an extreme value model is established by using generalized Pareto distribution to generate an optimized threshold value; constructing a time sequence feature matrix, predicting a fault probability by adopting a time sequence convolutional network and a long-short term memory network, and generating a protection strategy parameter; and generating an optimal driving waveform and a control signal, and updating parameters according to an actual response effect. According to the invention, predictive protection and nanosecond-level precise control of faults are realized, and the reliability and performance of the high-voltage IGBT module are remarkably improved.

The invention relates to an optically controllable switching device having a first and second line section, between which an optically controllable switch (T2) is inserted, and having a sensor element (SE). The optically controllable switch (T2) disconnects or connects depending on an optical switching signal (SB), whether the switch is "on" or "off". The sensor element (SE) comprises a carrier material (TM) with crystals comprising one or more paramagnetic centers (NV). When irradiated with pump radiation (LB), the sensor element (SE) emits fluorescent radiation (FL) which depends on the magnetic flux density B at the location of the sensor element (SE). A line current (I LTG) in the first line section of the line (LTG) generates a magnetic field with a flux density B which, with sufficient current strength, influences the fluorescent radiation (FL) from one or more paramagnetic centers (NV). The optically controllable switching device has first means (LWL1, PL1, LIV) for irradiating the one or more paramagnetic centers (NV) with pump radiation (LB) and second means (LWL2, F1, PD, LIV) for detecting and separating the fluorescent radiation (FL) and for detecting a measured value signal which depends on the intensity of the fluorescent radiation (FL) and / or on the phase shift of the modulation signal of the temporal profile of the intensity of the fluorescent radiation (FL). The optically controllable switching device has third means (LIV) for generating an optical switching signal (SB) and for controlling the state of the optically controllable switch (T2) using this optical switching signal (SB).The optical switching signal (SB) depends on the intensity of the fluorescence radiation (FL) and / or on the phase shift of the modulation signal of the temporal course of the intensity of the fluorescence radiation (FL).

The present invention discloses an integrated circuit chip with an address code, a key, and a mechanical keyboard. The integrated circuit chip contains a programmable address code, integrates a magnetic induction circuit, a GRB magic color drive circuit, and includes a power pin, a ground pin, and a data pin. The power pins of n integrated circuit chips are connected in parallel to share a power network VCC, the ground pins are connected in parallel to share a ground network GND, and the data pins are connected in parallel to share a data line network DIO connected to an MCU, and data information is transmitted on the data line network DIO. Another integrated circuit chip with an address code only requires a power network VCC and a ground network GND, and data information is modulated and transmitted on the power network, which greatly saves wiring space, reduces the difficulty of PCB design, and exponentially reduces the number of electronic components. In addition, a variety of different customized code sending methods and working modes are provided, making its application simpler, more efficient, and more reliable.

A transient voltage surge protection circuit includes a discharge transistor having a drain coupled to a first point of a voltage input bus, and a source coupled to ground; an RC string having a first capacitor and a first resistor coupled in series; a first charge transistor having a drain coupled to the drain of the discharge transistor, a source coupled to the gate of the discharge transistor, and a gate coupled to a mid-point between the first capacitor and the first resistor; a second charge transistor having a drain coupled to the drain of the discharge transistor and a gate coupled to the gate of the first charge transistor; a Zener diode string coupled to a second point of the voltage input bus and coupled to a third and fourth resistors in series. A midpoint between the third and fourth resistors is coupled to the second resistor.

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention relates to a simple and reliable touch control switch. The simple and reliable touch control switch consists of a 12-V direct-current power supply, a one-way silicon controlled rectifier 1 (SCR1) trigger circuit, a one-way silicon controlled rectifier 2 (SCR2) trigger circuit, a relay control circuit and a load RL circuit. A conventional mechanical self-locking rocker switch or a toggle switch has the defects that actions are mechanical, operating actions are different because of persons, a contact is easy to jitter, a contact is easy to ablate, abrade and the like. The touch control switch is realized by only using a small number of common components and two touch metal pieces, namely an on-load circuit is switched on by touching a touch electrode once, and an off-load circuit is switched off by touching the touch electrode once. The overall touch control switch is made of discrete components, and strong electricity can be effectively isolated from weak electricity through a relay, so that the power supply of a load can use alternating current and also can use direct current. Therefore, the touch control switch has a certain function in the field of household appliances, industrial automation, and optical, mechanical and electrical integration.

The invention relates to a purely optical fuse with a first and second line section, between which an optically controllable switch (T2) is inserted, and with a sensor element (SE). The sensor element (SE) comprises a carrier material (TM) with crystals comprising one or more paramagnetic centers (NV). When irradiated with pump radiation (LB), the sensor element (SE) emits fluorescent radiation (FL) that depends on the magnetic flux density B at the location of the sensor element (SE). A line current (I LTG) in the first line section of the line (LTG) generates a magnetic field with a flux density B which, with sufficient current strength, influences the fluorescence radiation (FL) from one or more paramagnetic centers (NV). The optically controllable switching device has first means (LWL1, PL1, LIV) for irradiating the one or more paramagnetic centers (NV) with pump radiation (LB) and second means (LWL2, F1, PD, LIV) for detecting and separating the fluorescence radiation (FL) and for detecting measured values which depend on the intensity of the fluorescence radiation (FL) and / or on the phase shift of the modulation signal of the temporal progression of the intensity of the fluorescence radiation (FL). The purely optical fuse compares these measured values with intensity and / or phase shift threshold values.The optically controllable switching device has third means (LIV) for generating an optical switching signal (SB) depending on the comparison result and for controlling the state of the optically controllable switch (T2) with this optical switching signal (SB).

A variable slew rate gate drive system for powering an electric machine. The system may include a gate driver operable for controlling each of a plurality of hybrid switch power modules between opened and closed states to facilitate powering the electric machine. The gate driver may be operable for selecting slew rates and controlling ON and OFF states of first and second semiconductor switches included as part of each power module to optimize powering of the electric machine by varying the slew rates as a function of performance characteristics of the first and second semiconductor switches.

A power switching device is disclosed. The power switching device includes a cascode switching circuit comprising a normally-on transistor and a normally-off transistor provided in a cascode topology. The power switching device also includes a gate driver circuit configured to apply a positive bias voltage at a respective gate terminal of the normally-on transistor under a normal operating condition, and to apply a negative bias voltage at the respective gate terminal of the normally-on transistor under a short circuit condition.

A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

A control circuit for a switching converter includes a compensation circuit, a ramp generation circuit, a comparison circuit and a logic circuit. The compensation circuit is configured to generate a compensation signal in response to a feedback signal and a reference signal. The ramp generation circuit is configured to generate a ramp signal. The comparison circuit is configured to provide a comparison signal in response to the compensation signal and the ramp signal. The logic circuit is configured to provide the PWM control signal to the switching converter. The PWM control signal is at a first voltage level when a value of the ramp signal reaches a value of the compensation signal. The PWM control signal is at a second voltage level in response to the clock signal.

The low-power fast wake-up band-gap reference voltage circuit operates in three phases: dormant, wake-up, and steady-state phases. The circuit enters wake-up subsequent to receipt of an enable signal which causes a one-shot timer to generate a slew enable signal pulse having a predetermined period. To a band-gap voltage reference circuitry comprising an operational amplifier, there is connected, at the wake-up phase, a boost circuitry, operative under the control of the slew enable signal that connects one or more of the one or more boost circuits to a band-gap voltage reference. Thereby, during the brief wake-up phase, more current is consumed to accelerate the response of the circuit. Upon completion of the wake-up phase the boost circuitry is disconnected under the control of the slew enable signal and for as long as the enable signal is active, the circuit is operative in a low-power mode.

MEMS device (100), having the following features: at least one touch sensor element (120, 1201-1204) configured to detect a touch (124) piezoelectrically, capacitively, optically, or magnetically; and at least one proximity sensor element (130, 1301-1304) configured to detect an object (200) spaced from the proximity sensor element (130, 1301-1304) with sound (190, 191, 192); wherein the at least one touch sensor element (120, 1201-1204) and the at least one proximity sensor element (130, 1301-1304) are integrated on a semiconductor chip (110); wherein the at least one touch sensor element (120, 1201-1204) comprises a plate (142) defining a recess (140) in an insulator (114) and configured to be bent upon contact; and wherein the at least one touch sensor element (120, 1201-1204) is designed to detect a bending of the plate (142) caused by a touch piezoelectrically, capacitively, optically or magnetically, wherein the MEMS device (100) is configured to determine a force of contact based on a magnitude of the bending.

In an example, a level shifter includes a low side having first and second inputs. The level shifter also includes a high side, where the high side has a latch having first and second terminals. The high side also includes a current comparator including first and second current mirrors. The high side includes isolation circuitry including first and second transistors, in which the first transistor has a first control terminal, the second transistor has a second control terminal, the first transistor is coupled between the first terminal and the first current mirror, the second transistor is coupled between the second terminal and the second current mirror, the first control terminal is coupled to the second current mirror, and the second control terminal is coupled to the first current mirror.

A keyboard key structure comprising a key stem, a contact-based mechanical trigger, and a contactless analog key switch. The key stem is configured to be depressed and move along a linear path over a range of operation. The contact-based mechanical trigger is configured to activate after the key stem is depressed a threshold distance in the range of operation. In response to the contact-based mechanical trigger activating, the contactless analog key switch is configured to detect, at a sample rate, a position of the key stem between the threshold distance and an end of the range of operation after the key stem is depressed. The contact-based mechanical trigger can be a galvanic-type key switch. The contactless analog key switch can be one of an optical key switch, a magnetic key switch, or an inductive key switch.

The utility model provides an insulated gate bipolar transistor driving circuit with adjustable positive and negative voltages, comprising a magnetic isolation module, the input end of which is connected with a driving signal and outputs an isolation driving signal; the input end of the first voltage regulating module is connected with the first positive voltage and outputs a second positive voltage within a first preset range; the input end of the second voltage regulating module is connected with the first negative voltage and outputs a second negative voltage within a second preset range; the push-pull output module is connected between the second positive voltage and the second negative voltage, the control end of the push-pull output module is connected with an isolation driving signal, and the output end of the push-pull output module is connected with the gate pole of the to-be-tested insulated gate bipolar transistor through a gate resistor; and the protection module is controllably connected between the output end of the push-pull output module and the second voltage regulation module under the action of the control signal. The driving circuit has the beneficial effects that the positive and negative voltage output capability can be flexibly adjusted according to debugging requirements, the working condition requirements of different clients are met, and the flexibility and adaptability of the driving circuit are improved.

A method may include receiving an input signal, generating a baseline signal based on the input signal, generating a corrected input signal by subtracting the baseline signal from the input signal, determining a threshold level change of the input signal when the corrected input signal exceeds a level change threshold, and responsive to the threshold level change, updating the baseline signal to the level change threshold.

The embodiment of the present application discloses a level shift circuit and a high-voltage half-bridge driver chip. The level shift circuit includes a first and a second high-voltage switch tube, a cross-coupling module and a conversion module; a controlled end of the first high-voltage switch tube; a controlled end of the second high-voltage switch tube; the cross-coupling module includes a first current mirror and a second current mirror; the first and second nodes of the conversion module are respectively connected to the first and second current mirrors through the first and second nodes, to output an output signal.

A system and method are used to maintain a variance in feedback factors of an amplifier between the first and second phases either below a threshold value or within a specified range. The system includes the amplifier and first through third capacitances. The amplifier is coupled between an input node and an output node that operates during first and second phases of operation. The first capacitance is coupled across the amplifier and between the input node and the output node during the first and second phases of operation. The second capacitance is coupled to the input node during the first phase of operation. The third capacitance is coupled to one of the input and output nodes during one or both of the first and second phases of operation.

Disclosed in the present invention are a resistor-based voltage-withstanding on-state voltage drop measurement circuit for junction temperature monitoring, and a monitoring method. The measurement circuit comprises: a high-resistance series high-voltage resistor RL; switching diodes D1 and D2; a low-voltage MOSFET M1; a phase inverter U1; a three-state gate U2; an RC delay circuit consisting of a resistor R1 and a capacitor C1; current-limiting resistors R2 and R3; auxiliary voltage sources VDD and VCC; an operational amplifier U3; and an isolation operational amplifier U4. The monitoring method comprises: designing an on-state voltage drop sampling circuit based on a high-resistance resistor, and performing parameter selection on the basis of an actual application scenario; measuring a collector current and on-state voltage drop model at different junction temperatures under offline conditions, so as to provide a calculation model for online monitoring; and under online conditions, performing online monitoring of junction temperature on the basis of the model obtained by means of performing testing under the offline conditions. The present invention has the advantages of being low cost, having high reliability, and adaptability to on-state voltage drop measurement at a high voltage and within a wide ambient temperature range.

The invention relates to a touch device and a touch signal detection method. The touch device comprises a processor and a touch sensor. The touch sensor comprises 2N electrodes, the 2N electrodes are arranged in two rows, and the number of the electrodes in each row is the same; the two electrodes, located in the diagonal direction, in the two adjacent columns of electrodes are connected with each other to form an emitting electrode and a receiving electrode. The emitting electrode and the receiving electrode are respectively connected with the processor; n is an integer greater than 1; the processor is used for generating a code printing signal of a first frequency for the emitting electrode and inputting the code printing signal to the emitting electrode; the first frequency is greater than or equal to preset frequency; and the processor is also used for detecting the output signal of the receiving electrode to obtain a touch semaphore and determining a trigger source of the touch signal acting on the touch sensor based on the touch semaphore. By adopting the touch equipment, the trigger source of the touch signal can be accurately determined on the basis of the touch sensor with a specific structure.

Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.

The invention provides a key operation method and a related device. A pressure sensor, an optical sensor, a bioelectric sensor and a temperature sensor can be arranged in a first key of the electronic equipment. The electronic equipment can accurately identify whether the touch operation acts on the first key and the type of the touch operation according to the data detected by the sensor in the first key. Therefore, the first key can support various types of touch operations (such as short-press operation, long-press operation, light-press operation, heavy-press operation, up-slide operation and the like). According to the method, a user can conveniently carry out different types of touch operations on the first key so as to control the electronic equipment to realize multiple functions.

A semiconductor switch comprising a first main terminal, a second main terminal, and a control terminal, the semiconductor switch further comprising: a III-nitride high-electron-mobility transistor (HEMT), the III-nitride HEMT comprising a first source terminal, a first drain terminal, and a first gate terminal; a first interface circuit operatively connected to the control terminal and to the first gate terminal; and a short-circuit detection circuit operatively connected to the first drain terminal and the first source terminal, the short-circuit detection circuit being configured to: sense a short-circuit across the first drain terminal and the first source terminal; and transmit a short-circuit detection signal to the first interface circuit, the first interface circuit being configured, upon receipt of the short-circuit detection signal, to cause the III-nitride HEMT to turn off, and / or to cause a voltage across the first gate terminal to be reduced.

A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter having a positive output rail and a negative output. The driver circuit also comprises: a driving stage that is connected between the positive output rail and the negative output rail; a shunt regulator configured to regulate the negative output voltage on the negative output rail based on a difference between the negative output voltage and a target negative voltage value, wherein the shunt regulator is powered by the positive output voltage on the positive output rail; a short-circuit transistor having a conduction channel that is connected between the negative output rail and a ground terminal; and a regulation control circuit configured to: provide a short-circuit control signal to a control terminal of the short-circuit transistor in order to short the negative output rail to the ground terminal until the positive output voltage reaches a positive threshold.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

The disclosure relates to an electronic circuit to verify the integrity of a switch. The circuit comprises a voltage comparator and decoupling switch. The decoupling switch configured receive the driving signal having a first logic value to enable the monitoring of the comparison voltage and is configured to receive the monitoring enable signal having a first logic value to command the opening of the decoupling switch. The electronic circuit is configured to generate the output monitoring signal having a first logic value in an event that the switch is an open circuit and having a second logic value in an event that the switch is a short circuit.

The invention discloses a bipolar magnetic induction integrated circuit and a switch, the bipolar magnetic induction integrated circuit corresponds to a key switch, and each key switch comprises a switch body and a magnetic element; the switch body comprises a component capable of moving up and down, the bipolar magnetic induction integrated circuit is arranged on the surface of the PCB, and the magnetic induction direction of the bipolar magnetic induction integrated circuit is a vertical direction; the magnetic element is positioned above the bipolar magnetic induction integrated circuit and is arranged on the part capable of moving up and down, and the NS pole direction of the magnetic element is a vertical direction or a horizontal direction; the magnetic element moves up and down perpendicular to the magnetic induction horizontal plane of the bipolar magnetic induction integrated circuit. The bipolar magnetic induction integrated circuit is higher in anti-jamming capability, more suitable for dynamic control and high in function integration level, the bipolar Hall chip integrates a latch function (such as a latch type Hall), the state can be kept until the magnetic field is reverse, and the bipolar magnetic induction integrated circuit is suitable for accurate position memory.

FinFET multi-diode thyristor switches for protecting high data rate communication system interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and / or reduces total on-state resistance.