3387 results about "MOSFET" patented technology

The invention relates to an ultrahigh-voltage silicon carbide start control chip protection method and system, and the method comprises the steps: obtaining the operation parameters and composite structure characteristic data of an ultrahigh-voltage silicon carbide start control chip, and carrying out the TVS-MOSFET hierarchical characteristic analysis, and obtaining the real-time state information of the chip; acquiring a grid charging curve of the ultrahigh-voltage silicon carbide starting control chip, and performing correlation analysis on the grid charging curve and the real-time state information of the chip to obtain a multi-threshold protection parameter; acquiring current change data of the ultrahigh-voltage silicon carbide starting control chip, and performing Miller platform feature analysis on the real-time state information of the chip to obtain a current abnormal trend; performing temperature control construction on a multi-threshold protection parameter and the current abnormal trend to obtain an initial control scheme; and carrying out clamping turn-off strategy construction on the initial control scheme and the potential fault area to obtain a chip start protection strategy. Optimized starting protection of the chip can be achieved through the comprehensive adjustment strategy, and therefore the service life of the chip is effectively prolonged.

The invention relates to the technical field of packaging of power electronic devices, in particular to a three-dimensional packaged double-sided heat dissipation power module. The structure comprises an upper active metal brazing base material substrate and a lower active metal brazing base material substrate, a plurality of silicon carbide MOSFET chips, conductive strips and an inserter used for fixing the chips are arranged between the upper active metal brazing base material substrate and the lower active metal brazing base material substrate, the upper half-bridge chip is annularly arranged around a direct-current positive terminal, the lower half-bridge chip is annularly arranged around a direct-current negative terminal, and heat dissipation channels are formed in the upper surface and the lower surface of each chip. The impedance of branches is controlled to be equal, the current of each branch chip is balanced, the distance and layout of the chips are optimized, the overall loop area is reduced, the parasitic stray inductance of the module is reduced, in addition, the chips and the substrate are connected in a crimping mode, the chips and the copper columns are in contact through pressure to achieve electric heat conduction, the crimping materials are graphene sheets and molybdenum sheets, and the cost is low. Good contact between the chip and the copper columns is ensured, and contact resistance and thermal resistance are reduced. According to the invention, the effects of improving the heat dissipation efficiency, reducing parasitic stray inductance, balancing the current distribution of the parallel chips, and enhancing the module reliability and the conversion efficiency are achieved.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention discloses a three-phase permanent magnet synchronous motor full-speed-domain driving control system and a control method thereof. The system is composed of a torque limiting module, a full-speed-domain control neural network module, a current control module, a coordinate transformation module-I, a coordinate transformation module-II, a coordinate inverse transformation module, an SVPWM module, a SiC MOSFET driving module, a full-speed-domain position rotating speed observation module, a weak magnetic feedback module and a three-phase permanent magnet synchronous motor. The control method is used for driving the control system. According to the method, accurate tracing of the optimal dq-axis reference current working point is realized based on deep learning, and accurate control of three operation modes of MTPA, field weakening control and MTPV is realized; an improved mobile vision field estimation algorithm is adopted, and the rotor position and the rotor rotating speed are accurately estimated within the full-speed domain range; the SiC MOSFET is used as an inverter switching tube, and a brand new drive circuit is designed to adapt to the operation condition of the electric vehicle.

A semiconductor integrated-circuit (IC) chip includes: a first transistor, a second transistor at a same horizontal level as the first transistor, a first oxide layer at the same horizontal level as the first and second transistors, horizontally around the first and second transistors and having a portion horizontally between the first and second transistors; a frontside interconnection scheme under the first and second transistors and first oxide layer, a backside interconnection scheme over the first and second transistor and first oxide layer, and a metal interconnect vertically in the portion of the first oxide layer and coupling the frontside interconnection scheme to the backside interconnection scheme.

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device and particularly to MOSFET transistors. A semiconductor device including a first-conductivity-type substrate, a first-conductivity-type epitaxy layer including a JFET region, two first well regions including two source regions, two second well regions, a scatter oxide layer, the first-conductivity-type substrate is adjacent to the first-conductivity-type epitaxy layer, the two first well regions are adjacent to the first-conductivity-type epitaxy layer and each of the two first well regions is adjacent to one second well region, the JFET region is adjacent to the two second well regions, the scatter oxide layer is adjacent to the two source regions, the two first well regions, the two second well region and the JFET region, and a width of the JFET region is greater near the scatter oxide layer than in part closest to the first-conductivity-type substrate.

The invention discloses an online aging state monitoring method and system for a silicon carbide MOSFET, and belongs to the technical field of semiconductor device monitoring, and the method specifically comprises the steps: collecting the working voltage, working current and junction temperature data of the silicon carbide MOSFET in real time, analyzing and processing the data through a data processing unit, and extracting the aging state characteristic parameters of the MOSFET; a dynamic aging state evaluation model fusing multi-source data and time sequence information is adopted to evaluate the aging state of the silicon carbide MOSFET, and a result is output to a display unit; according to the method, the aging state of the silicon carbide MOSFET is monitored, multi-level alarm strategies are set, different levels of alarm signals are triggered according to the aging state, meanwhile, feedback data are collected to optimize the state evaluation model, real-time and accurate monitoring of the aging state of the silicon carbide MOSFET is achieved, and the reliability and stability of a power electronic system are improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The present invention discloses a prediction method for a crosstalk spike in a half bridge of current-source inverter with silicon carbide devices, where, the prediction method includes calculation of the crosstalk voltage spike in the circuit of current-source type double-pulse test and analysis of the effect of each parameter on the magnitude of the crosstalk spike. The prediction method of the present invention analyzes the horizontal conduction crosstalk mechanism between the gate-source junction of the MOSFET caused by the high-frequency switching action of the silicon carbide (SiC) MOSFET and the SiC Schottky diode connected in series, and derives the prediction model for the crosstalk voltage spike in the half-bridge of current-source inverter. Based on the equivalent circuit of the current-source-type double-pulse test and the crosstalk-induced mechanism, the extreme value of crosstalk voltage spike is accurately predicted, which is helpful to analyze the effects of the drive circuit and the parameters of the power circuit on the crosstalk voltage spike through the prediction model.

An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region.

The invention discloses a high-voltage SiC MOSFET cellular structure. The high-voltage SiC MOSFET cellular structure comprises an N + type silicon carbide power substrate, an N type drift region and a current expansion layer which are stacked in sequence, the electric field modulation regions are arranged on the left side and the right side of the current expansion layer, the P-body region is arranged above the current expansion layer, and the N + type source region and the P + type source region are arranged above the P-body region; the gate trench is arranged in the middle of the current expansion layer, a P + type shielding region is arranged at the bottom of the gate trench, a gate is arranged in the gate trench, and the gate is located above the P + type shielding region; and the gate oxide layer covers the upper surfaces of the gate, the N + type source region and the P + type source region. According to the structure, the electric field modulation areas are arranged on the two sides of the current expansion layer, the peak electric field intensity of the bottom of the groove of the UMOSFET device is reduced, the reverse breakdown voltage of the device is greatly improved, and meanwhile, the N-type areas in the electric field modulation areas also effectively reduce the characteristic on-resistance when the power device is conducted.

According to the SiC MOSFET global short circuit and overcurrent protection circuit and the control method thereof provided by the invention, when a short circuit fault occurs in the SiC MOSFET, the drain current ID is more than several times of the rated current of the SiC MOSFET. When a short circuit occurs, a transistor QDZ of the short circuit detection circuit is switched on by node voltage Vr of the resistance-capacitance filter circuit, a fault signal VFAULT is converted into a low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET; when an over-current fault occurs in the SiC MOSFET, drain current ID is higher than rated current, node voltage Vo of the resistance-capacitance filter circuit lasts for a long time, the maximum value of capacitor voltage Vch of the over-current detection circuit is higher than reference voltage Vref2, a fault signal VFAULT is converted into low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET. According to the invention, high-speed short circuit and over-current fault protection of the SiC MOSFET in all inductance regions of a commutation loop can be realized.

A plurality of systems of protection circuits are supported without changing a layout in a switching element. A semiconductor device includes a main switching element including a MOSFET and a sense switching element having a smaller area in plan view than the main switching element and for detecting current flowing through the main switching element. A first gate terminal that is a gate terminal of the sense switching element is arranged between a second gate terminal that is a gate terminal of the main switching element and a source terminal of the sense switching element.

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

The invention relates to the technical field of transistor detection, in particular to a quick test method and system for an MOSFET device. The method comprises the following steps: acquiring and integrating multi-source parallel data of the MOSFET device to obtain real-time I-V characteristic data of the device; performing MOSFET device performance prediction based on the real-time device I-V characteristic data to obtain MOSFET device performance prediction data; screening according to the performance prediction data of the MOSFET device to obtain performance data of a primarily screened qualified device; performing adjustment based on the performance data of the preliminarily screened qualified device to obtain an MOSFET device test scheme; acquiring real-time test data of the MOSFET device, and screening qualified devices to obtain performance data of re-screened qualified devices; and performing device test summarization based on the performance data of the primarily screened qualified device and the performance data of the secondarily screened qualified device to obtain an MOSFET device test report. According to the invention, the test period can be shortened.

Disclosed in the present application are a silicon carbide MOSFET device and a manufacturing method therefor. The silicon carbide MOSFET is provided with a first withstand voltage masking structure and a second withstand voltage masking structure. The withstand voltage performance of the device is improved, the breakdown problem of a gate insulating dielectric layer can be avoided, the electrostatic effect of the device on a severe environment and the high-voltage peak tolerance capability in the circuit are improved, and the surge voltage resistance of the device and the over-voltage protection capability are improved. Ion implantation can be carried out on a first trench to form the first withstand voltage masking structure, and ion implantation can be carried out on a second trench to form the second withstand voltage masking structure.

The invention provides an etching parameter adjusting method and device in MOSFET chip production, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining plasma density distribution data and an etching rate monitoring value of a wafer surface, and dynamically dividing the wafer surface into a plurality of segment independent control units; adjusting a radio frequency power distribution weight, and synchronously adjusting a reaction gas injection parameter; carrying out coupling analysis on the concentration gradient of the etching by-product and the matching degree of the surface morphology of the wafer; and when the deviation of the target value threshold is detected, temperature compensation and air pressure compensation are carried out. According to the method and the device, the technical problem of poor etching precision of the MOSFET chip caused by non-uniform etching rates of different regions in the etching process is solved, and the uniformity of the etching rates is improved through real-time monitoring and dynamic compensation, so that the etching precision of the MOSFET chip is improved.

The invention discloses a TCM-mode-based Si-SiC hybrid power multi-phase staggered H-bridge converter structure and a control method thereof, according to the scheme, a three-phase staggered parallel topology of a two-phase low-frequency Si-IGBT bridge arm and a one-phase high-frequency SiC-MOSFET bridge arm is adopted, and a TCM control strategy is combined, so that zero voltage switching (ZVS) of a Si device is successfully realized, the switching loss is remarkably reduced, and the switching efficiency is improved. The system efficiency is greatly improved; and meanwhile, through pilot frequency interleaving and ripple compensation technologies, total output current ripples are greatly reduced, and optimal balance between system performance and manufacturing cost is realized while the power capacity of the converter is remarkably expanded and the dynamic response speed and the output electric energy quality are improved.

The invention discloses a junction temperature prediction method based on SiC MOSFET turn-off loss, and belongs to the technical field of power electronics and electricians. The junction temperature prediction method combines a turn-off loss model with a junction temperature prediction model based on turn-off loss, and comprises the following steps: firstly, establishing a SiC MOSFET turn-off loss model considering parasitic parameters, secondly, establishing the junction temperature prediction model based on the SiC MOSFET turn-off loss in an off-line manner, and then, calculating the turn-off loss on line according to the loss model. And finally substituting the loss data into the junction temperature prediction model to obtain a junction temperature prediction value. According to the method, the turn-off loss and the junction temperature of the SiC MOSFET under different working conditions can be predicted, and the method has the advantages of being high in real-time performance, easy to implement, high in model precision and the like; and an efficient and accurate solution is provided for thermal evaluation and junction temperature prediction of the silicon carbide power device.

The invention relates to the technical field of MOS semiconductors, and discloses a vertical D-MOSFET with trench isolation and an improved channel structure and a preparation method, the vertical D-MOSFET comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a source electrode, a grid electrode, a grid oxide layer and a semiconductor epitaxial layer, the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P + layer, a P well layer and an N well layer, the profile of the cross section of the grid electrode is triangular, and a polycrystalline silicon covering layer is deposited at the junction of the grid electrode and the gate oxide layer; the profile of the cross section of the gate oxide layer is in a semi-elliptical shape, and the profile of the cross section of the polycrystalline silicon covering layer is in a triangular shape. The section profile of the grid electrode is designed to be triangular, the grid oxide layer is controlled to be in a semi-oval shape, electric field distribution and a carrier migration path are optimized, the triangular grid electrode can reduce electric field concentration at the edge of the grid electrode, and the breakdown risk is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

The invention discloses a method for maintaining DC equalization of a high-voltage cascade energy storage system by using grounding switch backflow, and the method comprises the steps: collecting the data of a battery cell in a battery cluster in real time through a battery management system, carrying out the statistics of the voltage and current data of a battery cluster end, and uploading the data to a system main controller for calculation; the system main controller judges the state of each phase when the current is balanced according to the current battery data statistical state of each phase, and controls the on-off state of the MOSFET in each power module in the corresponding state; after the total charging or discharging current of each phase of battery cluster is determined, the cluster controller of each battery cluster controls the duty ratio of the MOSFET according to the current state of each battery PACK; and after the battery PACK receives the duty ratio parameter issued by the cluster controller, the output waveform of the MOSFET is modulated, and finally multi-level current equalization is realized. According to the invention, the duty ratio of the power module is controlled by applying a strategy, and the magnitude of equalization current between PACKs is controlled, so that multi-stage SOC equalization of the PACKs, clusters, bridge arms and phases is realized.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to the technical field of power electronic devices, in particular to a low-voltage direct-current circuit breaker, a fault protection method and a related device.The low-voltage direct-current circuit breaker comprises a through-flow branch, a transfer branch and an energy consumption branch which are connected in sequence; the through-current branch comprises an isolating switch and an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) commutation switch which are connected in series; the transfer branch comprises a first power electronic switch group and a buffer branch which are connected in parallel; the energy consumption branch comprises a first metal oxide MOV, a second metal oxide MOV and a second power electronic switch group; the first metal oxide MOV is connected in parallel with the second power electronic switch group; and the second metal oxide MOV is respectively connected with the first metal oxide MOV and the second power electronic switch group. The technical problems that an existing hybrid direct current circuit breaker is not suitable for a low-voltage direct current system and the loss is high in the turn-off process are solved.

The invention discloses a WOA-BP-based SiC MOSFET life prediction method and device and a storage medium, and relates to the technical field of reliability prediction of power electronic equipment. The method comprises the following steps: selecting drain-source electrode voltage as an aging characteristic parameter of the SiC MOSFET, and acquiring voltage data in real time in an aging test process by using a sensor; the collected voltage data are preprocessed, abnormal values are eliminated, missing values are supplemented, and the data are smoothed; parameters of a back propagation neural network BP are optimized through a whale optimization algorithm WOA, and a WOA-BP prediction model is constructed; and initializing a WOA-BP model and inputting voltage data for training, and establishing a mapping relation between the service life of the SiC MOSFET and the voltage to realize prediction of the residual service life of the SiC MOSFET. The SiC MOSFET service life prediction model has the advantages of being high in adaptability, low in calculation complexity, high in prediction precision and the like, can be widely applied to the fields of the semiconductor industry, new energy automobiles, industrial automation and the like, and provides powerful support for health management and maintenance of equipment.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a high-density SiC MOSFET (metal oxide semiconductor field effect transistor) structure and a preparation process thereof, the high-density SiC MOSFET structure comprises a plurality of parallel MOS cells, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode and a source electrode, each semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P well layer, an N well layer and a P-layer, the profile of the cross section of the grid electrode is T-shaped, and the width of the cross section of the P well layer and the width of the cross section of the N well layer do not exceed the width of the cross section of the grid electrode. The polycrystalline silicon is introduced to be in direct contact with the source electrode, so that the electric field effect of the drain electrode and the source electrode can be amplified, charges of the drain electrode mainly flow into the N diffusion layer from the metal deposition layer, and under the simultaneous action of a grid electrode electric field and an original electrode electric field, the charges mainly flow towards a charge channel and a charge channel in a concentrated manner; thus, diffusion of charges to adjacent MOS cells can be reduced.

Disclosed in the present invention are a resistor-based voltage-withstanding on-state voltage drop measurement circuit for junction temperature monitoring, and a monitoring method. The measurement circuit comprises: a high-resistance series high-voltage resistor RL; switching diodes D1 and D2; a low-voltage MOSFET M1; a phase inverter U1; a three-state gate U2; an RC delay circuit consisting of a resistor R1 and a capacitor C1; current-limiting resistors R2 and R3; auxiliary voltage sources VDD and VCC; an operational amplifier U3; and an isolation operational amplifier U4. The monitoring method comprises: designing an on-state voltage drop sampling circuit based on a high-resistance resistor, and performing parameter selection on the basis of an actual application scenario; measuring a collector current and on-state voltage drop model at different junction temperatures under offline conditions, so as to provide a calculation model for online monitoring; and under online conditions, performing online monitoring of junction temperature on the basis of the model obtained by means of performing testing under the offline conditions. The present invention has the advantages of being low cost, having high reliability, and adaptability to on-state voltage drop measurement at a high voltage and within a wide ambient temperature range.