2049 results about "MOSFET" patented technology

The invention provides a device for inhibiting drain-source overvoltage and overcurrent through active gate drive of a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), aiming at solving the problem of voltage or current overshoot caused by circuit parasitic parameters in a high-speed switching process of the SiC MOSFET and simultaneously considering the switching speed and energy loss balance. According to the device, drain-source voltage vdc and direct-current bus voltage of the SiC MOSFET are collected to serve as feedback signals, and gate driving voltage and equivalent gate resistance are dynamically adjusted; in a key stage (a Miller plateau switching-on period and a voltage rising period switching-off period) of a switch transient state, a gate resistance network is switched through a logic control circuit, and suppression of drain current overshoot and drain-source voltage overshoot is realized. Simulation verification shows that the device can reduce voltage overshoot by 20%-30% and current overshoot by 25%-60%, only a single voltage feedback channel is needed, the cost is obviously lower than that of a traditional multi-signal acquisition active gate driving scheme, and the device is suitable for a high-efficiency SiC MOSFET power converter.

The invention discloses a TCM-mode-based Si-SiC hybrid power multi-phase staggered H-bridge converter structure and a control method thereof, according to the scheme, a three-phase staggered parallel topology of a two-phase low-frequency Si-IGBT bridge arm and a one-phase high-frequency SiC-MOSFET bridge arm is adopted, and a TCM control strategy is combined, so that zero voltage switching (ZVS) of a Si device is successfully realized, the switching loss is remarkably reduced, and the switching efficiency is improved. The system efficiency is greatly improved; and meanwhile, through pilot frequency interleaving and ripple compensation technologies, total output current ripples are greatly reduced, and optimal balance between system performance and manufacturing cost is realized while the power capacity of the converter is remarkably expanded and the dynamic response speed and the output electric energy quality are improved.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a RESURF layer of a second conductivity type, a buried layer of the second conductivity type formed in the bottom portion of a high-side circuit, and a MOSFET having the RESURF layer serving as a drift layer, in which the MOSFET includes a first semiconductor layer of the second conductivity type serving as a drain layer, an end portion of the first semiconductor layer is located on a low-side circuit side more than an end portion of the buried layer is, and a curvature center of a curved portion of the first semiconductor layer is located closer to a high-side circuit than a curved portion of the buried layer is, and the curvature of the curved portion of the first semiconductor layer is smaller than that of the curved portion of the buried layer.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The utility model relates to a rear-phase-cut single-live-wire type wall light modulator, which comprises an MOS (Metal Oxide Semiconductor) tube switch loop unit, a singlechip control unit and a direct-current power supply unit, the MOS tube switch loop unit comprises a wiring terminal J2 connected with an MOS tube Q1, a grid electrode of the MOS tube Q1 is connected with four resistors in series in sequence and then is connected with an MOS tube Q2, a drain electrode of the MOS tube Q2 is connected with a diode D2, the diode D2 is connected with a diode D1, a fixed end contact of a single-pole double-throw switch is connected with the MOS tube Q2, and two movable end contacts of the single-pole double-throw switch are connected with the wiring terminal J1 and the wiring terminal J3 respectively; the direct-current power supply unit comprises an alternating-current voltage waveform acquisition circuit, a direct-current voltage drop circuit, an overcurrent protection circuit and a filtering voltage stabilizing circuit; according to the single-chip microcomputer control unit, a linear sliding potentiometer is connected with the PC2 end of a single-chip microcomputer after being connected with a resistor in series, the linear sliding potentiometer and a rotary potentiometer are sequentially connected between the output end of the direct-current power supply unit and the ground in series, a triode Q6 is connected with a triode Q5 and then connected with the collector electrode of a triode Q7, and the base electrode of the triode Q7 is connected with the PA6 end of the single-chip microcomputer after being connected with a resistor in series.

A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.

The invention discloses a SiC MOSFET service life prediction method and device, equipment and a medium, and relates to the technical field of health detection of power electronic devices. The method comprises the following steps: acquiring an acquisition signal set acquired by a multi-channel sensor; the collected signals are preprocessed, smoothing and fusion estimation are carried out by adopting an extended Kalman filtering algorithm, and multi-dimensional degradation features including drain-source conduction voltage drift rate and thermal resistance change rate are extracted through feature engineering. And carrying out global optimization on the key hyper-parameters and the initial weight of the LSTM network by adopting an improved artificial fish swarm algorithm. The algorithm comprises an adaptive optimization strategy, a mixed local search operator and a boundary constraint processing mechanism. And training the optimized LSTM network by using the multi-dimensional degradation characteristics, establishing a mapping relationship between the multi-dimensional degradation characteristics and the device life, and obtaining a trained prediction model. And acquiring a to-be-predicted acquisition signal set to extract multi-dimensional degradation features and input the multi-dimensional degradation features into the prediction model to obtain a residual life prediction result.

The invention relates to the technical field of semiconductor device preparation, in particular to a super-junction MOSFET preparation process parameter optimization method based on simulation analysis, which comprises the steps of generating a simulation model according to a preparation process, executing simulation based on a plurality of groups of initial process parameter sets and the simulation model, performing simulation electrical performance test on a plurality of simulated super-junction MOSFETs, and performing simulation analysis on the simulated super-junction MOSFETs. Performing mapping relation learning on the plurality of groups of initial process parameter sets and the plurality of electrical performance data sets by utilizing a pre-constructed back propagation agent model, performing optimization solution on a mapping relation model, performing decision screening on an optimal solution set, and importing an optimal process parameter combination into a pre-constructed TCAD simulation model for verification to obtain a TCAD simulation model; and completing super junction MOSFET preparation process parameter optimization based on simulation analysis. According to the method, accurate estimation of the optimal process parameter combination is realized through simulation analysis, and dynamic correction is carried out when the optimal process parameter combination does not reach the expectation, so that the super-junction MOSFET process parameter combination which is better in performance and feasible to prepare is obtained.

The invention discloses a control method of an interleaved parallel bidirectional DCDC converter. A circuit of the converter comprises three pairs of MOSFET switch tubes, three inductors and an output capacitor. The phase difference of PWM waves of the three pairs of MOSFET switch tubes is 120 degrees, and the phase difference is used for effectively reducing current ripples through staggered complementation of currents of all phases. Double closed-loop control is adopted, the DSP chip is responsible for current inner loop control, and the FPGA chip is responsible for voltage outer loop and power outer loop control. The current sharing precision is high, through flexible configuration of multiple proportionality coefficients and zero points, input fluctuation and load abrupt change interference can be accurately restrained, oscillation is avoided, stable output is ensured, and when load abrupt change or mode switching is carried out, output can be rapidly adjusted, transition time can be shortened, and overshoot can be reduced. And high dynamic response and strong robustness of the system are realized, so that complex and changeable application requirements are met.

Novel NEDMOS and / or LDMOS FET integrated circuit structures that reduce or eliminate the floating body effect by reducing the built-in voltage Vbi of the device. Reduction of Vbi includes adding a source-side structure that includes a “Vbi Reduction Material” (VRM) layer. VRM has a bandgap less than the bandgap of Si and, for an N-type device, a valence band that is higher than the valence band of the body material. The low Vbi of the VRM layer on the source-side of a MOSFET device that would otherwise exhibit a floating body effect allows significantly freer movement of holes from the body of the device towards the source region, thus increasing body hole collection efficiency, and significantly reduces the floating body effect.

The invention provides a power module packaging structure and a packaging process thereof. The power module packaging structure comprises an upper substrate; the heat dissipation bottom plate is arranged opposite to the upper base; the AMB substrate is arranged between the upper base body and the heat dissipation bottom plate; the power chip is arranged on the AMB substrate, a source electrode of the power chip is electrically connected with an external terminal through a copper clamping piece, and interconnection between the copper clamping piece and the source electrode of the power chip is achieved through a non-pressure silver sintering layer. The copper clamping pieces are adopted to replace traditional bonding wires, the non-pressure silver sintering interconnection technology is combined, the module layout is optimized in a collaborative mode, the on-resistance and parasitic inductance of the power module are remarkably reduced, meanwhile, the heat dissipation capacity and the thermal mechanical fatigue resistance reliability of the power module are greatly improved, and the service life of the power module is prolonged. Therefore, the bottleneck of performance and reliability of the existing SiC MOSFET power module in a high-frequency and large-current application scene is successfully solved.

The invention relates to the technical field of packaging, in particular to a double-end power supply and double-face heat dissipation packaged parallel half-bridge power module, which is characterized in that a SiC MOSFET chip and a diode chip are arranged between an upper DBC board and a lower DBC board, the bottom ends of the SiC MOSFET chip and the diode chip are connected with the lower DBC board through solder layers, and the lower DBC board is connected with the lower DBC board through solder layers. The top end of the SiC MOSFET chip and the top end of the diode chip are respectively connected with a conducting strip through a solder layer, and the conducting strip is connected with the upper DBC board through the solder layer. According to the invention, the two DBC boards and the buffer conducting strip realize electrical connection of all parts in the module, so that the whole packaging structure of the module is simplified; two-sided heat dissipation of the SiC MOSFET and the diode chip is realized through the copper-clad layers arranged on the surfaces of the two DBC boards, the problem of heat flow concentration of the SiC chip under the high-frequency working condition is effectively solved, and the problem of'heat-electric stress' coupling of the module under the high-frequency working condition is solved through system coupling current balance and two-sided heat dissipation capability, so that the module has multi-unit self-current-sharing, and the service life of the module is prolonged. The high-frequency switch stress is inhibited and balanced; and the power density is improved.

The invention relates to the technical field of gallium nitride transistors, and discloses a silicon carbide-gallium nitride heterogeneous integrated high-voltage power device structure, which comprises a silicon carbide device consisting of a plurality of parallel MOS (Metal Oxide Semiconductor) cells and a gallium nitride device consisting of two GaN structures, and is characterized in that the gallium nitride device is positioned on the back surface of the silicon carbide device; each MOS cell comprises a semiconductor epitaxial layer, an MOS source electrode, an MOS grid electrode and an MOS dielectric layer covering the surface of the MOS grid electrode; wherein the semiconductor epitaxial layer comprises an N substrate layer and an N diffusion layer from top to bottom. The transverse high electron mobility characteristic of the GaN HEMT and the longitudinal voltage withstanding advantage of the SiC MOSFET are combined, cooperative work of two wide bandgap semiconductors is achieved on a single substrate, the structure effectively utilizes the excellent heat conduction and voltage withstanding performance of the SiC substrate as a common carrier, meanwhile, through the series voltage withstanding design of the device level, the performance of the device level is improved, and the performance of the device level is improved. And the overall breakdown voltage is obviously improved.

The invention relates to an on-line monitoring method for the on-off state and abnormal behavior of a synchronous rectification MOSFET of a power system. According to the method, a drain-source voltage VDS signal and a drain current Isd signal of a synchronous rectification MOSFET are collected in the working process of a system, and on-line monitoring is conducted on the on-off state and the abnormal state of the MOSFET. The method specifically comprises the following steps: conducting state monitoring: when VDS is smaller than or equal to a conducting judgment threshold value, judging to be conducted, and otherwise, judging to be turned off; monitoring an oscillation state, and judging switch oscillation when the VDS generates multiple complete oscillations in a set time window; early turn-off monitoring is carried out, early turn-off is judged according to whether I sd is higher than a threshold value or not during turn-off in the DCM mode, and early turn-off is judged according to the current descending trend and zero intersection point deviation in the CCM mode; withstand voltage monitoring: when the VDS transient peak value exceeds the rated withstand voltage or margin of the device, determining that the device is unsafe; and mis-opening monitoring: in the DCM mode, when the VDS is close to the opening threshold value during the logic turn-off period, determining that the mis-opening risk exists. The method can improve the reliability of the power supply system.

The invention relates to a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) surge failure real-time discrimination method and system, and the method comprises the steps: 1, collecting SiC MOSFET surge waveform data, and carrying out the multi-scale physical feature extraction, and obtaining a physical frequency band energy feature; 2, performing feature alignment on the physical frequency band energy features to form a standardized feature vector; and 3, constructing a surge failure prediction model, performing temperature compensation on an output result of the surge failure prediction model, and judging a failure state. Current and voltage waveforms in a surge event are captured through a high-speed data acquisition system, key physical frequency band energy features are extracted by adopting an adaptive wavelet packet decomposition technology, a pulse width normalization coding model is constructed to realize feature alignment, and a physical guide degradation path auto-encoder model is designed to perform failure prediction. The method innovatively solves the problem of failure discrimination of surges with different pulse widths, and has the characteristics of high precision and strong real-time performance.

The present invention provides a planar silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. Some shallow trenches are arranged based on that a channel current is still parallel to a (0001) crystal plane of a SiC crystal, to further effectively use a crystal plane having a high channel mobility, for example, a (1120) crystal plane, a (1100) crystal plane, or a (0338) crystal plane, of the SiC crystal, thereby effectively reducing channel resistance of the planar SiC MOSFET device. In addition, source regions, well regions, and a channel are formed without protection from an additional ion implanted layer (IMP layer), leading to simple processes.

The invention discloses an ultra-wideband circulator based on a periodic modulation topology circuit, and belongs to the technical field of microwave and radio frequency nonreciprocal circuits. The working bandwidth range of the circulator is widened, and non-reciprocal transmission is achieved through non-magnetic materials. A time sequence control unit is respectively connected with a Floquet topology circuit layer, a clock signal driving module, a reset signal driving module and a start signal driving module; the Floquet topology circuit layer is respectively connected with a first coupling port, a second coupling port and a third coupling port; the other ends of the first coupling port, the second coupling port, the third coupling port, the clock signal driving module, the reset signal driving module and the starting signal driving module are respectively grounded; the Floquet topology circuit layer adopts a six-layer parallel network structure, and each layer of network structure comprises a coupling capacitor and three N-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) switches. The advantages of the switched capacitor structure are utilized, and the signal processing capacity which is high in integration level, small in size and capable of breaking through delay-bandwidth limitation is achieved.

The invention relates to power semiconductor device on-line monitoring and power electronic system control, in particular to a SiC MOSFET conduction current extraction circuit and method, high-frequency oscillation interference is effectively suppressed through a second-order passive RC filter circuit, a measurement error less than or equal to 1.5% is realized within a current range of 50A-300A in combination with an accurate mathematical model established by a depth symbol optimization algorithm, and the measurement accuracy is improved. The requirement of the intelligent gate driver on high-precision current feedback is met, and the measurement precision is remarkably improved; the pulse width direct analysis technology is adopted, a traditional active integrator and a digital decoding link are omitted, the system response delay is smaller than or equal to 500 ns, microsecond-level over-current protection can be supported, the response speed and the real-time performance are optimized, and the system safety in a high-frequency application scene is remarkably improved.

A semiconductor device and a power conversion device each comprise a drift layer, a gate electrode to face a well region and a source region via a gate insulating film, a source electrode provided on an interlayer insulating film covering the gate electrode and connected to the well region and the source region, a first separation region provided in an active region in which a plurality of MOSFETs each including the well region, the source region, and the gate electrode are arranged in the drift layer, the first separation region being provided to be connected to the drift layer and forming Schottky connection with the source electrode, and a surge current conduction region provided in the active region, and blocks connection between the source electrode and the drift layer, thereby enabling the achievement of a semiconductor device and a power conversion device that exhibit high surge tolerance.

The invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) modeling method based on an electrothermal coupling constraint neural network, which comprises the following steps of: defining a two-dimensional profile solution domain of an MOSFET, and determining that input variables of an electrothermal coupling constraint neural network model comprise working conditions and two-dimensional space-time coordinates sampled in the two-dimensional profile solution domain; constructing an electrothermal coupling constraint neural network model, and predicting potential, electron concentration, hole concentration and temperature; a composite loss function composed of a data loss item and a physical loss item is defined, the data loss item is a mean square error of a predicted value and an actual value of the neural network model, and the physical loss item is the sum of a partial differential equation set residual error and a boundary condition residual error; and training the neural network model by minimizing the composite loss function until the loss function converges, thereby obtaining the neural network model capable of representing the electrothermal coupling characteristics of the MOSFET. According to the invention, on the premise of ensuring physical accuracy, rapid prediction of the electric thermal field in the device can be realized.

The invention discloses a power battery active equalization control system based on SOC prediction, belongs to the technical field of battery management, and aims to solve the defect that the capacity fading of a battery pack cannot be fundamentally solved by a traditional voltage equalization strategy. According to the system, a dual-active half-bridge equalizer topology is adopted, a second-order RC equivalent circuit model and an FFRLS-EKF joint algorithm are combined to achieve high-precision SOC estimation, and the error is reduced by more than 20% compared with a traditional open-circuit voltage method; a phase shift and duty ratio combined control strategy is innovatively provided, the on-off state of an MOSFET and PWM signal parameters are adjusted in real time, the equalization current is cooperatively regulated and controlled, and the problem of pseudo equalization is solved. According to the method, the SOC of the battery pack can be quickly converged under the working conditions of standing, charging and discharging, the maximum deviation is reduced to 1.49% from 63.2%, the equalization efficiency is improved by more than 10%, and the method has the characteristics of simple circuit, efficient algorithm and strong expansibility, and is suitable for scenes such as a power battery system and an energy storage power station.

The invention relates to the technical field of silicon carbide semiconductor devices, in particular to an integrally-formed equal-depth double-groove SiC MOSFET structure and a preparation method thereof. According to the structure, an N + buffer layer and an N-drift layer are sequentially formed on an N-type SiC substrate, and a main groove and an auxiliary groove which are consistent in depth are formed in the surface of the N-type SiC substrate; a gate oxide layer and a polycrystalline silicon gate are sequentially formed in the main groove, and the auxiliary groove is filled with a SiC epitaxial material which is doped with the drift layer in the same type, so that a charge compensation and electric field regulation and control unit is formed; the P-type body region surrounds the trench structure and forms an N + source region, and the drain electrode is formed through a back metallization process. Through the collaborative design of the equal-depth double grooves, the uniformization of electric field distribution is realized, the on-resistance and the switching loss are effectively reduced, the thermal stability and the reliability of the device are improved, the integrated process is adopted for integration, the process is simplified, the production efficiency and the yield are improved, and the semiconductor device is suitable for high-frequency and high-voltage application scenes and has a wide industrialization prospect.

The invention provides an intelligent power module and a power electronic device, which are used for avoiding the problems of reliability and complexity of the existing intelligent power module through an IPM (Intelligent Power Module) which takes a hybrid device consisting of a normally open MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a low-voltage silicon MOSFET as a core power unit. The intelligent power module comprises at least one power unit, and the power unit comprises a normally open MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a low-voltage silicon MOSFET; the drain electrode of the low-voltage silicon MOSFET is electrically connected with the source electrode of the normally open type MOSFET; and the source electrode of the low-voltage silicon MOSFET is electrically connected with the grid electrode of the normally open MOSFET.

The invention relates to the technical field of MOS semiconductors, and discloses a SiC MOSFET structure with a second-order oxide layer and a preparation technology thereof.The SiC MOSFET structure comprises a plurality of MOS cells arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a source electrode and a grid oxide layer, each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, a P well layer and an N well layer, an N-doped layer is formed in the N drift layer of the single MOS cell through ion implantation, and the N-doped layer is located under the grid electrode; and a plurality of N + doped isolation layers which are not in contact with each other are formed in the N-doped layer through ion implantation. By introducing the N-doped layer right below the grid electrode and the doped N + isolation layers arranged and distributed in the N-doped layer, the distribution of an electric field below the gate oxide is effectively modulated, and the peak of the electric field is inhibited, so that the breakdown voltage of the device is remarkably improved, the reliability of the gate oxide layer is enhanced, and meanwhile, relatively low specific on-resistance is kept.

The utility model relates to a crosstalk suppression driving circuit of a silicon carbide MOSFET bridge circuit and power supply equipment. The crosstalk suppression driving circuit comprises an upper bridge driving module, an upper bridge crosstalk suppression module, a lower bridge driving module and a lower bridge crosstalk suppression module. The upper bridge driving module is respectively connected with the upper bridge crosstalk suppression module and the upper bridge arm, and the upper bridge crosstalk suppression module is also connected with the upper bridge arm; the lower bridge driving module is connected with the lower bridge crosstalk suppression module and the lower bridge arm, and the lower bridge crosstalk suppression module is further connected with the lower bridge arm. Each crosstalk suppression module and the corresponding bridge arm share a turn-off signal and a turn-on signal, and there is no need to additionally add a detection or control circuit to control the crosstalk suppression module. Each crosstalk suppression module is connected with the corresponding bridge arm in the turn-off process of the corresponding bridge arm, so that the forward driving crosstalk and the negative driving crosstalk of the silicon carbide MOSFET can be suppressed; and each crosstalk suppression module is automatically disconnected with the corresponding bridge arm before the corresponding bridge arm is conducted, so that the conduction loss of the bridge arm can be reduced, and the circuit efficiency is prevented from being reduced.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer “T”-shaped gate (as viewed in cross-section). The novel “T-gate” significantly decreases the gate resistance RG of a MOSFET device and thus increases the figure-of-merit fMAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths Lg scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance CGS and gate-to-drain capacitance CGD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

The invention provides a three-phase low-voltage MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) packaging integrated power module. A driving assembly, a direct-current bus capacitor and other modules are integrated in an aluminum shell package. The three DBC substrates respectively bear U-phase bridge arms, V-phase bridge arms and W-phase bridge arms, an upper bridge arm and a lower bridge arm of each phase are formed by a plurality of parallel MOSFET chips, drain electrodes of the chips are directly welded to a DBC upper copper layer, grid electrodes of the chips are connected with an upper-layer driving circuit board through copper columns, source electrodes of the chips are led out to a direct-current input terminal or an alternating-current output terminal through bonding wires, and a double-layer conductive structure is formed. A plurality of direct-current bus capacitors which are arranged above the aluminum shell in parallel are adjacently coupled with the DBC substrate, so that low-impedance energy buffering is realized; the alternating current output terminal is sleeved on the current sensor, detects the phase current and outputs the phase current through the signal terminal; and a thermistor is mounted on a copper layer on each DBC to monitor the junction temperature of the chip and provide over-temperature protection. The direct-current input terminal, the alternating-current output terminal, the power terminal and the signal terminal are integrally embedded in the aluminum shell and are directly butted with an external busbar and a controller, and additional sampling and driving boards are not needed.

The embodiment of the invention provides a transformer no-load closing angle control method, electronic equipment, a storage medium and a program product. The method comprises the following steps: periodically sampling three-phase voltages at a power supply side of a transformer, and determining a zero crossing moment when the phase voltage is changed from a negative value to a positive value according to respective sampling data for each phase in the three phases; based on the zero point moment of each phase, a preset switching-on angle and the total delay required from the switching-on instruction sending to the actual conduction of the main circuit, the target moments at which the switching-on instructions of the three phases should be sent out are calculated respectively, and corresponding switching-on trigger signals are output at the target moments of the phases respectively; and in response to the closing trigger signal of each phase, combined switch circuits arranged in the three-phase line are respectively driven, and each group of combined switch circuit comprises an MOS (Metal Oxide Semiconductor) tube and a dry reed relay which are connected in parallel, so that the MOS tube is conducted to establish an initial current path.

The invention discloses a passive multi-stage voltage soft turn-off circuit suitable for SiC MOSFETs. The passive multi-stage voltage soft turn-off circuit comprises a driving main branch, a plurality of voltage reduction branches, a driving resistor, a discharging resistor and a driving power supply circuit. The driving power supply circuit is powered by a positive power supply VCC when the SiC MOSFET is turned on, and is powered by a negative power supply VEE when the SiC MOSFET is turned off. The voltage reduction branches are connected to the two ends of the driving main branch in parallel. The step-down branch comprises a step-down delay unit, a step-down action unit and a step-down unit which are sequentially connected in series; the delay time of each step-down branch is increased in sequence, and the step-down voltage drop is increased in sequence. According to the invention, the voltage level can be conveniently controlled by changing the number of the voltage reduction branches, an additional power supply module does not need to be added, the voltage reduction time can be controlled by the voltage reduction delay branches, the degree of freedom of driving is greatly increased, and the circuit is low in complexity, high in voltage reduction degree of freedom and high in reliability.