47 results about "Effective capacitance" patented technology

The invention discloses a high-sensitivity touch control capacitor chip device and system, and relates to the technical field of touch control. The method comprises the steps that an original capacitance signal matrix is collected through mixed frequency band excitation, environment compensation is conducted on original capacitance signals through a nonlinear compensation mechanism, and an effective capacitance matrix is generated; extracting a time-domain pure touch signal through fractional order time-frequency combined noise suppression and dynamic baseline tracking; the method comprises the following steps: extracting deformation curvature characteristics of a contact area through a time-domain pure touch signal, and constructing a spatial-temporal characteristic tensor; and through self-adaptive convolution kernel generation and a multi-modal attention mechanism, taking the spatial-temporal feature tensor as input, taking the touch behavior classification probability distribution as output, and generating a final touch instruction according to the category corresponding to the maximum value of the probability distribution. Environmental interference is suppressed through multi-frequency excitation and frequency domain decoupling, temperature and humidity coupling compensation is introduced to improve signal stability, multi-dimensional spatial-temporal characteristics are constructed, and the recognition precision and robustness of the capacitive touch control system in a complex environment are remarkably enhanced.

The invention is suitable for the technical field of circuit monitoring, and provides a capacitance value online monitoring method and system based on thin film capacitor self-healing feature perception, and the method comprises the steps: synchronously collecting a voltage signal and a current signal of a to-be-detected thin film capacitor based on a preset sampling period, and constructing a voltage sequence and a current sequence with a unified time sequence; determining a candidate transient time window based on a preset sampling period and the voltage sequence; in the candidate transient time window, a time sequence of a self-healing event is determined based on the voltage sequence and the current sequence, and the self-healing event comprises an arcing stage, an arc quenching stage and a charging recovery stage; and based on the initial voltage, the final voltage and the effective charging current in the charging recovery stage, determining an effective capacitance estimation value of the to-be-tested thin-film capacitor. According to the technical scheme provided by the invention, the self-healing behavior of the thin-film capacitor is accurately identified, so that online monitoring of the capacitance value of the thin-film capacitor is realized, and the capacitance value monitoring error is effectively reduced.

The utility model discloses a micro-hemisphere gyro sensor, which is characterized in that an exciting electrode and a detecting electrode are separately arranged, so that compared with the traditional electrode design with an integrated structure, the micro-hemisphere gyro sensor has the advantage that the effectively utilized capacitance can be obviously increased under the condition of the same structural size. The design not only optimizes the capacitance performance, but also greatly reduces the signal interference intensity between the excitation electrode and the detection electrode, thereby effectively improving the mechanical sensitivity and the measurement precision of the gyroscope. The innovation not only enhances the performance of the equipment, but also provides a more reliable technical basis for the development of a high-precision navigation and positioning system.

The invention relates to an arrangement comprising a switching arrangement having a switching element and a control device which is designed to switch the switching element on the basis of a switching-off current determined by a relationship according to formula (I), where IT0, n describes a switching-off current to be switched off through the switching element (121), VDC describes an intermediate circuit voltage of a commutation circuit, and n represents a switching-off current to be switched off through the switching element (121). Ceff1 describes an effective capacitance of the commutation resonant circuit associated with the switching element (121), Ceff2 describes an effective capacitance of the commutation resonant circuit associated with the free running element (142), Lp describes an effective inductance of the commutation resonant circuit, and n describes a natural number, where at least one of the following conditions is satisfied: Formula 1); 2). # imgabs0 # 1) # imgabs1 # 2) # imgabs2 #

The invention discloses a compensation capacitance signal identification method and device, and the method comprises the steps: traversing an original capacitance pulse signal, extracting a maximum peak value and a corresponding pulse point position, generating a candidate capacitance pulse region, obtaining an average peak value of a maximum peak value array in the candidate capacitance pulse region, and carrying out the recognition of a compensation capacitance signal. Acquiring a maximum peak value of the maximum peak value array in an adjacent region of the candidate capacitance pulse region; determining the candidate capacitance pulse area as an effective capacitance pulse area; counting each pulse point and the maximum peak value corresponding to the standard pulse interval in the effective capacitance pulse area; adopting a search algorithm to obtain a plurality of new pulse points; and adding the plurality of new pulse points into the compensation capacitance pulse signal, and identifying the compensation capacitance pulse signal according to the maximum peak array and the pulse point position array of the compensation capacitance pulse signal. The method can improve the recognition precision and efficiency of the supplementary capacitance signal, and provides a basis for the reliability of subsequent railway safety operation.

A method of determining a lifetime parameter of a capacitor in a failsafe device includes measuring an amount of energy required to return the failsafe device to a failsafe position, measuring an effective capacitance of the capacitor, and comparing the amount of energy to the effective capacitance to determine the lifetime parameter of the capacitor.

The invention relates to a micromechanical pressure sensor (100), comprising a substrate (110) having a layer system (120) arranged thereon. The micromechanical pressure sensor (100) further comprises a sensor structure (200) fixed to the layer system (120) in a self-supporting manner by means of at least one suspension structure (140), the sensor structure has a first membrane structure (210), a second membrane structure (220) and a cavity region (240) which is arranged between the two membrane structures (210, 220) and which is closed by a side wall (230) extending in an edge region (212, 222) of the two membrane structures (210, 220). In this case, the sensor structure (200) comprises an effective capacitor (250), which is arranged in the cavity region (240) between the two diaphragm structures (210, 220), the active capacitor has a first electrode (251) fixed to the first membrane structure (210) and a second electrode (253) arranged between the first electrode (251) and the second membrane structure (220) and fixed to the second membrane structure (220).

One object is to inhibit the reduction of effective capacitance of a capacitor that includes an intermediate layer containing Fe. An aspect of the present disclosure provides a capacitor including a body, a first external electrode provided on the body, and a second external electrode provided on the body. The body includes: a first internal electrode layer; a second internal electrode layer; a dielectric layer disposed between the first and second internal electrode layers; and a first intermediate layer disposed between the first internal electrode layer and the dielectric layer, the first intermediate layer containing Fe at a first concentration. The first concentration is from 0.2 at % to 5 at %. The dielectric layer contains Fe at a second concentration, and the second concentration is less than 1 at %. An Fe concentration ratio, which represents a ratio of the first concentration to the second concentration, is greater than 1.

Embodiments of the present disclosure advantageously provide semiconductor devices, in particular Finn field-effect transistors (FinFETs), and methods for manufacturing such devices having improved effective capacitance (Ceff). The FinFET includes a gate structure in which a void is provided by recessing a high dielectric constant material layer placed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high dielectric constant dielectric layer and improving the effective capacitance (Ceff) of the device.

The utility model relates to the technical field of magnetic resonance imaging systems, in particular to a distributed adjustable capacitor for a magnetic resonance imaging radio frequency coil. A distributed adjustable capacitor for a magnetic resonance imaging radio frequency coil comprises an upper layer conductor, a lower layer conductor and an insulating medium layer, and is characterized in that the upper layer conductor is located on the upper surface of the insulating medium layer, and the lower layer conductor is located on the lower surface of the insulating medium layer; the overlapping part of the upper layer conductor and the lower layer conductor in the vertical direction is an effective capacitor, and the area of the effective capacitor is an effective capacitance value. Compared with the prior art, the unit areas of the effective capacitors of the distributed adjustable capacitor are the same, and the effective capacitors have the same capacitance value, so that when the distributed adjustable capacitor is cut to reduce the capacitance value, only the effective capacitors with the corresponding number need to be counted and cut off, and there is no need to subtract the effective capacitors for many times each time. And the debugging time of the magnetic resonance radio frequency imaging radio frequency coil is greatly saved.

A distributed tunable capacitor for a magnetic resonance imaging radio-frequency coil, the distributed tunable capacitor comprising an upper conductor (1), a lower conductor (3), and an insulating dielectric layer (2), wherein the upper conductor (1) is located on the upper surface of the insulating dielectric layer (2), and the lower conductor (3) is located on the lower surface of the insulating dielectric layer (2); and the overlapping portion between the upper conductor (1) and the lower conductor (3) in the vertical direction is an effective capacitor, and the area of the effective capacitor represents an effective capacitance value. Effective capacitors in the distributed tunable capacitor have the same unit area and the same capacitance value, such that when the distributed tunable capacitor is trimmed to reduce the capacitance value, it is only necessary to count a corresponding number of effective capacitors and cut same off, instead of trimming a tiny amount repeatedly through trial and error, thereby greatly reducing the debugging time of a magnetic resonance imaging radio-frequency coil.

This invention provides a multilayer ceramic capacitor comprising a plurality of segregated particles with a size of less than 10 micrometers, present in an effective capacitance portion. Most of the segregated particles are in direct contact with an internal electrode layer. The composition of the segregated particles includes silicon, alkaline earth metals, and rare earth elements. The concentration of the silicon-containing segregated particles is greater than the concentration of the alkaline earth metal-containing segregated particles, and the concentration of the alkaline earth metal-containing segregated particles is greater than the concentration of the rare earth element-containing segregated particles. The multilayer ceramic capacitor of this invention maintains high capacitance and avoids insulation resistance degradation caused by high temperature or high voltage, thus exhibiting excellent high-temperature load life and reliability.

The invention discloses a module FPC capacitor effective capacitance value detection system, which comprises an MCU module, a power supply module, a probe module, a capacitance value test module, an FPC capacitor bank module and a display module, and is characterized in that the power supply module, the probe module, the capacitance value test module, the FPC capacitor bank module and the display module are electrically connected with the MCU module; the probe module is electrically connected with the capacitance value test module and the power supply module. According to the invention, the actual capacitance value of the capacitor on the module FPC can be detected, the display effect of the module is prevented from being influenced by batch capacitance value difference or capacitor process fluctuation of the capacitor, and the yield of the module is improved.

The present invention discloses a highly sensitive touch capacitor chip device and system, which relates to the field of touch technology. The method includes: collecting the original capacitance signal matrix through mixed frequency band excitation, performing environmental compensation on the original capacitance signal through a nonlinear compensation mechanism, and generating an effective capacitance matrix; extracting a pure touch signal in the time domain through fractional-order time-frequency combined noise suppression and dynamic baseline tracking; extracting the deformation curvature characteristics of the contact area through the pure touch signal in the time domain, and constructing a spatiotemporal feature tensor; using adaptive convolution kernel generation and multimodal attention mechanism, taking the spatiotemporal feature tensor as input, and the touch behavior classification probability distribution as output, and generating the final touch instruction according to the category corresponding to the maximum value of the probability distribution. By suppressing environmental interference through multi-frequency excitation and frequency domain decoupling, and introducing temperature and humidity coupling compensation to improve signal stability, a multi-dimensional spatiotemporal feature is constructed, which significantly enhances the recognition accuracy and robustness of the capacitive touch system in complex environments.

A circuit design process is provided which includes performing noise impact on function testing of an instance of a logic cell within a circuit design, and based on the logic cell instance failing the noise impact on function testing, addressing the failure of the logic cell instance. The addressing includes selecting a noise tolerance data curve of multiple noise tolerance data curves with different associated capacitive loads on the logic cell, and adjusting an effective capacitive load on the logic cell instance to obtain an adjusted capacitive load corresponding to the associated capacitive load of the selected noise tolerance data curve. Further, the addressing includes verifying that the logic cell instance passes noise impact on function testing based on comparing a noise pulse at the logic cell instance to the selected noise tolerance data curve.

The present invention provides two high-density three-dimensional ferroelectric memory structures and their preparation methods. The preparation methods can reduce the difficulty of deep hole etching during the preparation of three-dimensional ferroelectric memory, while also increasing the effective area of ​​the ferroelectric capacitor per unit memory cell. The core structure and preparation process of the high-density three-dimensional ferroelectric memory include: dividing the conductive through-hole formed by deep hole etching into two smaller sub-through-holes as discrete conductors through isolation grooves, thereby reducing the aspect ratio of the deep hole structure during etching, thereby reducing the etching difficulty during the preparation process; and forming a groove structure on a vertical conductor extending in a direction perpendicular to the substrate to increase the contact area between the conductor and the ferroelectric material, thereby increasing the effective capacitance area of ​​the memory cell and ensuring that a sufficient storage window can be maintained when the process node is reduced. The present invention improves the storage density and reliability of three-dimensional ferroelectric memory and has broad application prospects.

The present invention can suppress a decrease in effective capacitance in a capacitor including an intermediate layer containing Fe. A capacitor according to one embodiment of the present invention includes a main body, a first external electrode provided in the main body, and a second external electrode provided in the main body. The main body has: a first internal electrode layer containing Fe at a first concentration; a second internal electrode layer; a dielectric layer disposed between the first internal electrode layer and the second internal electrode layer in the first direction; and a first intermediate layer provided between the first internal electrode layer and the dielectric layer and containing Fe at a second concentration. The first external electrode is electrically connected to the first internal electrode layer, and the second external electrode is electrically connected to the second internal electrode layer. The first external electrode includes an Ni plating layer. The first concentration is 0.01 at% or more. The second concentration is 3 times or more and 2 at% or less of the first concentration.

An apparatus includes a logic gate, a first inverter, a second inverter, a first resistor connected between the output of the logic gate and the input terminal of the first inverter, a first capacitor connected between the input terminal and the output terminal of the first inverter, a second resistor connected between the output terminal of the first inverter and the input terminal of the second inverter, a second capacitor connected between the input terminal of the second inverter and ground, and a third resistor connected between the output terminal of the second inverter and the logic gate, wherein the second input of the logic gate is configured to receive an enable signal, and wherein the first inverter is configured as a negative amplifier such that an effective capacitance provided by the first inverter and the first capacitor is greater than a physical capacitance of the first capacitor.

The invention relates to a phase-locked loop and a control method thereof, a chip, a communication system, electronic equipment and a medium, and the method comprises the steps: obtaining a first analog voltage signal outputted by a filter in the phase-locked loop, and adjusting a control bit value of a capacitor array of a voltage-controlled oscillator in the phase-locked loop according to the first analog voltage signal, therefore, the effective capacitance value of the capacitor array is changed, and the output frequency of the voltage-controlled oscillator is adjusted. According to the method, the linearity of the phase-locked loop is improved by adjusting the control bit value of the capacitor array, so that the stability of the output frequency of the voltage-controlled oscillator can be ensured.

The present application provides a method and apparatus for capacitance detection, the method comprising: determining a first variation corresponding to the n-th frame of raw capacitance data based on a difference between the n-th frame of raw capacitance data and the (n-M)-th frame of raw capacitance data output by a detection channel in the capacitance detection apparatus, where n is a positive integer greater than M and M is a positive integer greater than or equal to 1; determining a temperature compensation coefficient corresponding to the n-th frame of raw capacitance data based on the first variation corresponding to the n-th frame of raw capacitance data; and determining effective capacitance data in the n-th frame of raw capacitance data based on the temperature compensation coefficient corresponding to the n-th frame of raw capacitance data and the n-th frame of raw capacitance data. The method and apparatus of the present application can obtain more accurate effective capacitance data.

The invention relates to a miniaturized dielectric filter and a production process thereof, the miniaturized dielectric filter comprises a ceramic filter body and a ceramic cover plate, a plurality of columnar through holes are formed in the ceramic filter body at intervals, columnar through hole conducting layers are arranged on the inner walls of the columnar through holes, and the columnar through hole conducting layers are electrically connected; the ceramic cover plate is assembled at one end of the ceramic filter body in a sealed mode, a plurality of bonding pad assemblies corresponding to the columnar through holes in a one-to-one mode are arranged between the ceramic filter body and the lower end face of the ceramic cover plate, and blind hole cavities communicated with the columnar through holes are formed in the bonding pad assemblies. And a blind hole conductive layer electrically connected with the columnar through hole conductive layer is arranged in the blind hole cavity. The ceramic cover plate is sealed in the ceramic filter body, so that an electromagnetic field is completely wrapped in the ceramic dielectric, a strong electric field area between the resonance disc and the external shielding cover and the discharge risk are eliminated, and meanwhile, an effective capacitance effect can be generated between the blind hole conducting layer and the frequency modulation hole, so that the resonance frequency is reduced, and the miniaturization of the filter is realized.

A semiconductor structure and a method for forming the same include: providing a substrate, forming a gate structure on the substrate, forming dummy sidewalls on the sidewalls of the gate structure, forming contact hole etch stop layers on the sidewalls of the dummy sidewalls, and forming source and drain doped regions within the substrate on both sides of the gate structure; forming a sacrificial dielectric layer above the source and drain doped regions and the top of the gate structure; forming source and drain plugs that penetrate the sacrificial dielectric layer above the top of the source and drain doped regions and contact the source and drain doped regions; etching the sacrificial dielectric layer until the top of the dummy sidewalls is exposed; after the top of the dummy sidewalls is exposed, removing the dummy sidewalls to form a gap between the contact hole etch stop layer and the sidewalls of the gate structure; forming a top dielectric layer to fill the gap between the source and drain plugs, the top dielectric layer also filling the gap, or the top dielectric layer sealing the top of the gap, the dielectric constant of the material of the top dielectric layer being less than the dielectric constant of the material of the dummy sidewalls. The present invention can reduce the effective capacitance between the gate structure and the source and drain plugs.

Embodiments of the present disclosure advantageously provide semiconductor components, particularly fin field effect transistors (FinFETs), and methods of making such components with improved effective capacitance (Ceff). The FinFET includes a gate structure in which an air gap is provided by recessing a high dielectric constant material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high dielectric constant dielectric layer and improving the effective capacitance (Ceff) of the component.

Provided is a laminated ceramic capacitor, comprising a plurality of segregated particles with a size of 10 microns or less in an effective capacitance part; wherein the segregated particles are most in direct contact with the internal electrode layers, and the segregated particles have ingredients comprising Si, an alkaline earth metal, a rare earth element or a combination thereof. The segregated particles comprising Si are in a higher concentration than that of the segregated particles comprising the alkaline earth metal, and the segregated particles comprising the alkaline earth metal are in a higher concentration than that of the segregated particles comprising the rare earth element. The laminated ceramic capacitor of the present invention can maintain a high capacitance and avoid insulation resistance degradation resulting from a high temperature or a high voltage, thereby demonstrating a good high-temperature operating life and good reliability.

Disclosed is a diode device (1) including an insulator (7) extending between and in contact with two metal terminals (3, 5), wherein the insulator comprises at least one epsilon-near-zero (ENZ) material, or comprises at least one epsilon-negative (ENG) material (7A) and a second insulator material (7B) forming a double insulator structure, and an electron source layer (9), particularly of graphene, between a metal terminal and the ENZ or ENG material. The insulator provides a reduced effective capacitance which permits rectifying diode operation at THz, infrared or visible frequencies, particularly for a solar radiation rectenna.

Lensed antennas are provided that include a plurality of radiating elements and a lens positioned to receive electromagnetic radiation from at least one of the radiating elements, the lens comprising a plurality of rods. The rods include dielectric material and / or unit cell structures with three-dimensional meta-material patterns. The rods can be formed of stacked rod members. The stacked rod members can be formed by a stacked series of the unit cell structures. The rods can have the same size and materials with different spacings, the same size and spacing and different materials, or different sizes with the same or different spacing, each configuration arranged to define different effective permittivities across a diameter of the lens.

The present invention discloses a dual-T type MIM capacitor equivalent circuit model and a method for extracting its parameters. In the equivalent circuit model, the first end of the effective capacitor is electrically connected to the second end of the series inductor 1, the second end is electrically connected to the first end of the low-frequency parasitic resistor, the second end of the low-frequency parasitic resistor is electrically connected to the first end of the high-frequency parasitic inductor, the second end of the high-frequency parasitic inductor is electrically connected to the first end of the series inductor 2, and the high-frequency parasitic resistor is connected in parallel with the high-frequency parasitic inductor; the first end of the dielectric capacitor 1 is electrically connected to the second end of the series inductor 1, and the second end is electrically connected to the first end of the substrate parasitic capacitor 1, and the substrate parasitic resistor 1 is connected in parallel with the substrate parasitic capacitor 1. The dual-T type equivalent circuit model of the present invention can fit MIM capacitors in a wider frequency range.

Provided is a multilayer ceramic capacitor capable of improving reliability while improving effective capacitance. A laminated ceramic capacitor (100) is provided with a laminated body (6) including a plurality of dielectric layers (2) and a plurality of internal electrode layers (4) laminated in the thickness direction, and a pair of external electrodes, an inner layer part (16) of a laminated body (6) is provided with a central region (16c) at the center in the width direction, a first side edge adjacent region (16a) adjacent to a first side edge part (20a), and a second side edge adjacent region (16b) adjacent to a second side edge part (20b). The area-equivalent diameter (D50) of the dielectric particles in the dielectric layer in the first side edge adjacent region (16a) and the second side edge adjacent region (16b) is larger than the area-equivalent diameter (D50) of the dielectric particles in the dielectric layer in the central region (16c).

The present invention provides a multilayer ceramic capacitor capable of achieving a balance of initial capacitance / effective capacitance / insulation breakdown voltage in size restriction and ensuring reliability. In a multilayer ceramic capacitor (1), a dielectric layer (14) contains Ba and Ti, an internal electrode layer (15) contains Ni, 1.7 < = L0 / T0 < = 2.3 and 1.0 < = W0 / T0 < = 1.4, where L0 is the dimension in the longitudinal direction, T0 is the dimension in the lamination direction, and W0 is the dimension in the width direction, and in a cross section passing through the lamination direction and the width direction at the center in the longitudinal direction, T0 is the dimension in the lamination direction. When the amount of shift in the width direction of the ends of the internal electrode layers (15) adjacent to each other in the stacking direction is d < = 5 [mu] m, Sn having a segregated atomic composition percentage of 2 at% or more is segregated at the interface between the internal electrode layers (15) and the dielectric layers (14), and WS is a dimension in the width direction of the side gap portion (20), and WS is a dimension in the width direction between the side gap portion (20) and the side gap portion (20), and WS is a dimension in the width direction between the internal electrode layers (15) and the dielectric layers (14). When the dimension of the outer layer part (12) in the lamination direction is set as TG, 0.3 < = WS / TG < = 0.6, and the dimension WI of the internal electrode layer (15) in the width direction is set as T0lt. WI.

An apparatus includes a first inverter, a first capacitor connected between the input terminal and the output terminal of the first inverter, a second inverter, a third inverter, a second capacitor connected between the input terminal and the output terminal of the third inverter, a fourth inverter, a plurality of resistors coupled in series between an output of a logic gate and a first input of the logic gate, and a third capacitor connected between the first input of the logic gate and ground, wherein the logic gate has a second input configured to receive an enable signal, and wherein each of the first inverter and the third inverter is configured as a negative amplifier such that an effective capacitance between its input and output terminals is greater than a physical capacitance of the corresponding capacitor.