1099 results about "Memory circuits" patented technology

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

An apparatus includes a cache memory circuit, and a hierarchal store queue circuit that further includes a primary queue and a secondary queue. The hierarchal store queue circuit may be configured to write incoming store requests to the primary queue in response to the primary queue currently having capacity, and to write incoming store requests to the secondary queue in response to the primary queue currently not having capacity. The hierarchal store queue circuit may be further configured to commit store requests to the cache memory circuit from the primary queue but not from the secondary queue. In response to a determination that the primary queue currently has capacity, the hierarchal store queue circuit may perform a transfer of at least one store request from the secondary queue to the primary queue.

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-number difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-number difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

A method of operating a memory device including a memory cell array and a memory circuit includes receiving a first command from a controller, determining, in response to the first command, whether first device information stored in the memory circuit has an error, receiving, in response to the determining that the first device information has the error, a reset command from the controller, and performing a refresh operation on the memory circuit in response to the reset command. The first device information includes information about an operation parameter and an operating frequency of the memory device.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells connected to word lines and bit lines located on opposite sides of the memory cells. The memory cell may include gate all around transistors. A memory circuit according to the present disclosure also includes edge cells having word line tap structures configured to connect front side word lines with back side word lines. Some embodiments of the present disclosure provide an IC chip having memory cells with power rail on the front side and logic cells with power rail on the back side.

Provided in the embodiments of the present disclosure are a storage unit, a memristor array, a compute-in-memory circuit and an operation method. The storage unit comprises n weight units and a lateral gate transistor. Each of the n weight units comprises a first memristor element and a first switch element, a first electrode of the first memristor element being electrically connected to a first electrode of the first switch element, and a second electrode of the first memristor element being used as a second end of the corresponding weight unit and being used for receiving a first bit line signal. The second electrodes of the first switch elements of the N weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other, and are electrically connected to a first end of the lateral gate transistor. The control electrodes of the first switch elements are respectively used for receiving different first word line signals. A second end of the lateral gate transistor is used for receiving a source line signal, and a control end of the lateral gate transistor is used for receiving a second word line signal.

Electro-optic (“EO”) computing systems for high bandwidth and high-capacity memory access via wavelength-division multiplexed (“WDM”) switching are provided herein. Examples of the EO computing system include one or more compute circuit packages, one or more memory circuit packages, and an optical switch connected between the compute and memory circuit packages.

A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.

The invention provides a column memory circuit, a chip, an image sensor and an imaging apparatus. The column memory circuit comprises M * N memory bank modules, N read-out modules and a data transmission module, and a correlated double-sampling module of the column memory circuit is arranged in the read-out module; the first end of the memory bank module receives a first data signal, the second end of the memory bank module is coupled with the first end of the reading module corresponding to the memory bank module, and the second end of the reading module is coupled with the data transmission module; the memory bank module converts a received first data signal into a second data signal, the reading module performs correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module outputs the third data signal. According to the column memory circuit, the area of the column memory circuit can be obviously reduced, the circuit performance can be well ensured, and the cost of an image sensor can be obviously reduced by adopting the column memory circuit provided by the invention.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel portion, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel portion and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, so that power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are formed to be stacked; therefore, the length of a wiring between the circuits can be shortened, and a low-power consumption operation and a high-speed operation can be performed.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.

The invention provides a matrix multiplication device, a matrix multiplication system including the same, and an operation method of the matrix multiplication device. The matrix multiplication apparatus includes a weight memory circuit, an input matrix buffer, a first array of processing elements, and a second array of processing elements. A weight memory circuit stores a first pruned sub-matrix and a second pruned sub-matrix. The input matrix buffer receives an input matrix including a plurality of input elements, outputs a first plurality of input elements corresponding to a first plurality of remaining weights of the first pruned sub-matrix, and outputs a second plurality of input elements corresponding to a second plurality of remaining weights of the second pruned sub-matrix. A first processing element array receives the first plurality of remaining weights and the first plurality of input elements and outputs a first sub-output matrix. A second processing element array receives the second plurality of remaining weights and the second plurality of input elements and outputs a second sub-output matrix.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention provides a memory circuit which at least comprises an amplifier, the amplifier is provided with a first node and a second node, the first node is electrically connected with a first data line, and the second node is electrically connected with a first reference data line. The amplifier is used for amplifying the voltage difference between the first data line and the first reference data line; the first end of the first transmission tube is electrically connected with the first node, the second end of the first transmission tube is electrically connected with a second data line, and the first transmission tube is used for being switched on according to a control signal in at least part of time periods of a read-write stage and switched on according to the control signal in at least part of time periods of an idle stage.

Disclosed herein is intravascular ultrasound (“IVUS”) system is disclosed which includes an IVUS console for generating a vessel contour trace and a blood flow image from an IVUS image. The IVUS console includes a communication interface; a memory circuit; an image output display; and a processor circuit configured to, when an interim vessel contour trace meets or exceeds accuracy criteria, display on the image output display a complete vessel contour trace comprising the interim vessel contour trace with user-interactable key nodes or control points and merge or superimpose a blood flow IVUS image with the complete vessel contour trace.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to perform computation operations of at least one neural network model associated with tensors, at least one memory circuit configured to store the tensors, a plurality of bus circuits operably coupled to the at least one processing core and the at least one memory circuit. The plurality of bus circuits configured to send the tensors from the at least one memory circuit to the at least one processing core responsive to receiving requests for read operations or write operations, and a controller operably coupled to the plurality of bus circuits, the controller configured to determine a priority of each of the tensors for each bus circuit for the read operations or the write operations.

There is disclosed in one example a computing apparatus, including: a hardware platform including a processor circuit and a memory circuit; first means for accessing a machine learning engine; second means for accessing a user interface; and instructions encoded within the memory to instruct the processor to: load into the machine learning engine via the first means an object prevalence model, including an enterprise-specific prevalence model; provide to the machine learning engine an object set from the enterprise; identify an enterprise-novel object from the object set; solicit and receive via the second means user-sourced feedback for the enterprise-novel object; and act according to the user-sourced feedback.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A robotic controller is provided for generating sequences of movement primitives for sequential tasks of a robot having a manipulator. The controller includes at least one control processor, and a memory circuitry storing a dictionary including the movement primitives, a pretrained learning module, and a graph-search based planning module having instructions stored thereon. The controller to perform steps acquiring a planned task provided by an interface device operated by a user, wherein the planned task is represented by an initial state and a goal state with respect to an object, generating a planning graph by searching a feasible path of the object for the novel task using the graph-search based planning module and selecting movement primitives from the dictionary in the pretrained learning module, wherein the pretrained learning module has been trained based on demonstration tasks, parameterizing the feasible path represented by the movement primitives as dynamic movement primitives (DMPs) using the initial state and goal state, and implementing the parameterized feasible path as a trajectory according to the selected movement primitives using the manipulator of the robot by tracking and following the parameterized for the planned task.

A circuit includes a memory circuit, and a power management circuit having a first circuit. The first circuit is configured to, in response to a first state of the first power management control signal and a first state of the second power management control signal, control supply of a first supply voltage to the memory circuit in accordance with a first power mode control signal. The first circuit is further configured to, in response to a second state of the first power management control signal, store a state of the first power mode control signal, and control supply of the first supply voltage to the memory circuit in accordance with the stored state of the first power mode control signal. The power management circuit is configured to, in response to a second state of the second power management control signal, disable a part of the first circuit.