1302 results about "Memory circuits" patented technology

The invention discloses a phase change memory and electronic equipment, the phase change memory comprises a comparator, a second switch, a third switch, a memory circuit, a selected digital line, a first switch and an unselected digital line, the memory circuit, the selected digital line, the first switch and the unselected digital line are connected in sequence, and the reference voltage of the unselected digital line is set in a reading operation through the first switch and the third switch; the reference voltage is in positive correlation with the second negative voltage, the second negative voltage is smaller than the first negative voltage, and compared with the reference voltage which is in positive correlation with the first negative voltage, the lower reference voltage can be generated, so that the overshoot current flowing through the memory cell at the opening moment is reduced, and the reading interference suffered by the memory cell is reduced.

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

The present application relates to the technical field of integrated circuits, relates to a computing-in-memory circuit based on BNN algorithm acceleration, and solves the problems in the prior art of a large circuit area, high energy consumption, and low energy efficiency of computing-in-memory. The circuit comprises: selecting a first algorithm network and a second algorithm network from a flexible RRAM storage array; inputting a plurality of rows of data into the first algorithm network and a multiply-accumulate module to obtain a multiply-accumulate result, and inputting the multiply-accumulate result into a shifter; the shifter shifting the multiply-accumulate result, outputting the shifting result to an adder-subtractor to obtain a sum-calculation result and outputting the sum-calculation result to a comparator; the comparator performing binarization on the sum-calculation result, outputting the binarized sum-calculation result to a second algorithm network, performing recalculation to output a column accumulate current, and sending the column accumulate current to a maximum value comparator output module; and the maximum value comparator output module determining a column having the maximum column sum as a classification result. While keeping the original network precision, the required circuit area is greatly reduced, the energy consumption is reduced, and the energy efficiency of the entire computing-in-memory circuit is improved.

Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.

The present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. The imaging device is formed in such a manner that a first stacked body in which a plurality of devices are stacked and a second stacked body in which a plurality of devices are stacked are bonded to each other. For example, a pixel circuit, a driver circuit of a pixel, and the like can be provided in the first stacked body, and a reading circuit of the pixel circuit, a memory circuit, a driver circuit of the memory circuit, and the like can be provided in the second stacked body. With these structures, the imaging device which is small can be formed. Furthermore, wiring delay or the like can be prevented by stacking circuits, so that high-speed operation can be performed.

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

An apparatus includes a cache memory circuit, and a hierarchal store queue circuit that further includes a primary queue and a secondary queue. The hierarchal store queue circuit may be configured to write incoming store requests to the primary queue in response to the primary queue currently having capacity, and to write incoming store requests to the secondary queue in response to the primary queue currently not having capacity. The hierarchal store queue circuit may be further configured to commit store requests to the cache memory circuit from the primary queue but not from the secondary queue. In response to a determination that the primary queue currently has capacity, the hierarchal store queue circuit may perform a transfer of at least one store request from the secondary queue to the primary queue.

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

A discrete three-dimensional (3-D) processor comprises vertically stacked and communicatively coupled first and second dice. The first die comprises memory arrays, while the second die comprises non-memory circuits and off-die peripheral-circuit components of the memory arrays. The total-number difference of the BEOL layers between the memory arrays and the off-die peripheral-circuit components is substantially larger than the total-number difference of the BEOL layers between the non-memory circuits and the off-die peripheral-circuit components.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

The invention discloses a ferroelectric memory circuit capable of improving an imprinting effect and an imprinting effect improving method, the ferroelectric memory circuit comprises a plurality of memory units distributed in rows and columns, each memory unit comprises a ferroelectric capacitor, one polar plate of each ferroelectric capacitor is connected to a plate line PL, the plate line PL is connected with a plate line voltage driving circuit, and the plate line voltage driving circuit is connected with a ferroelectric capacitor. The board line voltage driving circuit is provided with a signal input IN, and comprises a high-low level switching circuit which is used for outputting a high level to a board line PL or outputting a low level to the board line PL according to the high-low level of the signal input IN; and the high-level voltage selection circuit is connected to the at least two high-level voltage outputs and is used for applying the selected high-level voltage to the board line PL when the high level is output to the board line PL according to the signal input IN. The circuit structure of the ferroelectric memory is optimized and improved, the ferroelectric memory is tested before leaving a factory, and voltage compensation adjustment is carried out according to the test, so that memory unit failure possibly caused by an imprinting effect can be prevented, and the read-write frequency of the memory unit is obviously increased.

A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

The invention discloses a self-detection circuit and a storage device, the storage device comprises a storage circuit, a control circuit and a self-detection circuit, the self-detection circuit is coupled between the control circuit and the storage circuit, and the self-detection circuit comprises a built-in self-test module and a built-in self-test interface; wherein the built-in self-test module is connected to the control circuit through a built-in self-test interface and a first customized bus, and the built-in self-test module is configured to receive a test instruction from the control circuit through the first customized bus and the built-in self-test interface, and execute a self-test operation based on the test instruction to detect a damaged storage unit in the storage circuit, and corresponding dead pixel information is generated and stored in the storage circuit. Through the above mode, the self-detection circuit provided by the invention can perform dead pixel automatic test on the damaged storage unit in the storage circuit, reduces external operation, can obtain dead pixel information in the storage circuit in real time, and is high in automation degree, generalization degree and parallelization degree.

A method of operating a memory device including a memory cell array and a memory circuit includes receiving a first command from a controller, determining, in response to the first command, whether first device information stored in the memory circuit has an error, receiving, in response to the determining that the first device information has the error, a reset command from the controller, and performing a refresh operation on the memory circuit in response to the reset command. The first device information includes information about an operation parameter and an operating frequency of the memory device.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells connected to word lines and bit lines located on opposite sides of the memory cells. The memory cell may include gate all around transistors. A memory circuit according to the present disclosure also includes edge cells having word line tap structures configured to connect front side word lines with back side word lines. Some embodiments of the present disclosure provide an IC chip having memory cells with power rail on the front side and logic cells with power rail on the back side.

Provided in the embodiments of the present disclosure are a storage unit, a memristor array, a compute-in-memory circuit and an operation method. The storage unit comprises n weight units and a lateral gate transistor. Each of the n weight units comprises a first memristor element and a first switch element, a first electrode of the first memristor element being electrically connected to a first electrode of the first switch element, and a second electrode of the first memristor element being used as a second end of the corresponding weight unit and being used for receiving a first bit line signal. The second electrodes of the first switch elements of the N weight units are respectively used as the first ends of the corresponding weight units and are electrically connected to each other, and are electrically connected to a first end of the lateral gate transistor. The control electrodes of the first switch elements are respectively used for receiving different first word line signals. A second end of the lateral gate transistor is used for receiving a source line signal, and a control end of the lateral gate transistor is used for receiving a second word line signal.

Electro-optic (“EO”) computing systems for high bandwidth and high-capacity memory access via wavelength-division multiplexed (“WDM”) switching are provided herein. Examples of the EO computing system include one or more compute circuit packages, one or more memory circuit packages, and an optical switch connected between the compute and memory circuit packages.

A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.

An image sensor includes a logic die, including column readout circuits and bitlines connected to the column readout circuits. A sensor die is overlaid on the logic die. The image sensor includes an array of detector elements, each including a sensing circuit on the sensor die, which includes a photodiode, a floating diffusion node a charge sharing transistor coupled between the photodiode and the floating diffusion node, a reset transistor coupled to the floating diffusion node, and a source follower transistor. In each detector element, a pixel circuit on the logic die includes a select transistor, which has an input coupled to the output of the source follower and an output coupled to one of the bitlines. Two current memory circuits are coupled to the input of the select transistor and are configured to sense and output respective signals indicative of levels of noise in the detector element.

The invention provides a column memory circuit, a chip, an image sensor and an imaging apparatus. The column memory circuit comprises M * N memory bank modules, N read-out modules and a data transmission module, and a correlated double-sampling module of the column memory circuit is arranged in the read-out module; the first end of the memory bank module receives a first data signal, the second end of the memory bank module is coupled with the first end of the reading module corresponding to the memory bank module, and the second end of the reading module is coupled with the data transmission module; the memory bank module converts a received first data signal into a second data signal, the reading module performs correlated double sampling processing on the second data signal through the correlated double sampling module to obtain a third data signal, and the data transmission module outputs the third data signal. According to the column memory circuit, the area of the column memory circuit can be obviously reduced, the circuit performance can be well ensured, and the cost of an image sensor can be obviously reduced by adopting the column memory circuit provided by the invention.

A magnetoresistive memory device and an integrated memory circuit are provided. The magnetoresistive memory device includes a magnetic tunneling junction (MTJ) and a composite spin orbit torque (SOT) channel in contact with a terminal of the MTJ. The SOT channel includes: a first channel layer, configured to convert a portion of a charge current into an orbital current based on orbital Hall effect; and a second channel layer, covering the first channel layer, and configured to convert a portion of the charge current into a first spin current based on spin Hall effect, and to convert the orbital current to a second spin current.

A memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel portion, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel portion and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, so that power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are formed to be stacked; therefore, the length of a wiring between the circuits can be shortened, and a low-power consumption operation and a high-speed operation can be performed.

The invention discloses an instruction-driven coprocessor architecture design method for an in-memory computing platform of a high-performance magnetic memory. The instruction-driven coprocessor architecture design method comprises the following steps of: switching a magnetic memory into a normal mode or an in-memory computing mode by writing a corresponding operation code into a state register OP; the normal mode is used for the read-write function of a normal memory, and the in-memory calculation mode provides the function that the magnetic memory serves as a calculation unit; when the magnetic memory is used as a computing unit, the operation of in-memory computing consists of two memory access instructions, namely, an in-memory computing activation instruction and an in-memory computing address transmission instruction; the in-memory calculation activation instruction is used for activating an in-memory mode of the memory, and the in-memory calculation address transmission instruction is used for providing necessary control signals for in-memory calculation. On the premise that a memory protocol and an instruction set architecture are not changed, memory access and calculation instructions can be distinguished through the memory circuit with the changeable state, and the high-reliability, low-power-consumption and high-parallelism in-memory calculation architecture based on the magnetic memory is achieved.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

A memory circuit includes a first memory cell operatively accessible through a first access line and a second access line; a first read pass-gate transistor and a second read pass-gate transistor coupled to the first access line and second access line, respectively; a first sense amplifier coupled to the first access line and the second access line; a first read enable control circuit configured to generate a first read enable signal based on a clock signal; and a second read enable control circuit configured to generate a second read enable signal. The first read enable signal selectively transitions to a different logic state based on a first sense enable signal. The second read enable signal is configured to activate or deactivate both the first and second read pass-gate transistors, and the first sense enable signal is configured to activate or deactivate the first sense amplifier.