796 results about "Memory circuits" patented technology

In an implementation, a device includes: a first inverter; a first sense amplifier connected to the first inverter; a first match line connected to the first sense amplifier; a first analog content addressable memory cell including: a first pull-down transistor; a second pull-down transistor, the first pull-down transistor and the second pull-down transistor being connected in series between the first match line and a reference node; a first memory circuit configured to store a first upper bound of a first range and to activate the first pull-down transistor when an analog input value is less than the first upper bound of the first range; and a second memory circuit configured to store a first lower bound of the first range and to activate the second pull-down transistor when the analog input value is greater than the first lower bound of the first range.

Systems and methods for providing memory access commands to memory circuitry using a gap controlled multi-clock cycle memory command protocol is described. More than one memory commands are combined into one multi-clock cycle memory command using gap controlled multi-clock cycle memory command protocol. The number of clock cycles included in the gap between two clock cycles in the multi-clock cycle memory command is controlled and adjustable.

A cache writeback circuit is disclosed for writing back, without invalidating, dirty cache lines. The cache writeback circuit is configured to enter an active state based on detecting a trigger condition indicative of cache misses to a memory cache circuit within a memory hierarchy of a computer memory subsystem causing cache line eviction activity. During the active state, the cache writeback circuit is configured to identify a set of dirty cache lines in the memory cache circuit, and write back, without invalidating, cache lines of the identified set of dirty cache lines from the memory cache circuit to a memory circuit within a lower level of the memory hierarchy, such as DRAM. The cache writeback circuit may further be configured to identify the dirty cache lines via a cache walk operation, which can be suspended, for example, when a higher-priority cache operation occurs.

The present application discloses a computing-in-memory circuit, chip and electronic device, wherein the computing-in-memory circuit comprises: a resistive random access memory array, a clamping circuit, a current mirror and an analog-to-digital conversion circuit; the clamping circuit is connected between a signal input terminal and the resistive random access memory array, configured to input clamping voltage signal to the N resistive random access memories selected of the resistive random access memory array, wherein N is an integer and N≥2; the current mirror is connected between the resistive random access memory array and the analog-to-digital conversion circuit, configured to output convergence current to the analog-to-digital conversion circuit based on the N-way currents output from the N resistive random access memories selected; the analog-to-digital conversion circuit configured to convert the convergence current to a digital signal.

The invention provides an automatic design method and equipment of a storage circuit and a storage medium. The method comprises the following steps: acquiring demand parameters input by a user in a compiler; importing a plurality of circuit units after the standard memory circuit is disassembled into a compiler; determining a target circuit architecture according to the demand parameters; calling a plurality of corresponding circuit units from a compiler according to the demand parameters; and splicing the called circuit units to positions corresponding to the target circuit architecture to obtain a target storage circuit meeting the demand parameters. On this basis, the demand parameters of the user and the plurality of circuit units obtained by disassembling are input into the compiler, and the target circuit architecture is determined through the compiler, the plurality of corresponding circuit units are called, and the splicing of the plurality of circuit units is executed, that is, the whole design of the target storage circuit can be automatically completed in the compiler. The manual participation degree is reduced, the overall efficiency is high, the possibility of manual misjudgment can be completely eradicated, and the reliability of the whole circuit design is ensured.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to process computations of the at least one neural network model comprising at least one tensor, at least one memory circuit configured to store the at least one tensor, a bus circuit, electrically coupled to the at least one processing core and the at least one memory circuit, configured to transmit the at least one tensor based on a memory access operation instruction, and a controller configured to control a priority of a memory access operation for each tensor of the at least one processing core.

Data stored in a memory circuit may be encrypted using client keys that need to be available for high-speed data processing and yet held securely to avoid unauthorized access to the encrypted data. A secure processor circuit in a processor-based system obtains client keys associated with client applications and generates secure key-encryption keys that are used to encrypt the client keys so the client keys can be securely stored in the memory circuit. In some examples, data keys for encrypting data blocks associated with the client application may be generated from the client key, encrypted by a data key-encryption key generated in the secure processor circuit, and stored in the memory circuit. In such examples, because the client keys and data keys are encrypted while in memory, they are safer from software attacks on the memory circuit, which improves the security of the encrypted data blocks.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

The invention provides a memory circuit which at least comprises an amplifier, the amplifier is provided with a first node and a second node, the first node is electrically connected with a first data line, and the second node is electrically connected with a first reference data line. The amplifier is used for amplifying the voltage difference between the first data line and the first reference data line; the first end of the first transmission tube is electrically connected with the first node, the second end of the first transmission tube is electrically connected with a second data line, and the first transmission tube is used for being switched on according to a control signal in at least part of time periods of a read-write stage and switched on according to the control signal in at least part of time periods of an idle stage.

Disclosed herein is intravascular ultrasound (“IVUS”) system is disclosed which includes an IVUS console for generating a vessel contour trace and a blood flow image from an IVUS image. The IVUS console includes a communication interface; a memory circuit; an image output display; and a processor circuit configured to, when an interim vessel contour trace meets or exceeds accuracy criteria, display on the image output display a complete vessel contour trace comprising the interim vessel contour trace with user-interactable key nodes or control points and merge or superimpose a blood flow IVUS image with the complete vessel contour trace.

According to one example of the present disclosure, a system may be provided. The system may comprise at least one processing core configured to perform computation operations of at least one neural network model associated with tensors, at least one memory circuit configured to store the tensors, a plurality of bus circuits operably coupled to the at least one processing core and the at least one memory circuit. The plurality of bus circuits configured to send the tensors from the at least one memory circuit to the at least one processing core responsive to receiving requests for read operations or write operations, and a controller operably coupled to the plurality of bus circuits, the controller configured to determine a priority of each of the tensors for each bus circuit for the read operations or the write operations.

There is disclosed in one example a computing apparatus, including: a hardware platform including a processor circuit and a memory circuit; first means for accessing a machine learning engine; second means for accessing a user interface; and instructions encoded within the memory to instruct the processor to: load into the machine learning engine via the first means an object prevalence model, including an enterprise-specific prevalence model; provide to the machine learning engine an object set from the enterprise; identify an enterprise-novel object from the object set; solicit and receive via the second means user-sourced feedback for the enterprise-novel object; and act according to the user-sourced feedback.

A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

A robotic controller is provided for generating sequences of movement primitives for sequential tasks of a robot having a manipulator. The controller includes at least one control processor, and a memory circuitry storing a dictionary including the movement primitives, a pretrained learning module, and a graph-search based planning module having instructions stored thereon. The controller to perform steps acquiring a planned task provided by an interface device operated by a user, wherein the planned task is represented by an initial state and a goal state with respect to an object, generating a planning graph by searching a feasible path of the object for the novel task using the graph-search based planning module and selecting movement primitives from the dictionary in the pretrained learning module, wherein the pretrained learning module has been trained based on demonstration tasks, parameterizing the feasible path represented by the movement primitives as dynamic movement primitives (DMPs) using the initial state and goal state, and implementing the parameterized feasible path as a trajectory according to the selected movement primitives using the manipulator of the robot by tracking and following the parameterized for the planned task.

A distance measurement device includes a light emitter for transmitting pulsed light and a light receiver for detecting reflected light from an object, providing an output signal. The device has at least one of a circuit or a processor with memory storing executable computer program code. The circuit or processor calculates an object distance using the time of flight of the pulsed light. Additionally, a histogram representing received light intensity for each time of flight is generated from the output signal. The device determines whether the object is within a short-distance range based on the timing of a peak in the histogram, and calculates the object distance using both a feature value related to the number of light reflections and the timing of the peak's decline.

A memory circuit includes a memory cell, a bit line, a bit line bar, a pass-gate transistor coupled to the memory cell and the bit line, a sense amplifier coupled to the bit line, the bit line bar and the pass-gate transistor, and a pre-charge circuit coupled to the first node, and configured to pre-charge the first node to a pre-charge voltage in response to a pre-charge control signal. The sense amplifier includes a first path between the bit line and the bit line bar. The first path includes a first isolation transistor configured to receive an isolation control signal, and being coupled between the bit line and a first node, and a first inverter configured to receive a sense amplifier enable signal, and being coupled between a second node and a third node.

A system includes a Visual See-Through (VST) pipeline circuit capable of processing image data. The VST pipeline circuit is embodied as a die. The VST pipeline circuit includes an Image Signal Processing (ISP) circuit and a Display Processing Unit (DPU) circuit coupled to the ISP circuit. The VST pipeline circuit includes a memory circuit coupled to the ISP circuit and to the DPU circuit. The memory circuit is configured to implement a plurality of buffers that facilitate low latency operation of the ISP circuit and the DPU circuit.

The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

User feedback in memory training startup sequences is described. In one or more implementations, a system includes a plurality of memory circuits configured as a system memory, and at least one processing circuit. The processing circuit executes platform initialization code configured to partially train a subset of memory circuits from a plurality of memory circuits during an initial stage of a startup sequence, and fully train each memory circuit of the plurality of memory circuits during a subsequent stage of the startup sequence. The processing circuit further executes basic input output system code configured to use the subset of memory circuits to output user feedback during the initial stage, and use the system memory to complete the startup sequence during the subsequent stage.

A decoder includes memory and circuitry coupled to the memory. Using the memory, the circuitry: decodes, from a bitstream, a base data unit of a face image related to a face video and one or more enhancement data units of the face image; decodes, from the bitstream, geometric information corresponding to each of frames of the face video; and generates the face video from the base data unit, the one or more enhancement data units, and the geometric information. In the bitstream, the base data unit is added to a data set corresponding to a first frame that is a frame of the face video. In the bitstream, the one or more enhancement data units are added to one or more data sets corresponding to one or more second frames of the face video.

A leak detection system is configured to provide vehicle-specific leak detection for a vehicle. The leak detection system includes a memory circuit having a plurality of leak detection instructions matched with vehicle identification information. The system additionally includes an ultraviolet light source and a camera configured to capture an image of an area illuminated by the ultraviolet light source. A processor is in operative communication with the memory circuit and the camera. The processor is configured to facilitate identification of at least one of the plurality of leak detection instructions in response to receipt of vehicle identification information associated with the vehicle, and compare the image captured by the camera to a known image of the vehicle to determine presence and location of a leak.

A memory circuit includes a memory cell array, a data line selectively coupled to memory cells of the memory cell array, a dummy cell coupled to a reference line, and a comparator coupled to the data line and the reference line. The memory circuit, during a first read operation, charges the data line through a first selected memory cell of the memory cell array and charges the reference line through the dummy cell, during a second read operation, discharges the data line through a second selected memory cell of the memory cell array and discharges the reference line through the dummy cell, and during each of the first and second read operations, outputs a voltage from the comparator having one of a low or high voltage level based on a difference between a data line voltage on the data line and a reference voltage on the reference line.

An 8T CFET SRAM is proposed to perform the parallel weighted-sum operation to speed-up the inference process. A circuit includes a memory array including memory cells, each of the memory cells including a plurality of transistors, and coupled to a first word line and a second word line, and configured to receive a first data element, store a second data element, and provide a multiplication value of the first data element and the second data element. The first word line is configured to receive a first logic state corresponding to the first data element being binarized, and the second word line is configured to receive a second logic state corresponding to the first data element being binarized. A first internal node among the transistors is configured to store a first logic state corresponding to the second data element being binarized, and a second internal node among the transistors is configured to store a second logic state corresponding to the second data element being binarized.

The present invention provides a recording head that can update eigenvalues ​​while suppressing increases in memory capacity and head size. [Solution] The recording head 810 has a memory section 20 configured using a fuse element or an antifuse element. The memory section 20 has a main memory circuit M0 for storing eigenvalues ​​related to the recording head 810, and correction memory circuits M1 and M2 for storing correction values ​​for updating the eigenvalues.

A memory circuit comprises: a first memory cell configured to store a first data bit; a second memory cell configured to store a second data bit; a sampling amplifier coupled to the first and second memory cells, respectively, via a data bit line and a reference bit line; a first switch; and a second switch. The first switch is selectively coupled between the data bit line and a first input node of the sampling amplifier, and the second switch is selectively coupled between the reference bit line and a second input node of the sampling amplifier.

A chip comprises a plurality of signal receiving circuits, a transceiver circuit and a memory circuit. The plurality of signal receiving circuits are set at different locations on the chip. The transceiver circuit includes a dynamic switch circuit and a baseband processor. The dynamic switch circuit is configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits. The baseband processor is configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and obtain a data packet of an input radio-frequency signal received by an external antenna. The memory circuit is configured to store the frequency spectrum and magnitude of the to-be-analyzed signal, and transmit the frequency spectrum and magnitude to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.

A compare circuitry that can be implemented in a memory circuit includes: selection logic coupled to a sense amplifier of the memory circuit, the selection logic structured to receive a sense amplifier enable signal, a column output from the sense amplifier, and a column output bar from the sense amplifier, wherein the selection logic is structured to pass through the column output and the column output bar when the sense amplifier enable signal is active and hold the column output and the column output bar at a same value when the sense amplifier enable signal is inactive; and an XNOR gate structured to receive the column output and the column output bar passed through the selection logic, a data input, and a data input bar and output a bit compare output.

Memory circuits with tracking cells are provided. A memory circuit includes a memory array comprising a plurality of first memory cells. The memory circuit includes a tracking column comprising one or more second memory cells. Each of the second memory cells is coupled to a first metallization layer disposed on a first side of a substrate and a second metallization layer disposed on a second side of the substrate, the second side opposite to the first side. The second metallization layer is configured to receive, from the second memory cells, a level of an internal node of a memory node. The first metallization layer is configured to provide, to the second memory cells, at least one supply voltage.

A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a memory circuit configured to receive a clock signal and generate an output signal. The memory circuit includes a timing delay circuit. The semiconductor device includes a design-for-test (DFT) circuit comprising a shadow latch. The DFT circuit is configured to receive an output of the timing delay circuit, and generate a DFT output signal via the shadow latch. A first output hold of the output signal is about equal to a second output hold of the DFT output signal.

A method of operating a memory circuit is disclosed. A memory circuit includes a memory array having a memory portion and a spare portion. The method includes receiving a first write command to a first memory address, where the first memory address has a state mapped to a first backup memory address, and where the first memory address corresponds to a first memory location in the memory portion, and the first spare memory address corresponds to a first spare memory location in the spare portion. The method further includes, in response to the first write command, performing a first write operation by attempting to write the first data to the first memory location; determining whether the first write operation is successful; and in response to success of the first write operation, de-mapping the first memory address from the first standby memory address.