26733 results about "Electric charge" patented technology

In electronic displays or imaging units, the control of pixels is achieved by an array of transistors. These transistors are in a thin film form and arranged in a two-dimensional configuration to form switching circuits, driving circuits or even read-out circuits. In this invention, thin film transistors and circuits with indium oxide-based channel layers are provided. These thin film transistors and circuits may be fabricated at low temperatures on various substrates and with high charge carrier mobilities. In addition to conventional rigid substrates, the present thin film transistors and circuits are particularly suited for the fabrication on flexible and transparent substrates for electronic display and imaging applications. Methods for the fabrication of the thin film transistors with indium oxide-based channels are provided.

A battery-powered, modular surgical device comprising an electrically powered surgical instrument that requires a pre-determined minimum amount of electrical energy to complete a surgical procedure, and a power module assembly that has a battery that powers the surgical instrument and has a current state of electrical charge, and a control circuit that is electrically coupled to the battery and the surgical instrument and has a memory and a microprocessor. The microprocessor determines the current state of electrical charge of the battery, compares the current state of electrical charge to the pre-determined minimum amount of electrical energy, permits the battery to discharge if the current state of electrical charge is above the pre-determined minimum amount of electrical energy, and maintains the battery in a non-discharge state if the current state of electrical charge is below the pre-determined minimum amount of electrical energy.

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

A solid-state image sensor of a charge sorting method used in a time-of-flight measurement method, in which noise derived from background light, which is caused by the reflection light from the subject derived from background light is eliminated, reflection light from the subject derived from a predetermined light source, which is previously set in the solid-state image sensor, is effectively extracted as a signal component to achieve high sensitivity and low noise, which is a solid-state image sensor that is equipped with a plurality of charge-storage sections, discriminates photoelectrons generated by incoming light on the incoming timing and sort to the above-described plurality of charge-storage sections, and measures the timing of the incoming light, in which the sensor has: a plurality of capacitors that capable of conducting to the plurality of charge-storage sections; and a control section that controls a conducted state between the above-described plurality of charge-storage sections and the above-described plurality of capacitors, in which by selectively conducting the above-described plurality of charge-storage sections and the above-described plurality of capacitors by the control of the above-described control section, the difference component of charge stored in the above-described plurality of charge-storage sections is extracted.

A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The silicon content is gradually changed throughout the duration of the HfxSiyOz deposition process. The etching rate for the HfxSiyOz layer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfxSiyOz layer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). To compensate for this coupling, the read or programming process for a given memory cell can take into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, a process can be performed that includes sensing information about the programmed state of an adjacent memory cell (e.g., on an adjacent bit line or other location).

Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.