190 results about "Memory control" patented technology

Cache, cache management method, and electronic device. The cache includes: multiple cache lines, a first read request queue and a second read request queue; a first read request queue is configured for storing and sending a first read request to a memory controller; the first read request is configured for requesting data from memory and storing the data in the memory controller; the number of the first read requests stored in the first read request queue is greater than that of the multiple cache lines; the second read request queue is configured for storing and sending a second read request to memory controller; and the second read request corresponds one-to-one with the first read request, and the second read request is used to request data corresponding to the first read request from the memory controller when a cache line corresponding to the first read request is idle

The present disclosure provides an integrated circuit comprising a memory controller configured to transmit information stored in a memory to a processing unit. An example memory controller includes an error detection circuit configured to detect an error in the information by implementing an error correcting code algorithm, and to generate an interrupt signal in the event of detection of at least one error in the information and a transmission control circuit configured to transmit the interrupt signal to the processing unit only when the error is detected for the first time in the information by the error detection circuit.

This invention provides an eFuse control device and method. The method includes: the eFuse control device receiving eFuse-based programming instructions sent by an external accessor, the programming instructions including read operation instructions and write operation instructions; the external accessor including a central processing unit and a CP test machine; the eFuse control device, based on the programming instructions and reading corresponding information values ​​from the eFuse memory, determining whether to perform corresponding read / write operations on the eFuse memory based on the information values, and returning corresponding data and status information; the information values ​​include: an enable control word stored in the control group area of ​​the eFuse memory. This method effectively improves the flexibility of data management in the eFuse memory while ensuring the security of data in the eFuse memory.

This invention provides an on-chip FLASH functional testing system based on an off-chip SPI master, relating to the field of integrated circuit and memory control technology. The system receives operation commands and corresponding data from an off-chip SPI master via on-chip SPI and transmits them to a controller with an independent SPI interface for the on-chip FLASH. The controller executes corresponding operations on the on-chip FLASH based on the operation commands and data, and transmits the execution results back to the off-chip SPI master via on-chip SPI. The off-chip SPI master generates functional test results for the on-chip FLASH based on the execution results fed back by the controller. The controller of this invention enables the off-chip SPI master to access and functionally test the on-chip FLASH in the same way as the off-chip FLASH. The entire testing process is transparent to the upper-layer system, requiring no additional adaptation logic, significantly improving the simplicity of the testing process and the system integration.

A memory device operates with multiple internal ranks that enable concurrent access. The memory device receives multiple commands from a memory controller, which are assigned to different individual ranks and executed concurrently. Data is transferred between the memory device and the memory controller in an interleaved data pattern that includes interleaved data associated with multiple commands for multiple different ranks.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

A data storage apparatus may include a storage device; a buffer memory device configured to temporarily store write data and a mapping table; and a memory controller configured to control the storage device to program the write data. The memory controller is configured to when externally receiving write commands including a logical addresses, store the logical addresses by mapping the logical addresses to physical addresses sequentially stored in the mapping table in a sequence in which the write commands are received, and when a program operation corresponding to a first write command fails, invalidate first mapping information corresponding to the first write command and update the first mapping information by allocating a new physical address to a logical addresses including the first write command in response to a reprogram command generated with respect to the first write command.

Methods, apparatus, and systems for managing parity data generation are provided. In one aspect, a memory system includes a memory device and a memory controller. The memory device includes N dies, each die including M memory surfaces. Each of the M memory surfaces includes a first memory block, the first memory block including memory pages, each memory page being associated with a word line in a set of sequentially numbered word lines. The memory controller is configured to: generate first parity data for first data to be written to a memory page associated with a k-th word line of the first memory block of each of the M memory surfaces of the N dies; and generate second parity data for second data to be written to memory pages associated with at least the (k-1)-th and (k+1)-th word lines of the first memory block of each of the M memory surfaces of the N dies.

A memory system, a method for controlling the refresh of a memory device, and a memory device are provided. The memory system includes a memory controller and a memory device. The memory controller periodically generates refresh commands at an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during the refresh cycle time. The memory device includes: a memory cell array including memory cells connected to the plurality of word lines; a temperature sensor configured to provide temperature information by measuring the operating temperature of the memory cell array; and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller changes the hammer rate, which is the number of hammer executions per unit of hammer refresh operation performed during the refresh cycle time relative to the number of normal executions per unit of normal refresh operation performed during the refresh cycle time.

A shunt regulator is provided which can reduce a consumption current at the time of normal operation even if a circuit including a large current flowing at the time of operation is included. The shunt regulator includes a capacitor connected between an output terminal and a ground terminal, a voltage dividing circuit and an output transistor connected between the output terminal and the ground terminal, an error amplifier which controls the output transistor based on a voltage of an output terminal of the voltage dividing circuit and a reference voltage, a nonvolatile memory, a memory control circuit which outputs a read signal of data to the nonvolatile memory, and a voltage detection circuit which detects that the voltage of the output terminal reaches a prescribed voltage which allows a data read operation of the nonvolatile memory, outputs a detection signal to the memory control circuit, and an operation current of the nonvolatile memory is supplied from the capacitor.

This disclosure provides a mapping table caching control method, a mapping table query method, and related apparatus. The method includes: when the current mapping relationship is continuous with the previous mapping relationship cached in the memory controller, incrementing the continuity count by 1 and caching the current mapping relationship in the memory controller; when the current mapping relationship is not continuous with the previous mapping relationship, comparing the continuity count with a preset threshold; if the continuity count is greater than the preset threshold, organizing the continuous mapping relationships cached in the memory controller using a combination of a first data structure and a linked list and storing them in a first mapping table cache unit; clearing the continuous mapping relationships cached in the memory controller; caching the current mapping relationship in the memory controller and setting the continuity count to 1; the preset threshold is a positive integer greater than 1, which improves storage space utilization and the efficiency of updating the mapping table, and reduces the table refresh frequency.

The present invention relates to a memory controller and a data processing method. The memory controller includes an error correction code engine, a buffer memory, and a microprocessor. The microprocessor performs a repeated read operation on a memory device in response to a first decoding result of intended data to obtain a plurality of read results of a data chunk containing the intended data, wherein the data chunk includes a plurality of bits. The microprocessor further performs a data reconstruction and correction procedure based on the read results of the data chunk. In the data reconstruction operation, the microprocessor determines a bit value corresponding to a bit of the data chunk based on the read results of the data chunk to generate a reconstructed data chunk. In the error correction operation, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the intended data.

A memory controller for a dynamic random-access memory (DRAM) is disclosed. The memory controller includes control circuitry that is configured to transmit, via a command / address (CA) interface, a command to place the DRAM into a mode that causes the DRAM to perform a self-refresh operation. The memory controller is configured to receive address information recorded by the DRAM while operating in a test-during-self-refresh mode. The address information identifies memory cells internally read and evaluated for an error by the DRAM during the self-refresh operation.

According to some example embodiments an operating method of a memory controller includes buffering first user data received from a host in a first region of a buffer memory corresponding to a first memory region of a memory device, receiving a flush request from the host, duplicating the first user data in a second region of the buffer memory corresponding to a second memory region of the memory device, padding, as padded data, the first user data duplicated to the second region with dummy data, programming the padded data in the second memory region of the memory device, buffering second user data received from the host in the first region, and programming, in the first memory region of the memory device, the first user data buffered in the first region and the second user data buffered in the first region.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a column selection control circuit that combines outputs of the state machine and the set of registers to trigger an appropriate column during an appropriate clock cycle, available at a start of a corresponding clock cycle. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

A storage system of one embodiment of the present application includes a substrate including a core portion, a plurality of first and second pad electrodes provided over a first surface, and a plurality of third and fourth pad electrodes provided over a second surface opposite to the first surface; a memory controller provided on the first surface side; a nonvolatile memory provided on the first surface side; a first member provided on the second surface side; a second member provided on the second surface side; a plurality of first electrodes respectively connected between the memory controller and each of the plurality of first pad electrodes; a plurality of second electrodes respectively connected between the nonvolatile memory and each of the plurality of second pad electrodes; a plurality of third electrodes respectively connected between the first member and each of the plurality of third pad electrodes; and a plurality of fourth electrodes respectively connected between the second member and each of the plurality of fourth pad electrodes. Each of the plurality of first pad electrodes and each of the plurality of third pad electrodes are provided at positions symmetrical with respect to an imaginary surface passing through a center line in a thickness direction of the substrate. The plurality of second pad electrodes and the plurality of fourth pad electrodes are provided at positions symmetrical with respect to the imaginary surface.

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

The application relates to an address processing device, method, chip and electronic equipment. In the address processing device, a memory control module is used for detecting whether there is a free address in a memory module when the address processing device works in a memory control mode and a FIFO output module is not full, and if there is, the free address is written into the FIFO output module; a bitmap control module is used for detecting whether there is a free address in a bitmap register when the address processing device works in a bitmap control mode and the FIFO output module is not full, and if there is, the free address is written into the FIFO output module; and the FIFO output module is used for receiving an address allocation request and outputting the free address to a sending end of the address allocation request when the FIFO output module is not empty. The address allocation delay is greatly reduced.

The application provides a memory initialization device, method and computer system, wherein the memory initialization device mainly comprises a first processor core and a memory control system comprising at least one second processor core. During the memory initialization process, the first processor core can call the second processor core to perform the memory initialization. The embodiment of the application is beneficial to shorten the memory initialization time.

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in a plurality of groups, and circuits coupled to the memory devices. The circuits including circuitry configurable to receive from the memory controller a system clock and input control and address (C / A) signals, and to generate a module clock signal and module C / A signals in response to the system clock and input C / A signals. The circuits further include circuitry configurable to generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and to output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices.

The application belongs to the field of memory control, and provides a memory control method and a memory device. The method comprises the following steps: in response to a voltage abnormal event, obtaining an operation state of a memory module and determining an abnormal level; if the operation state is busy, sending a transmission suspension command to a host system, and judging whether the memory module supports an operation suspension function; if the memory module supports the operation suspension function, sending a suspension execution command, otherwise marking that the operation needs to be re-executed; recording an operation context containing a progress parameter, and writing the operation context into a non-volatile backup area when a supply voltage is higher than a backup voltage threshold; setting a timing duration according to the abnormal level; if the supply voltage returns to normal before the timing duration expires, reading the operation context and continuing to execute the suspended operation from a suspension point. The application executes differentiated interruption protection according to hardware capability when the voltage is abnormal, and realizes breakpoint continuation after the voltage returns to normal, thereby effectively improving the data reliability of the memory device in a severe power supply environment.

The present invention provides a memory control device, a memory control method, and a program capable of storing information related to alarms issued in a plant. [Solution] The system includes a storage control means 351 that stores multiple alarm information indicating a failure or abnormality of plant equipment in a storage unit 34, and stores multiple alarm identification information identifying the alarm information in the storage unit 34, wherein the multiple alarm information stored in the storage unit 34 includes first alarm information which indicates a failure or abnormality of first equipment of first plant, and second alarm information which indicates a failure or abnormality of second equipment of second plant, and the multiple alarm identification information stored in the storage unit 34 includes first alarm identification information which identifies the first alarm information, and second alarm identification information which identifies the second alarm information, wherein at least a part of the first alarm identification information and the second alarm identification information are common.

Various aspects relate to a memory module including: a memory interface; a storage device for persistently storing data; a non-volatile memory device providing a memory storage for persistently storing data and providing a write buffer configured to receive, via the memory interface, and to store corresponding data to be written to the memory module; and a memory controller configured to write the corresponding data selectively from the write buffer to the storage device or to the memory storage.

An operation method of a storage device and a memory controller is provided. The storage device includes a memory device having a plurality of memory blocks and a memory controller. The memory controller is configured to control a garbage collection operation of the memory device. The memory controller is further configured to select, by using a reinforcement learning model, a victim block and a target block for performing the garbage collection operation among the plurality of memory blocks, according to state information of each of the plurality of memory blocks and feature information of data written in each of the plurality of memory blocks.

This invention provides a DNN in-memory computing acceleration circuit and its control method based on a hybrid TFET-CMOS in-memory multiplication unit, belonging to the fields of semiconductor integrated circuit design and artificial intelligence hardware technology. The circuit includes a hybrid TFET-CMOS in-memory multiplication array, an in-memory control module, a low-power shift-add tree module, a ReLU activation module, a selection circuit, word line and bit line driving modules, and an input feature circuit. It utilizes the extremely low off-state current of TFET devices and the high driving capability of CMOS to construct a hybrid TFET-CMOS in-memory multiplication unit, significantly improving write performance and read / write stability while maintaining microwatt-level standby power consumption. Through a bit-serial input strategy combined with a reusable low-power shift-accumulate tree module, it achieves dynamic physical mapping of multi-layer neural network architecture and time-division multiplexing of hardware resources. This invention effectively eliminates the risk of read interference during in-memory computing, exhibits ultra-low static power consumption and high energy efficiency in sparse event-driven scenarios, and achieves end-to-end highly robust intelligent inference.

A memory die estimates a bit error rate (BER) of a fuzzy program operation and uses the BER to determine whether to decode fuzzy program data on the memory die for a fine program operation. A controller on the die receives data from a storage device and generates parity pages based on the data. The controller performs a fuzzy program operation to write the data to memory cells in a block. The controller separates states in the memory cells into categories based on values of the parity pages associated with the states. The controller also performs a soft bit sensing operation and estimates a BER of the memory cells based on the soft bit sensing operation. Based on the BER, the memory controller performs on-die decoding of fuzzy program data with the parity pages or transfers the fuzzy program data to the storage device for decoding.

An electronic device includes a first non-volatile memory (NVM), a security device and a system on chip (SOC). The first NVM includes a non-security region and a security region. The security device includes a second NVM, a second memory controller and a memory processor. The SOC includes a main processor, a first memory controller and a security processor. In a low power mode, the memory processor is configured to provide, to the second memory controller, in response to a first write request signal, a first control command and a first security data, and the second memory controller is configured to provide, to the second NVM, in response to the first control command, a first program command, a first address, and the first security data.

Provided is an integrated circuit device including a memory storing trim data therein, a sleep register inputting the trim data to a sleep function block, a normal register inputting the trim data to a normal function block, a memory controller loading the trim data stored in the memory into the sleep register or the normal register, and a wake controller loading the trim data stored in the normal register into the sleep register via the memory controller upon first self-wake-up after power-up so as to allow the memory to be loaded first-time only after the power-up.