2060 results about "Memory control" patented technology

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

The embodiment of the invention provides a memory recovery method and device, equipment and a medium, the method is executed by computer equipment deployed with a container, and the container comprises a quality service agent component and a memory recovery agent component. The method comprises the following steps: determining a to-be-recycled memory node in a memory control group managed by a container through a quality service agent component, and transmitting the to-be-recycled memory node to a memory recycling agent component; obtaining a memory usage amount and a memory recovery index corresponding to the to-be-recovered memory node through the memory recovery agent component, and determining a memory recovery amount corresponding to the to-be-recovered memory node according to the memory usage amount and the memory recovery index; and calling a memory recovery interface through the memory recovery agent component, and recovering the physical memory in the memory node to be recovered based on the memory recovery amount. By implementing the embodiment of the invention, the memory resource utilization rate can be improved.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module, the memory module is provided with a plurality of chips, each chip is provided with a plurality of planes, and each plane is provided with a plurality of entity blocks. The method comprises the following steps: acquiring a chip enabling number of a memory module; selecting a target allocation method from a plurality of allocation methods according to the chip enabled number, the plurality of allocation methods including a first allocation method based on a plurality of chips and a second allocation method based on a plurality of planes; and dividing the plurality of entity blocks into a plurality of super blocks based on a target allocation method. Thus, the allocation strategy of the super blocks is optimized through the target allocation method, the utilization rate of the entity blocks in the memory module is improved, and meanwhile the garbage collection efficiency is improved.

The invention belongs to the technical field of artificial intelligence chip and robot control, and relates to a heterogeneous calculation and control fusion chip control system and method, a robot and a storage medium. A GPU, an NPU, a BPU and an MCU are integrated in a central large core cluster, a communication network subunit and a memory control subunit are matched, and a low-delay data channel is constructed in a chip, so that perception, cognition and control instructions can be directly interacted, the cross-chip communication delay is reduced, and the real-time performance is improved. The three-level cache module is accessed through the memory control subunit, high-bandwidth sharing and centralized scheduling are achieved, data migration is reduced, the bandwidth bottleneck is relieved, and the complex task processing efficiency is improved. A trust root subunit is arranged in each unit, chip-level trusted verification and access isolation are provided, and the reliability under key action control and security sensitive scenes is enhanced.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

The invention relates to a heterogeneous trusted execution environment architecture construction method and device, and the method comprises the following steps: constructing a tensor analyzer which is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; and providing memory protection with uniform tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

A memory device may include a first main memory configured to store an address mapping table, at least one second main memory configured to store data received from a host device, and a memory controller configured to, compressively convert a host physical address set received from the host device into a device physical address set indicating a range of physical addresses in the at least one second main memory associated with the host physical address set, generate at least one address mapping table entry based on the device physical address set, the at least one address mapping table entry associated with at least one device physical address subset associated with the device physical address set, and store the at least one address mapping table entry in the address mapping table of the first main memory.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

A storage device includes a memory that includes a firmware image area, and a memory controller that receives a first firmware image that includes a firmware signature, firmware data, a first certificate that includes a first certificate public key, and a second certificate that includes a second certificate public key. The memory controller verifies the first certificate using the second certificate public key, compares a hash value of the firmware data with the firmware fingerprint when the first certificate is verified, verifies the firmware signature using the first certificate public key when the hash value of the firmware data matches the firmware fingerprint, and stores the first firmware image in a firmware image area when the firmware signature is verified.

A logic die and a semiconductor device including the same are provided. The semiconductor device includes a logic die including a memory controller, an interface circuit, and a plurality of TSVs arranged in a TSV region. A plurality of memory dies are vertically stacked on the logic die and connected to the plurality of TSVs. The memory controller operates in a first voltage domain, and the plurality of memory dies operate in a second voltage domain. The interface circuit includes a plurality of TSV circuit blocks connected to the plurality of TSVs. Each TSV circuit block is configured to switch a voltage level of a signal transmitted via a corresponding TSV between a first voltage level in a first voltage domain and a second voltage level in a second voltage domain.

The invention belongs to the technical field of cache prefetching optimization of a firmware layer of a computer storage system, and particularly provides a memory control method, a storage device, a medium and equipment.The instantaneous flow is effectively filtered and persistent hotspot data is accurately recognized through a three-layer structure of combining a first-stage hotspot filtering module with a window cache, a view queue and a protection queue; the second-stage continuous access filtering module dynamically judges a continuous access mode by means of mean-variance statistics of an annular buffer area, and accidental continuous triggering of prefetching is avoided; and the third-stage random access judgment module prohibits invalid prefetching and effectively distinguishes access modes. The pre-fetching bandwidth is limited through the token bucket algorithm, the global priority queue of the skip list is combined, it is ensured that the priority of the write task is higher than that of the pre-fetching task, pre-fetching and foreground I / O resources are isolated, delay jitter control over foreground key I / O can be achieved during full-load pre-fetching, and the problem that delay soaring is caused when pre-fetching preempts the resources is solved.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

Control circuitry for memory includes a state machine including a number of state elements corresponding to a maximum number of available columns of a blast operation for memory; a set of registers including a corresponding register for each state element; and a last cycle detection circuit structured to combine outputs of the set of registers with the outputs of the state machine to generate a last cycle signal that goes high on a rising edge of a closing clock of a multi-cycle operation. The state machine receives a clock and various inputs associated with a start of memory operations and provides intermediate state element outputs and a final state element output as the outputs. Each register of the set of registers is available to store, from an address enable signal, a value indicating that a column in memory to which that register corresponds is to be accessed.

The invention relates to a non-volatile memory erase scheme. Methods, systems, and devices provide techniques for erasing data in a memory device. The memory device includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines forming a subset of word lines in the memory block. The memory device further includes a memory controller configured to perform: receiving an erase command for erasing data in the memory block; and in response to receiving the erase command, causing one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different periods such that when data erase begins at a first word line segment, data erase does not start at another word line segment.

The invention belongs to the technical field of data processing and analysis, and particularly relates to a geomagnetic and inertial navigation fused glasses guide direction identification and content triggering system, which comprises a sensing compensation component, a calculation storage component, a guide resource component and a display component, the sensing compensation assembly comprises an inertial measurement unit, a geomagnetic sensor, an active magnetic compensation coil and a coil driving module; the calculation storage assembly comprises a control processor and a memory, and the control processor is used for driving the active magnetic compensation coil to obtain a coil compensation geomagnetic vector according to a phase coding zero-returning sequence, executing attitude propagation based on the inertial measurement unit, and executing course updating on the coil compensation geomagnetic vector based on Huber anti-outlier loss to obtain a head attitude. According to the invention, the influence of magnetic disturbance and attitude jitter on direction identification and content triggering can be effectively reduced, and the stability, consistency and practicability of the glasses guide system in a real use scene are improved.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled with the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M target read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model. The peripheral circuit may be configured to determine a target valley voltage based on the predicted valley voltage. The target valley voltage may be configured as a read voltage for a read operation on the at least one code word.

The invention provides a data erasing method and a memory storage device, which can reduce the response time of a data erasing instruction so as to improve the performance of a host system. The memory storage device comprises a memory module and a memory control circuit unit. The data erasing method comprises the steps that in response to a data erasing instruction, multiple target mapping tables are determined according to a target logic address of the data erasing instruction, and the multiple target mapping tables comprise a first mapping table and a second mapping table; executing a data erasing operation on the first mapping table to erase mapping information corresponding to the target logic address in the first mapping table; performing data pre-erasing operation on the second mapping table to mark the second mapping table in the target index table; and sending a reply to indicate that the data erasing instruction is completed.

Examples disclose a memory system and operating method thereof and computer-readable storage medium. An example memory system includes a memory controller and a memory coupled to the memory controller. The memory includes multiple memory blocks, a memory block includes multiple physical pages. The memory controller is configured to: determine at least one source memory block from the multiple memory blocks; in response to the bitmap type associated with a first source memory block from the at least one source memory block being a first bitmap, write valid data stored in the first source memory block into the first target memory block from the multiple memory blocks; in response to the valid data being written into the first target memory block, erase the source memory block.

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.