2408 results about "Memory control" patented technology

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

A memory system and a method for decoding of one or more codewords. The system has a storage medium having therein a first decode, a first processor associated with the storage medium and configured to XOR results obtained from the first decoder when the one or more codewords in the storage medium are decoded, and a memory controller having therein a second decoder and a buffer, the memory controller configured to XOR results obtained from the second decoder. The second decoder decodes the one or more codewords after failure of the first decoder to decode the one or more codewords.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: acquiring original data from a host system; executing a plurality of randomization operations on the original data to obtain a plurality of write-in data; based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, executing randomization verification operation on each piece of write-in data to verify the data uniformity of each piece of write-in data in each direction so as to obtain target write-in data in the plurality of pieces of write-in data, wherein the randomized quality of the target write data is determined to be qualified; and storing the target write data to a plurality of target memory cells among the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

The invention discloses memory calibration with tolerance check. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to: perform a horizontal memory calibration for some of a plurality of performance states during an initialization process; and determining information indicative of a set of differences between calibration results for pairs of performance states of the plurality of performance states and storing the information in a storage circuit. The memory controller is further configured to, after the initialization process and in response to a change from a first performance state of the plurality of performance states to a second performance state of the plurality of performance states, set an initial memory parameter for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing the initial level calibration.

This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system that includes DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and send the precharge command to at least one DRAM bank of the particular DRAM group.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes memory control circuitry for controlling at least one memory die of a first memory type. A die-to-die (D2D) interface circuit couples to a host IC chiplet. The D2D interface circuit includes input / output (I / O) circuitry for coupling to multiple signaling lanes for transferring information packets with the host IC chiplet.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring block use conditions of a plurality of physical blocks of a rewritable nonvolatile memory module and a working state of storage equipment; when the working state is a busy state, whether garbage collection operation is executed or not is judged according to the block use condition and the host write-in requirement; and dynamically adjusting the write-in speed of the write-in operation of the host according to the number of the plurality of residual blocks when executing the garbage collection operation during the write-in operation of the host. According to the method, the use condition of the physical block and the write-in behavior of the host are monitored in real time, and a dynamic write-in speed adjusting mechanism is combined, so that the execution efficiency of garbage collection operation is obviously improved, and the write-in performance of the storage equipment under the high-load condition is effectively improved.

The embodiment of the invention provides a memory recovery method and device, equipment and a medium, the method is executed by computer equipment deployed with a container, and the container comprises a quality service agent component and a memory recovery agent component. The method comprises the following steps: determining a to-be-recycled memory node in a memory control group managed by a container through a quality service agent component, and transmitting the to-be-recycled memory node to a memory recycling agent component; obtaining a memory usage amount and a memory recovery index corresponding to the to-be-recovered memory node through the memory recovery agent component, and determining a memory recovery amount corresponding to the to-be-recovered memory node according to the memory usage amount and the memory recovery index; and calling a memory recovery interface through the memory recovery agent component, and recovering the physical memory in the memory node to be recovered based on the memory recovery amount. By implementing the embodiment of the invention, the memory resource utilization rate can be improved.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module, the memory module is provided with a plurality of chips, each chip is provided with a plurality of planes, and each plane is provided with a plurality of entity blocks. The method comprises the following steps: acquiring a chip enabling number of a memory module; selecting a target allocation method from a plurality of allocation methods according to the chip enabled number, the plurality of allocation methods including a first allocation method based on a plurality of chips and a second allocation method based on a plurality of planes; and dividing the plurality of entity blocks into a plurality of super blocks based on a target allocation method. Thus, the allocation strategy of the super blocks is optimized through the target allocation method, the utilization rate of the entity blocks in the memory module is improved, and meanwhile the garbage collection efficiency is improved.

The invention belongs to the technical field of artificial intelligence chip and robot control, and relates to a heterogeneous calculation and control fusion chip control system and method, a robot and a storage medium. A GPU, an NPU, a BPU and an MCU are integrated in a central large core cluster, a communication network subunit and a memory control subunit are matched, and a low-delay data channel is constructed in a chip, so that perception, cognition and control instructions can be directly interacted, the cross-chip communication delay is reduced, and the real-time performance is improved. The three-level cache module is accessed through the memory control subunit, high-bandwidth sharing and centralized scheduling are achieved, data migration is reduced, the bandwidth bottleneck is relieved, and the complex task processing efficiency is improved. A trust root subunit is arranged in each unit, chip-level trusted verification and access isolation are provided, and the reliability under key action control and security sensitive scenes is enhanced.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

The invention discloses an energy storage system and a data storage method, and relates to the technical field of energy storage. The energy storage system comprises a battery pack, a data collector, a memory and a controller. The data collector is connected with a plurality of batteries in the battery pack through a bus, the data collector is used for collecting operation data of the battery pack, the operation data comprises data streams of M dimensions, and M is a positive integer. The memory includes a volatile memory device and a non-volatile memory device, the volatile memory device including a cache and M first-in first-out buffers. The controller is electrically connected with the data acquisition unit and the memory, and is used for acquiring data streams of M dimensions, writing the data streams of M dimensions into the M first-in first-out buffers frame by frame, reading target data streams stored in the first-in first-out buffers to the cache when the data streams stored in the first-in first-out buffers meet storage conditions, and storing the target data streams in the memory. And writing the target data set stored in the cache into the nonvolatile memory device.

The invention relates to a heterogeneous trusted execution environment architecture construction method and device, and the method comprises the following steps: constructing a tensor analyzer which is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; and providing memory protection with uniform tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: firstly, obtaining original data from a host system; then, a plurality of randomization operations are performed on the original data to obtain a plurality of write-in data. Next, a first randomization verification operation is performed on each write data, by which target write data among the plurality of write data is acquired, where the randomization quality of the target write data is determined to be qualified. Finally, the target write data is stored in a plurality of target memory cells of the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The invention relates to the technical field of memory control, and particularly provides a memory allocation method and system, a terminal and a storage medium, and the method comprises the steps: configuring a memory pool based on a data processing flow and memory demand characteristics; obtaining a basic unit of each calculation unit for processing data each time, and configuring an address range and a current state for each memory block based on the determined size of the memory block in the memory pool; constructing a balanced binary search tree, and inserting all the memory blocks into nodes of the balanced binary search tree based on the sizes of the memory blocks; acquiring a memory allocation request, searching an optimal memory block in the balanced binary search tree based on the optimal adaptation strategy for memory allocation, and updating the current state of the optimal memory block to be occupied; and obtaining a memory release request, releasing the corresponding memory block back to the memory pool, and updating the current state of the released memory block to be idle. Accurate configuration, efficient utilization and flexible management of the memory are achieved, and scientificity and effectiveness of memory management are effectively improved.

A memory device may include a first main memory configured to store an address mapping table, at least one second main memory configured to store data received from a host device, and a memory controller configured to, compressively convert a host physical address set received from the host device into a device physical address set indicating a range of physical addresses in the at least one second main memory associated with the host physical address set, generate at least one address mapping table entry based on the device physical address set, the at least one address mapping table entry associated with at least one device physical address subset associated with the device physical address set, and store the at least one address mapping table entry in the address mapping table of the first main memory.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.