3544 results about "Memory control" patented technology

A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

A photoelectric conversion device includes: a plurality of pixels each including a sensor portion configured to emit a pulse corresponding to an incident photon, a counter configured to count the number of pulses, and a memory configured to store a count value of the counter; and a control unit configured to generate a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period and to output the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period.

Systems, methods, and apparatus related to memory devices that perform matrix vector multiplication using memory cells. In one approach, a memory cell array has memory cells used to perform matrix vector multiplication based on summing output currents from the memory cells. A context of memory cells is determined by a controller (e.g., a memory controller internal or external to a memory chip having the array). The context can include, for example, a physical location of memory cells, weight patterns being programmed, and / or neighboring cell interference, etc. Based on the determined context, the controller dynamically determines adjustments (e.g., adjusted target threshold voltages or currents) for programming the memory cells to store weights prior to performing the matrix vector multiplication.

A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and a redundancy control circuit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

A memory controller includes a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address according to an output control signal; a row-hammer detector configured to generate the output control signal by checking a row-hammer possibility based on the active command and the active address; and a memory interface configured to provide the active command and the active address issued by the scheduler to a memory device.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

A buffer chip includes a chip select signal reception circuit for receiving one or more system chip select signals transmitted from a memory controller and a chip ID reception circuit for receiving chip ID information transmitted from the memory controller. The buffer chip also includes a chip select signal generation circuit that generates memory chip select signals by using the one or more system chip select signals and the chip ID information and a chip select signal transmission circuit that transmits the memory chip select signals to a plurality of memory chips.

To provide a memory system and a memory device with high reliability.SOLUTION: A memory system of the embodiment includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to determine a first voltage based on information regarding a gradient of a distribution of threshold voltages of each of the plurality of memory cells, and to perform tracking operations. The memory controller causes the memory device to perform a plurality of read operations using a plurality of read levels for the plurality of memory cells in the tracking operation. The memory controller acquires the number of ON cells in each of the plurality of read operations. The memory controller sets a first potential difference of the plurality of read levels in a voltage range lower than the first voltage and a second potential difference of the plurality of read levels in a voltage range higher than the first voltage to be different from each other.SELECTED DRAWING: Figure 12

According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input / output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input / output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input / output module, and the memory controller.

A memory system and a method for decoding of one or more codewords. The system has a storage medium having therein a first decode, a first processor associated with the storage medium and configured to XOR results obtained from the first decoder when the one or more codewords in the storage medium are decoded, and a memory controller having therein a second decoder and a buffer, the memory controller configured to XOR results obtained from the second decoder. The second decoder decodes the one or more codewords after failure of the first decoder to decode the one or more codewords.

The invention provides a data writing method and a memory controller, which are suitable for a rewritable nonvolatile memory module with a plurality of memory units. The method comprises the following steps: acquiring original data from a host system; executing a plurality of randomization operations on the original data to obtain a plurality of write-in data; based on a plurality of directions of a three-dimensional circuit architecture of the rewritable nonvolatile memory module, executing randomization verification operation on each piece of write-in data to verify the data uniformity of each piece of write-in data in each direction so as to obtain target write-in data in the plurality of pieces of write-in data, wherein the randomized quality of the target write data is determined to be qualified; and storing the target write data to a plurality of target memory cells among the plurality of memory cells. Through multiple randomization operations and verification processes, the randomness and reliability of data storage are effectively improved, so that the overall performance and data security of a storage system are enhanced.

Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of pages in which data is stored, and a memory controller configured to provide, when a read request is externally received, address information including a physical address and a dummy address to the memory device. The memory device may perform a successive read operation of sequentially reading data from pages starting from a selected page corresponding to the physical address, among the plurality of pages, according to the dummy address.

The invention discloses memory calibration with tolerance check. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to: perform a horizontal memory calibration for some of a plurality of performance states during an initialization process; and determining information indicative of a set of differences between calibration results for pairs of performance states of the plurality of performance states and storing the information in a storage circuit. The memory controller is further configured to, after the initialization process and in response to a change from a first performance state of the plurality of performance states to a second performance state of the plurality of performance states, set an initial memory parameter for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing the initial level calibration.

This specification describes memory controllers with adaptive precharge scheduling. In one aspect, a memory controller includes a refresh scheduler configured to send refresh commands to dynamic random-access memory (DRAM) banks of a DRAM memory system that includes DRAM banks arranged in a set of DRAM bank groups each comprising one or more DRAM banks. The memory controller includes an adaptive precharge scheduler configured to determine a priority score for each DRAM bank group based on a set of parameters, select, based on the priority score for each DRAM bank group, a particular DRAM bank group to close so that each DRAM bank in the DRAM bank group can be refreshed by the refresh scheduler, and send the precharge command to at least one DRAM bank of the particular DRAM group.

The invention provides a memory management method and a memory controller, which are applied to a storage device configured with a memory module. The method comprises the following steps: acquiring a continuity state table, identifying a target mapping table according to a data access instruction and the continuity state table, acquiring a continuity state of the target mapping table, judging whether a continuous section mapping table is used or not according to the continuity state, and if so, loading the continuous section mapping table to a buffer memory, and if not, loading the target mapping table to the buffer memory, and obtaining the physical address according to the loaded mapping table to access the memory module. According to the method, the continuity of the entity address in the mapping table is evaluated, and the optimal mapping table processing mode is dynamically selected, so that the data access performance is effectively improved, and the use efficiency of the buffer memory is optimized.

Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

Scheduling processing-in-memory transactions in systems with multiple memory controllers is described. In accordance with the described techniques, an addressing system segments operations of a transaction into multiple microtransactions, where each microtransaction includes a subset of the transaction operations that are scheduled by a corresponding one of the multiple memory controllers. Each transaction, and its associated microtransactions, is assigned a transaction identifier based on a current counter value maintained at the multiple memory controllers, and the multiple memory controllers schedule execution of microtransactions based on associated transaction identifiers to ensure atomic execution of operations for a transaction without interruption by operations of a different transaction.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes memory control circuitry for controlling at least one memory die of a first memory type. A die-to-die (D2D) interface circuit couples to a host IC chiplet. The D2D interface circuit includes input / output (I / O) circuitry for coupling to multiple signaling lanes for transferring information packets with the host IC chiplet.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring block use conditions of a plurality of physical blocks of a rewritable nonvolatile memory module and a working state of storage equipment; when the working state is a busy state, whether garbage collection operation is executed or not is judged according to the block use condition and the host write-in requirement; and dynamically adjusting the write-in speed of the write-in operation of the host according to the number of the plurality of residual blocks when executing the garbage collection operation during the write-in operation of the host. According to the method, the use condition of the physical block and the write-in behavior of the host are monitored in real time, and a dynamic write-in speed adjusting mechanism is combined, so that the execution efficiency of garbage collection operation is obviously improved, and the write-in performance of the storage equipment under the high-load condition is effectively improved.

The embodiment of the invention provides a memory recovery method and device, equipment and a medium, the method is executed by computer equipment deployed with a container, and the container comprises a quality service agent component and a memory recovery agent component. The method comprises the following steps: determining a to-be-recycled memory node in a memory control group managed by a container through a quality service agent component, and transmitting the to-be-recycled memory node to a memory recycling agent component; obtaining a memory usage amount and a memory recovery index corresponding to the to-be-recovered memory node through the memory recovery agent component, and determining a memory recovery amount corresponding to the to-be-recovered memory node according to the memory usage amount and the memory recovery index; and calling a memory recovery interface through the memory recovery agent component, and recovering the physical memory in the memory node to be recovered based on the memory recovery amount. By implementing the embodiment of the invention, the memory resource utilization rate can be improved.

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

A device control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: obtaining device status information of the memory storage device, and the device status information includes at least one of temperature information and power consumption information; and adjusting a connection interface standard adopted by a connection interface unit of the memory storage device from a first connection interface standard to a second connection interface standard according to the device status information, and the first connection interface standard is different from the second connection interface standard.

The invention provides a memory management method and a memory controller. The method comprises the following steps: acquiring a plurality of virtual blocks of a memory module and corresponding error bit statistical information, evaluating the health condition of each virtual block, and selecting a target virtual block with a poorer health condition from the virtual blocks; and executing enhanced block mapping operation on the target virtual block, and mapping the entity blocks in the target virtual block into enhanced blocks in pairs. When the data is written, the data is written into the two entity blocks of the enhancement block in parallel; and during data reading, selecting one of the two entity blocks in turn according to a preset reading strategy for reading. Through dynamic enhancement block mapping and an alternate reading strategy, additional data protection is provided in the aging stage of the storage device, the service life of the device is prolonged, and meanwhile, dynamic balance between data security and storage capacity is achieved.

The invention provides a memory address generation method, a memory control method and a memory address generation device. The generation method comprises the following steps: obtaining a data memory address based on an address signal from a bus of the SOC system by utilizing a memory controller in the SOC system, and correspondingly storing data from the bus into a data memory unit according to an access sequence from the lowest bit to the highest bit of the data memory address; and based on the mode of the storage controller, obtaining the ECC memory address, and correspondingly storing the obtained ECC check codes into the ECC storage unit according to the access sequence from the highest bit to the lowest bit of the ECC memory address. Therefore, the problem of common cause failure of the address line can be avoided, and the function safety protection effect is improved.