1507 results about "Memory control" patented technology

The invention belongs to the field of memory control, and provides a mapping table management method and a storage device.The method comprises the steps that a write-in instruction from a host system is received; judging an access mode of the write-in instruction according to an access feature of a logic address corresponding to the write-in instruction; if the access mode of the write-in instruction is judged to be a continuous access mode, updating a mapping relation from a logic address to a physical address corresponding to the write-in instruction to a main mapping table; and if it is judged that the access mode of the write-in instruction is a random access mode, recording and managing a mapping relation from a logic address to a physical address corresponding to the write-in instruction through a temporary mapping table arranged in a buffer memory, and delaying updating of a main mapping table. Therefore, the random write-in performance of the storage device is improved, and the service life is prolonged.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

Secure communication provided with secure and non-secure root ports. One embodiment comprises: a plurality of cores; a memory controller to couple to a memory; an interconnect fabric coupled to the plurality of cores and the memory controller; and a root complex to support end-to-end encrypted channels between devices, the root complex comprising: a root port to receive non-posted requests from a requestor device, the root port to associate a first tag value with a non-posted request to indicate whether the non-posted request is received over an end-to-end encrypted channel; and a bridge device to transmit the non-posted request with the first tag value and to subsequently receive a completion message including the first tag value, wherein the root port is to determine whether the completion message is to be encrypted in accordance with the end-to-end encrypted channel based on the first tag value.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

A system includes a host device, a memory expanding device, and a switch connecting the host device and the memory expansion device, wherein the host device includes a cache controller including a prefetch support circuit configured to generate prefetch information, a root complex configured to transmit the prefetch information to the memory expanding device and receive prefetch data from the memory expanding device, and one or more prefetch buffers storing the prefetch data, and the memory expanding device includes a memory device and a memory controller including a prefetch decision circuit configured to read the prefetch data from the memory device based on the prefetch information received from the host device and prefetch the prefetch data to the host device.

The invention belongs to the technical field of artificial intelligence chip and robot control, and relates to a heterogeneous calculation and control fusion chip control system and method, a robot and a storage medium. A GPU, an NPU, a BPU and an MCU are integrated in a central large core cluster, a communication network subunit and a memory control subunit are matched, and a low-delay data channel is constructed in a chip, so that perception, cognition and control instructions can be directly interacted, the cross-chip communication delay is reduced, and the real-time performance is improved. The three-level cache module is accessed through the memory control subunit, high-bandwidth sharing and centralized scheduling are achieved, data migration is reduced, the bandwidth bottleneck is relieved, and the complex task processing efficiency is improved. A trust root subunit is arranged in each unit, chip-level trusted verification and access isolation are provided, and the reliability under key action control and security sensitive scenes is enhanced.

A memory apparatus includes a DFE receiver and a DFE reset circuit. The DFE receiver is configured to receive a data signal and a data strobe signal from a memory device. The DFE receiver includes a DFE tap that is determined according to a previous data signal, and the DFE receiver adjusts the data signal according to the DFE tap. The DFE reset circuit is configured to receive a gate enable signal and an internal enable signal from the memory controller, generate a DFE reset signal according to the gate enable signal and the internal enable signal. The DFE reset circuit outputs the DFE reset signal to the DFE receiver to reset the DFE tap of the DFE receiver between read bursts.

The application provides a data comparison method, a memory device, and a memory controller. A pre-seeding operation is performed on input data to pre-screen a plurality of candidate matching input data and a plurality of first mismatching input data. A group test is performed on the candidate matching input data to compare the candidate matching input data with a plurality of reference data to generate a matching result, thereby distinguishing a plurality of matching input data and a second mismatching input data from the candidate matching input data, wherein the matching result indicates information about the matching input data which matches the reference data, while the second mismatching input data does not match the reference data.

The invention provides a memory management method, a memory controller and an effective data positioning circuit unit. The method comprises the following steps: determining a plurality of candidate virtual blocks according to respective valid data count values of a plurality of virtual blocks; obtaining a mapping table bitmap corresponding to each candidate virtual block, determining a plurality of target virtual blocks based on the mapping table bitmaps, and generating a corresponding integrated mapping table bitmap; obtaining one or more sub-mapping tables according to the integrated mapping table bitmap; and generating an effective data table according to the physical address in the sub-mapping table and the physical address contained in the target virtual block. According to the method, the candidate objects for garbage collection are subjected to secondary screening in a hardware acceleration mode to determine the optimal target combination, and the mapping relation of the candidate objects is integrated to obtain the physical address of the corresponding effective data, so that the effective data table is made to improve the efficiency of garbage collection operation, and the reading burden of a storage device is reduced.

The invention belongs to the technical field of cache prefetching optimization of a firmware layer of a computer storage system, and particularly provides a memory control method, a storage device, a medium and equipment.The instantaneous flow is effectively filtered and persistent hotspot data is accurately recognized through a three-layer structure of combining a first-stage hotspot filtering module with a window cache, a view queue and a protection queue; the second-stage continuous access filtering module dynamically judges a continuous access mode by means of mean-variance statistics of an annular buffer area, and accidental continuous triggering of prefetching is avoided; and the third-stage random access judgment module prohibits invalid prefetching and effectively distinguishes access modes. The pre-fetching bandwidth is limited through the token bucket algorithm, the global priority queue of the skip list is combined, it is ensured that the priority of the write task is higher than that of the pre-fetching task, pre-fetching and foreground I / O resources are isolated, delay jitter control over foreground key I / O can be achieved during full-load pre-fetching, and the problem that delay soaring is caused when pre-fetching preempts the resources is solved.

The invention belongs to the technical field of data processing and analysis, and particularly relates to a geomagnetic and inertial navigation fused glasses guide direction identification and content triggering system, which comprises a sensing compensation component, a calculation storage component, a guide resource component and a display component, the sensing compensation assembly comprises an inertial measurement unit, a geomagnetic sensor, an active magnetic compensation coil and a coil driving module; the calculation storage assembly comprises a control processor and a memory, and the control processor is used for driving the active magnetic compensation coil to obtain a coil compensation geomagnetic vector according to a phase coding zero-returning sequence, executing attitude propagation based on the inertial measurement unit, and executing course updating on the coil compensation geomagnetic vector based on Huber anti-outlier loss to obtain a head attitude. According to the invention, the influence of magnetic disturbance and attitude jitter on direction identification and content triggering can be effectively reduced, and the stability, consistency and practicability of the glasses guide system in a real use scene are improved.

According to one aspect of the present disclosure, a memory device is provided. The memory device may include a memory cell array including a plurality of memory cells. A preset number of the memory cells may form a code word. The memory device may include a peripheral circuit coupled with the memory cell array. The peripheral circuit may be configured to obtain M first results corresponding to at least one code word at M target read voltages. The peripheral circuit may be configured to obtain a predicted valley voltage according to the M first results and the M target read voltages in conjunction with a preset function model. The peripheral circuit may be configured to determine a target valley voltage based on the predicted valley voltage. The target valley voltage may be configured as a read voltage for a read operation on the at least one code word.

A 3D semiconductor device including: a first level including a first single crystal layer and a memory control circuit including first transistors and control circuit connectivity provided by first, second, and third metal layers; a second level including second transistors (one which includes a metal gate) disposed atop the first level; third transistors disposed atop second transistors with a fourth metal layer disposed atop; a memory array including word-lines, the memory array includes at least four memory mini arrays, where each mini array includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second or third transistors; a connection path from the fourth metal to the third or second metal layer, which includes a via disposed through the second level, and where the memory control circuit includes at least one power down control circuit.

The invention relates to the technical field of data processing, in particular to a cloud platform data analyzing and processing system based on front-end segmentation, which comprises the steps of synchronously displaying fields and paging information to construct export parameters, cloning rendering data to establish a running state, monitoring page turning change to generate buffer content, and segmenting and packaging buffer data according to a memory state. And pushing the data to the local, rolling back the page structure, and completing the export of the process ending identifier. According to the method, export parameters are constructed by synchronously searching fields, header structures and paging numbers; a data clone structure is established in combination with field mapping and paging tracks; field changes are monitored to generate buffer contents; paging data are split according to memory occupation and packaged into local caches; and pushing data to the local and rolling back a display structure to support key links of export processes such as field tracking, memory control, data merging and page recovery.

An embodiment of an IC is provided. The IC includes a memory, a controller, an intrusion detector and a memory clear circuit. The memory is configured to store sensitive data. The controller is configured to access the memory. The intrusion detector is configured to detect whether an intrusion event is present in response to an input signal. The memory clear circuit is configured to clear the sensitive data of the memory when the intrusion detector detects the intrusion event.

A memory controller is coupled via at least one data path to plural memory regions for distributing and storing plural data entries. The memory controller includes parity generating circuitry configured to: perform logical operations on the plural data entries, based on an order in which the plural data entries are transmitted to the plural memory regions, to generate a parity entry; and add location information of the plural data entries, stored in the plural memory regions, into the parity entry.

In some implementations, a memory system may receive multiple memory requests associated with a memory, wherein the memory is associated with multiple memory ranks, and wherein each memory request, of the multiple memory requests, includes a memory address indicating a memory rank, of the multiple memory ranks, that is to be accessed for that memory request. The memory system may group the multiple memory requests based on the multiple memory ranks. The memory system may transmit, to a memory controller associated with the memory, a scheduled set of memory requests, wherein the scheduled set of memory requests includes memory requests selected from one or more groups of memory requests associated with one or more scheduled memory ranks of the multiple memory ranks.

The invention provides a memory management method and a memory controller. The memory management method is applied to the storage device provided with a memory module and a buffer memory. The method comprises the steps of determining a necessary function and a high-frequency call function as a first type function by analyzing a call relationship of functions in a firmware program, and pre-loading the first type function into a resident storage area of a buffer memory; dividing the rest of the second type functions into a plurality of storage libraries according to the function calling relationship, and storing the rest of the second type functions in a storage module; and when the specific function needs to be executed, dynamically loading the storage library containing the target function into the dynamic storage area of the buffer memory. According to the method, through weight calculation and an intelligent allocation strategy, the number of times of switching of a storage library (Bank) can be reduced, so that the resource utilization rate of a memory is improved, the overall performance of a system is improved, automatic management of firmware codes is achieved, and the complexity and error risk of manual adjustment are reduced.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

A 3D semiconductor device including: a first level including a single crystal layer, a memory control circuit, a first metal layer, a second metal layer, and a third metal layer; connection of the first transistors comprises the first, and / or the second, and / or the third metal layer; a fourth metal layer disposed atop third transistors disposed atop second transistors disposed atop said first level; a memory array including word-lines and at least four memory mini arrays which include at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors (at least one with a metal gate) or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array; the memory control circuit includes first transistors and voltage regulators.

A method of forming a semiconductor includes bonding a first memory die to a first memory-controller die to form a first bonded assembly, bonding second memory die to a second memory-controller die to form a second bonded assembly, and bonding the first bonded assembly to the second bonded assembly to form a memory stack.

A memory controller configured to write, read, and erase data for a nonvolatile memory device storing first meta data and first journal data indicating first changes of the first meta data, the memory controller comprising: a buffer memory circuit including a buffer memory and a buffer controller, wherein the buffer memory stores second meta data and second journal data indicating second changes of the second meta data, and wherein the buffer controller controls the buffer memory; and an accelerator managing the first meta data, the second meta data, the first journal data, and the second journal data, wherein the buffer controller includes: a first error correction code (a first ECC) engine configured to correct a first error of first data that includes the second meta data; and a second error correction code (a second ECC) engine configured to correct a second error of second data including the second journal data.

A method of operating a non-volatile memory (NVM) device includes: reading, by a memory controller of the NVM device, first metadata bits and first redundant bits stored in an erase sector of a memory cell array of the NVM device, where the first redundant bits are generated using an error-correction code (ECC) for protection of the first metadata bits; and performing an ECC decoding process for the first metadata bits, which includes: forming a first data frame by filling the first data frame with the first metadata bits, a first number of dummy bits, and the first redundant bits; computing, by the memory controller, a syndrome vector for the first data frame in accordance with the error-correction code; and in response to determining that the syndrome vector comprises a non-zero element, performing, by the memory controller, error correction for the first data frame to obtain decoded first metadata bits.

A memory controller includes a first storage circuit which stores trained center eyes for a dual data rate (DDR) interface, each trained center eye including a corresponding trained delay value, and a second storage circuit which stores boundary points for the DDR interface. The memory controller includes test circuitry which halts normal operation and uses a corresponding trained delay value of a trained center eye for a first bit lane of the DDR interface as a starting delay value in performing a search for a first boundary point of a data eye margin by repeatedly adjusting a delay between a data signal (DQS) of the first bit lane and a corresponding data strobe signal (DQS) and performing a test with each adjusted delay. The test circuity stores the first boundary point in the second storage circuit, restores the delay back to the corresponding trained delay value, and resumes normal operation.

The invention discloses an AIGC-based self-media video generation method, and relates to the technical field of video generation, and a system adopted by the method comprises a sequence semantic arrangement module, a cross-segment stitching module, a global memory anchor point module and a self-adaptive memory control module. The sequence semantic arrangement module is used for fusing text semantics, action intensity and music beats to determine a tangency point and an overlapping window and arranging a segment-level generation process, and the cross-segment stitching module is used for performing fade-out and fade-in by using a Hanning window in a submerged space and performing cross gradual change by combining motion compensation to realize seamless connection and picture continuity between segments. The global memory anchor point module is used for maintaining anchor point embedding and periodic snapshot of a main body and a style, performing parity check and providing a returnable global consistency reference, and the adaptive memory control module is used for gating TTT based on a deviation value and performing hierarchical updating according to a low-frequency style and a high-frequency detail, the deviation is large and stable in style, and the adaptive memory control module is used for controlling the TTT according to the deviation value. The method has the characteristic of natural connection.

A memory management method and a memory controller for executing virtual block mapping operations. The method performs initial virtual block mapping across multiple physical channels, then dynamically divides the channels into two groups when free blocks in a target channel fall below a threshold. By remapping blocks separately for each group, the method enables simultaneous garbage collection and host write operations across different channel groups, so as to improve operational efficiency of the storage device.

An apparatus includes memory control circuitry to control access to at least one array of memory storage cells and to schedule received memory access requests targeting locations in the at least one array of memory storage cells. The apparatus also includes utilisation status determining circuitry to determine a utilisation status associated with accessing the array of memory storage cells, in which the utilisation status is indicative of a utilisation of a group of memory storage cells in the at least one array of memory storage cells. The apparatus includes feedback signalling circuitry to signal to a source of the received memory access requests feedback indicative of the determined utilisation status.

Example systems and methods for data migration in memory systems are disclosed. One example method includes receiving, by a memory controller of a memory system, a command comprising a first logical address and a second logical address. In response to the command, a correspondence of data to the second logical address is established based on a correspondence of the data to the first logical address. The first logical address is deallocated based on the command.

A semiconductor system may include a command address bus, a data bus, a management bus, a memory module including multiple memories and coupled to the command address bus, data bus and management bus, a memory controller configured to control, through the command address bus and the data bus, the memory module to perform a write operation and a read operation and a baseboard management controller configured to perform, through the management bus, a management operation of managing the multiple memories.

The invention relates to the technical field of storage control, in particular to a memory control method, a storage device, a medium and computer equipment, a three-level index structure is arranged, only a first-level root table resides in a cache, an index is rapidly extracted through bit operation so as to reduce cache occupation and invalid IO overhead, the search range is narrowed through a hash bucket of a three-level page table, and the search efficiency is improved. Conflicts are solved through a linked list, and the mapping efficiency and the system stability can be improved through a fixed structure; and the second-level block table and the third-level page table are loaded in a non-blocking manner without occupying a CPU, so that the bandwidth is saved, and the concurrency performance and the cache hit rate are improved. Through the overall scheme of three-level index, chained hash table, loading on demand and bit operation, the delay of the whole process from logic address input to physical address output is remarkably reduced, and the low delay requirement of a high-performance storage system is met; the three-level index structure supports flexible adjustment of the sizes of a root table, a block table and a page table, adapts to storage devices with different capacities, and has good expandability.