182 results about "Memory management" patented technology

The embodiment of the application discloses a memory retrieval method, a memory management method and a computer device. The method is used for the computer device, the computer device and a distributed cache, the computer device comprises a persistent storage, and the distributed cache and the persistent storage both store candidate memories. The method comprises the following steps: obtaining a retrieval request of a target user from a target terminal, extracting target query information from the retrieval request; if a target memory matched with the target query information is not obtained from the distributed cache, obtaining the target memory from the persistent storage, and sending a target retrieval result to the target terminal based on the target memory. The technical scheme can improve the interaction efficiency between the intelligent agent and the user by using the hierarchical storage memory.

The application relates to the technical field of memory detection, in particular to a memory usage tracking method and a storage medium. The method constructs a target memory block containing a header space and a data space through obtaining a memory allocation request, records memory management information in the header space, and hangs the target memory block to a ring-shaped bidirectional linked list; in a memory access process, the validity of the target memory block is checked and access time information is updated, and safe release is performed according to the memory management information when releasing; through periodic traversal of the ring-shaped bidirectional linked list, in combination with the time information and the reference state of the target memory block, a memory usage tracking result is generated, and continuous monitoring and abnormal occupation analysis of the memory life cycle are realized. The application realizes traceability, checkability and analysis of the memory usage state, thereby effectively improving the safety, reliability and problem positioning efficiency of memory management.

The present application provides a memory management method, a storage device and a host system. The method comprises: configuring a first physical area in a memory module; obtaining an operation instruction from a host system; if the operation instruction is a first type of operation instruction, performing a first access operation on a first physical unit in the first physical area according to the operation instruction without performing a logical-to-physical conversion; and if the operation instruction is a second type of operation instruction, performing the logical-to-physical conversion to determine a second physical unit, and performing a second access operation on the second physical unit according to the operation instruction, wherein the second physical unit is not located in the first physical area. Thus, the performance of the storage device when used in an artificial intelligence model running in cooperation with the host system can be improved.

The present application provides a memory management method and a storage device. The method comprises: based on an operation event, obtaining a selection strategy corresponding to the operation event through a performance mapping table; determining a target virtual block combination from a plurality of candidate virtual block combinations according to the selection strategy; and responding to the operation event using the target virtual block combination. Thus, the performance and / or operation stability of the storage device can be effectively improved.

The application discloses a video target recognition method based on multi-model hot switching, and belongs to the technical field of computer vision and video processing. The method comprises an arbitration module, a switching control module and a feature adaptation and buffer module. The arbitration module generates a switching preparation signal by extracting multi-dimensional indexes such as optical flow mean, local variance, target density and scene confidence in real time through a lightweight channel independent of main reasoning. The switching control module performs atomic replacement of a computation graph pointer in a vertical blanking period, and realizes millisecond-level hot switching with zero frame loss by combining an asynchronous pre-copy and a chasing mechanism of a double buffer. The feature adaptation and buffer module solves tensor shape mismatch between heterogeneous models through a pre-compiled adaptation layer. The application also provides optimization schemes such as multi-index nonlinear fusion decision, zero-copy memory management, local slice focus reasoning and edge-cloud hierarchical unloading, significantly reduces switching delay, guarantees continuous recognition of a video stream, and is suitable for edge computing scenes with limited resources.

This application provides a memory management apparatus and method for an intelligent processor. The memory management apparatus includes a prefetch circuit, a setting circuit, and a mapping circuit. The prefetch circuit obtains raw data via a direct memory access circuit. The raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. The setting circuit parses the raw data to sequentially map each of the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between each physical address and the corresponding second virtual address as a first mapping table according to the write request, and accesses the memory using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

This application provides a method and apparatus for extracting and securely storing conversational memories for AI companions. It achieves effective memory filtering through sentiment annotation and importance assessment. A storage mechanism is constructed, combining semantic association and secure encryption to establish a reliable memory management strategy. Retrieval optimization is introduced, ensuring efficient memory retrieval through parallel querying and feedback mechanisms. This method effectively addresses the shortcomings of traditional technologies in memory extraction, secure storage, and retrieval optimization, providing technical support for AI companions.

The present application relates to the technical field of memory management, and discloses a memory management method for a multi-core system, a multi-core system, a device, and a medium. The method comprises: a master core unit marking initial memory management priorities of the master core unit and slave core units as a second level, the memory management priorities further comprising: a first level higher than the second level and a third level lower than the second level; determining a system operating condition; on the basis of the system operating condition and the second level, updating and determining current memory management priorities of the master core unit and the slave core units; and on the basis of a memory scheduling and allocation request sent by an applicant, the system operating condition, the type of the applicant, and a current memory management priority of the applicant, a memory manager performing memory scheduling and allocation processing, and allocating an idle memory unit to the applicant, so that the applicant executes a task in a task queue, the applicant being the master core unit or one of the slave core units. The present application can improve system memory utilization rate and ensure efficient and correct operation of the multi-core system.

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

This invention discloses a high-speed read / write management system and method suitable for DDR5 memory, relating to the field of memory management technology. It solves the problem of ineffective high-speed read / write of data in DDR5 memory, and includes a region partitioning module, a state analysis module, a space analysis module, a read analysis module, and an execution module. The region partitioning module is used to partition the storage regions in the DDR5 memory; the state analysis module is used to analyze the storage status of different storage groups; the space analysis module is used to analyze the storage groups in the DDR5 memory; the read analysis module is used to analyze read operations in the DDR5 memory; and the execution module is used to write the write file to the target write line of the DDR5 memory. This invention achieves effective high-speed read / write of data in DDR5 memory.

The application belongs to the technical field of computer memory management, and discloses an active page replacement method and system based on regional reuse mode identification, which comprises the following steps: working set identification based on memory access sample clustering, obtaining memory access samples by sampling the memory access instructions of a process, and clustering the samples to obtain the working set in the current monitoring window in real time; adaptive memory region division based on working set integration, dividing the address space into regions according to virtual address continuity and adaptively splitting / merging; reuse mode identification based on state transition, determining the reuse mode of each region according to the switching between hot and cold states of each region and the state duration; active page replacement and prefetching method based on the reuse mode, prefeteching the regions that will reach the reuse time, and triggering the replacement of the regions that are in the cooling state for a long time. Compared with the existing passive page fault triggering method, the application can reduce the page fault and jitter, reduce the replacement traffic, and improve the application execution efficiency and system throughput.

The present application relates to an artificial intelligence chip, a method for virtual address conversion, a computing device, a computer readable storage medium and a computer program product. The artificial intelligence chip comprises: an address cache bank arranged before a memory management unit and comprising a plurality of address caches, the address cache bank being configured to perform hit and miss detection on virtual addresses associated with read / write requests from a plurality of computing units to obtain corresponding physical addresses; the memory management unit being configured to query virtual addresses missed by the address cache bank and provide the queried corresponding physical addresses to the address cache bank; and the plurality of computing units being configured to perform calculations and provide read / write requests to the address cache bank. The present application can significantly reduce arbitration conflicts between multiple requests and improve the conversion efficiency of virtual addresses to physical addresses and the performance of the chip.

An apparatus (2) has memory management circuitry (16, 20) for controlling access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control tables. Table access circuitry (17), (23) accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a start level, the table access circuitry (17, 23) selects a selected table entry of the given access control table corresponding to the target address based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter (190) specified in a table entry of a higher level access control table at a higher level of the table structure than the given access control table.

This invention belongs to the field of artificial intelligence communication technology and discloses an AI autonomous intelligent agent execution framework architecture system based on layered decoupling. The invention integrates the core capabilities of ReAct execution loop, intelligent context compression, and autonomous error correction in the decision layer to achieve accurate parsing of instruction intent, dynamic iteration of decision logic, and autonomous error correction. The transmission layer establishes a multi-platform message intelligent routing and protocol unification mechanism to achieve efficient data interaction and instruction transmission across platforms and protocols. The execution layer integrates hybrid memory management and sandbox-isolated practical execution capabilities to achieve multi-dimensional memory of execution data, secure isolation of execution behavior, and accurate implementation of practical tasks. The system's layers are clearly defined, decoupled, independent, and collaborative, possessing high scalability, cross-platform adaptability, execution security, and decision autonomy.

The present application provides a memory management method and a storage device. The method comprises: obtaining temperature information of the storage device; obtaining write buffer quota information according to a difference between the temperature information and target temperature information; and adjusting a write buffer capacity of the storage device according to the write buffer quota information. Thus, a good balance between performance maintenance and temperature regulation of the storage device can be achieved.

This invention discloses a GPU memory virtualization method and apparatus based on deep parsing of the ioctl protocol, belonging to the field of electronic information technology. The method includes: intercepting ioctl system call requests initiated by the target container to obtain ioctl system call requests for GPU memory management; parsing its parameter blocks and extracting memory-related instructions to obtain memory-related instructions for subsequent auditing; constructing a shadow object tree and intelligently auditing memory allocation and mapping operations to obtain a precise memory usage ledger; determining whether the quota has been exceeded and executing interception during the physical admission control phase to obtain a control result on whether instruction pass-through is allowed; implementing view virtualization and returning virtualized memory information to the application in the target container to achieve transparent application adaptation, thereby completing precise virtualization isolation and multi-tenant secure sharing of GPU memory. This invention combines kernel-level control strength with user-space deployment flexibility.

This application relates to a context memory management method and system for adaptive multi-turn dialogue interaction. The method includes: querying a vector database for several historical intent vectors with the highest semantic similarity to the intent vector of the current user input, and returning a candidate vector ID list composed of candidate vector IDs of each historical intent vector; obtaining the context ID corresponding to each candidate vector ID in the candidate vector ID list, and obtaining the context record corresponding to the candidate vector ID based on the context ID; calculating the time decay factor of each context record based on the timestamp; calculating the weight of each context record based on the semantic similarity and time decay factor corresponding to the context record; determining whether the highest weight exceeds a set threshold, if so, using the user input as a continuation of the corresponding context record and updating the corresponding context record; otherwise, using the user input as a new context record and saving the new context record.

This application provides a method, system, device, and medium for virtual terminal resource preloading and caching management based on the ISOBUS standard. This application innovatively constructs a multi-level caching architecture and combines a Markov chain-based resource prediction engine with adaptive memory management technology to achieve intelligent preloading and efficient caching of interface resources. Addressing the pain points of existing ISOBUS VT systems, such as high resource loading latency, low cache hit rate, and insufficient memory utilization, this invention provides a targeted technical solution. Experimental data verifies that this technical solution can reduce resource loading time by 50% to 70%, increase cache hit rate to over 92%, improve memory utilization by 40%, and reduce system crash rate by over 80%.

This invention relates to the field of Internet Protocol (IP) technology and discloses a method and storage medium for storing overlapping IP segment types based on LPM (Limited Memory Management). The method involves loading IP segment and VALUE information into an IPVALUE array; constructing an IP scale based on the IPVALUE array; traversing the IPValue array and measuring according to the IP scale array to obtain the IP segment fragment; querying the LPM unit based on the IP segment fragment; if a corresponding fragment IP is found, using the return value of the LPM unit as the VALUE set for that IP segment fragment; if no corresponding fragment IP is found, creating a Value set to store the fragment's Value information, and then storing the address of the fragment IP and the address of the Value set in the LPM unit; querying a specified IP based on the LPM unit, returning null if not found, and returning the address of the set array if found. This method effectively supports the storage and querying of multiple overlapping IP segment information while maintaining low memory usage and high query efficiency.

This disclosure provides a memory management method and mobile terminal based on a memory spatiotemporal network, relating to the field of computer technology. The method includes: acquiring interaction data during the interaction between an agent and a user, and generating corresponding memory nodes based on each round of interaction data; obtaining the semantic and spatiotemporal correlation degrees between multiple memory nodes based on their semantic features and spatiotemporal information, thereby determining the memory correlation degree between each memory node; establishing temporal connections between memory nodes whose correlation degrees satisfy the correlation conditions to form memory association links, the set of links forming a memory spatiotemporal network; responding to the user's current interaction request, determining a target memory node matching the current interaction request or a target memory association link containing the target memory node in the memory spatiotemporal network, and forming response information accordingly. This disclosure improves the accuracy of the agent's invocation of memory nodes, thereby optimizing the response information generated by the agent.

The application provides an agent memory management method and device based on a decoder memory component, wherein the method comprises: acquiring user input data; inputting the user input data into a pre-constructed large language model to generate a user response; asynchronously monitoring the user response to extract multi-source information of user feedback; generating a training queue according to the multi-source information; and performing knowledge solidification after incremental training of the training queue to realize agent memory management. By introducing an auxiliary small model, the long-term memory is separated from the context window of the large language model, flexible management and persistent storage of long-term memory are realized, new knowledge can be efficiently captured, and the loss of time sequence structure information is avoided.

The application discloses a radio data processing method, device and equipment and a storage medium. The method comprises the following steps: acquiring a radio data set to be processed; wherein the radio data set to be processed has corresponding generation time information, the radio data set to be processed comprises radio data to be processed of a to-be-processed task, and the to-be-processed task comprises a plurality of subtasks executed in a preset order; determining a target memory matched with the radio data set to be processed according to the generation time information, a total number of memories and a pre-established memory management table, and storing the radio data set to be processed in the target memory; calling a processing thread corresponding to each subtask in the plurality of subtasks in the target memory according to the preset order, and processing the radio data to be processed by using the processing thread. The technical scheme of the application improves the calculation speed of radio data.

The application discloses a PE virus detection method, comprising the following steps: determining target resources required by a PE file during runtime; wherein the target resources comprise a CPU, a memory management module and a runtime library; virtually executing the PE file by simulating the target resources, and recording characteristic information generated by the PE file during the virtual execution; and judging whether the PE file is a virus file according to the characteristic information. The application can reduce resource consumption of PE virus detection. The application also discloses a PE virus detection device, a storage medium and an electronic device, which have the above beneficial effects.

The present disclosure provides a memory management method and a memory controller. The method is suitable for a storage device configured with a memory controller and a memory module, comprising: monitoring the number of read operations on a logical address through a first read counting operation to screen out a hot spot logical address, and tracking the read counting of the hot spot logical address through a second read counting operation to determine a first target block; performing a scanning operation on the first target block to obtain the error rate of each word line in the first target block, and marking the word line with an error rate exceeding a preset threshold as a target word line; and copying valid data in the target word line to a second target block. The present disclosure locates the physical block where the hot spot data is located through hierarchical read counting monitoring, and realizes local data migration through word line level error rate evaluation, which reduces unnecessary data migration amount compared with the full block refresh scheme, and reduces the impact on the host command response.

This invention provides a method and computing system capable of enhancing memory protection related to the operating system kernel, thereby ensuring system security. The computing system provided by this invention may include: a processor configured to execute a guest virtual machine (VM), wherein an operating system (OS) runs on the guest VM, and an application (APP) runs on the OS. The kernel of the OS includes: a protection service module configured to receive at least one virtual address and first size information sent by a client of the APP; and a memory management unit (MMU) manager. The computing system further includes a virtual machine manager configured to receive the at least one virtual address and the first size information sent by the protection service module. The computing system also includes a host VM, which includes: a protection manager configured to receive and obtain a physical address array and second size information based on the at least one virtual address and the first size information to protect memory allocated by the kernel of the OS.

This application discloses a method and apparatus for writing buffer data in a memory management unit, relating to the field of chip verification technology, and is invented to shorten verification time and improve verification efficiency. The method includes: traversing a page table to obtain the mapping relationship between virtual addresses and physical addresses recorded in the page table; filtering the mapping relationship according to a predetermined strategy to obtain a target mapping relationship; converting the target mapping relationship into a predetermined format to obtain a target mapping relationship; and writing the predetermined format target mapping relationship into a substitution bypass buffer in the memory management unit through a backdoor access function. This application is applicable to verification related to substitution bypass buffers.

The present disclosure provides an artificial intelligence training method and device based on selective memory reinforcement and a medium, relating to the technical field of artificial intelligence. The method comprises: acquiring multi-modal interaction data of an interaction object; encoding the multi-modal interaction data to generate corresponding interaction feature vectors, and calculating an emotional energy value and a valence of a current interaction event; calculating an importance score of the current interaction event based on the interaction feature vectors, the emotional energy value and the valence, and performing selective memory storage according to the importance score to generate structured memory data; generating multi-modal feedback instructions based on the interaction feature vectors, the structured memory data and a predefined personality vector; executing the multi-modal feedback instructions, and updating the personality vector based on response data of the interaction object to the execution result of the feedback instructions. The present disclosure can realize efficient memory management according to the importance score, and the real-time updated personality vector enables the AI to form an interaction style adapted to the user.

A method of preloading address translation information directly into cache memory of an IOMMU includes storing the address translation information in a register set of memory management input / output registers of an input-output memory management unit and loading the address translation information into cache memory of the input-output memory management unit. The address translation information includes a virtual address and a corresponding physical address of system memory of a computing system. The address translation information is sent by software being executed by a processor of the computing system. The address translation information is received directly from the processor.

Embodiments of the present application provide a memory management method and device, and relate to the technical field of computers. The method comprises: receiving a continuous memory allocation request sent by a first CPU core, the continuous memory allocation request comprising a first number of pages; querying a bitmap of a continuous memory allocation area to obtain a first number of page frame numbers, the first number of page frame numbers corresponding to free memory pages with consecutive physical addresses, and the value of each bit in the bitmap indicating whether the corresponding memory page in the continuous memory allocation area is free or used; from a clean cache pool, reclaiming the memory pages corresponding to the first number of page frame numbers; allocating the reclaimed memory pages to the first CPU core and setting the value of the bit corresponding to the reclaimed memory pages in the bitmap to a value indicating that the memory pages are used. The scheme can reduce memory allocation delay, improve the control accuracy of memory allocation operations, and enhance memory security.