514 results about "Host interface" patented technology

Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.

Apparatuses, systems, and techniques for classifying one or more computer programs executed by a host device as being ransomware using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service to protect one or more computer programs executed by the host device. The security service obtains a series of snapshots of data stored in the physical memory and extracts a set of features from each snapshot of the series of snapshots, each snapshot representing the data at a point in time. The security service classifies a process of the one or more computer programs as ransomware or non-ransomware using the set of features and outputs an indication of ransomware responsive to the process being classified as ransomware.

The invention discloses a multichannel extended hard disk automatic test device and method. The multichannel extended hard disk automatic test device comprises a control server, a network switch, a test host and a test device, the control server is connected with at least one test host through a network switch, each test host is connected with a test device through a programmable power strip, and the test devices are connected with multiple paths of hard disk equipment; the control server can generate test parameters and issue the test parameters to the test host with the network wakeup function, and the test host can automatically call corresponding test scripts according to the received test parameters, execute test tasks on the hard disk, record the test process and result and upload the test process and result to the control server; the test device can realize automatic switching of a plurality of hard disks of the same test host interface according to the test parameters; and meanwhile, the power supply of the test host is controlled through the programmable power strip so as to generate abnormal power failure test excitation. According to the invention, a single test host can automatically and orderly test a plurality of hard disks in batches.

The invention discloses a shared cache system applied to a real-time network terminal chip. The shared cache system comprises queue management, enqueue scheduling control, dequeue scheduling control, write bus control, read bus control, a data cache, a register module, an RXFIFO module and a TXFIFO module. According to the cache allocation strategy, the variable-length data is stored by using the fixed-length unit. The user can customize and configure the private space, the residual space is the shared space, and the storage utilization rate is high. The shared cache is mainly used for storing data packets sent by an external application layer through a host interface. And storing the received data packet, extracting frame information according to a network flow protocol, and directly discarding frames which do not meet the protocol. The shared cache is provided with a dynamic cache structure, the state of each queue can be updated in real time, frame loss is prevented, and the data stream processing capacity is improved. And meanwhile, complex hybrid scheduling of a real-time network is met. The whole shared cache is subjected to anti-radiation reinforcement, the scene requirement of space navigation application is met, and high reliability is achieved.

Technologies for configuring multiple virtual bridges and interface mappings in a Service Function Chaining (SFC) architecture are described. A DPU can include memory to store a configuration file specifying the virtual bridges and interface mappings, and a processing device operatively coupled to the memory. The processing device, according to the configuration file, generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU, and the second virtual bridge is controlled by a user-defined logic. The processing device adds add one or more host interfaces to the second virtual bridge, a first service interface to the first virtual bridge to operatively couple to the first network service, and one or more virtual ports between the first virtual bridge and the second virtual bridge.

An integrated circuit includes a host interface coupled to a host device executing a tenant operating system (OS) on bare metal and hardware accelerator(s) coupled to the host interface and a network interface. The hardware accelerator(s) receive, over the host interface, a snapshot request relating to a snapshot of tenant OS. Snapshot request includes a location, in a physical memory of the host device, of a swap file having contents of random access memory of the host device. The hardware accelerator(s) encrypt the swap file and initiate transfer of the encrypted swap file to a network storage device coupled to a cloud-based server. The hardware accelerator(s) send, over the network interface, to a snapshot manager hosted by the cloud-based server, metadata associated with storing the encrypted swap file in the cloud-based server, to allow the snapshot manager to manage the snapshot of the tenant OS.

Apparatuses, systems, and techniques for classifying a candidate uniform resource locator (URL) as a malicious URL using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service that obtains a snapshot of data stored in the physical memory and extracts a set of features from the snapshot. The security service classifies the candidate URL as a malicious URL using the set of features and outputs an indication of the malicious URL.

The invention relates to the technical field of host extension, and discloses a host extension method, device and equipment based on an RS485 bus and a storage medium, and the method comprises the steps: carrying out the parameter configuration of an RS485 bus host interface, and obtaining an independently configured RS485 host interface group; constructing a five-level data stack structure for the RS485 host interface group to obtain a host data frame management unit; host interaction task processing is carried out on the host data frame management unit, and host data frames are stored in corresponding data frame cache regions; performing scheduling task processing on the host data frame in the host data frame management unit to obtain a data forwarding result; performing task scheduling time sequence processing based on the data forwarding result to obtain a task scheduling sequence; and the task scheduling sequence is input into the man-machine interaction task module for state monitoring to obtain a system operation state record, so that a plurality of host devices can monitor and control the slave devices at the same time, and the accuracy and reliability of data transmission are improved.

The embodiment of the invention provides a main control chip, a data processing method, a solid state disk and a computer system, and the main control chip comprises a flash memory host interface controller which comprises a distribution address obtaining module and a command execution module; the allocation address acquisition module is used for acquiring a first cache address and a second cache address correspondingly allocated for the data write command, the first cache address is a cache space address located inside the main control chip, and the second cache address is a cache space address located outside the main control chip; the command execution module is used for writing the write data into the first cache address and the second cache address; and the main control chip performs programming operation based on the write data in the first cache address, and releases the write data in the second cache address after the main control chip performs data consistency confirmation on the write data in the first cache address. According to the technical scheme provided by the embodiment of the invention, the overall power consumption of the main control chip can be reduced on the premise of ensuring the stable work of the main control chip.

On-demand paging support for confidential computing is described. An example of an apparatus includes circuitry including one or more processors including a first processor, the first processor including a TEE and registers, wherein the one or more processors are to: receive a memory access request associated with a trust domain (TD), wherein one or more direct memory access payloads associated with the request being generated by a protocol engine (PE) of a peripheral device and written to a host interface (HIF), the HIF including an address translation engine (ATE); and, in response to a page fault being identified for a payload, divert the payload and forward a payload fault to one or more TD fault buffers in a set of registers, and resolve the page fault by an ATE driver and a virtual machine manager using the TEE.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

A data transmission method is provided. The data transmission method may be applied to an apparatus. The data transmission method may include the following steps. The modem of an apparatus may receive or transmit data packets from or to the host device of the apparatus through a host interface in an event that the modem is in a first mode during the period. Then, the modem may store the data packets in a buffer in an event that the modem is in a second mode during the period. The host interface is in an active mode in an event that the modem is in the first mode, and the host interface is in a low power low-power mode in an event that the modem is in the second mode.

An apparatus with a solid state drive (SSD) configured to manage storage resources for proof of space activities. The SSD has a host interface configured to receive at least read commands and write commands from an external host system. The SSD has memory cells formed on at least one integrated circuit die, and a processing device configured to control executions of the read commands and the write commands. In response to an indication of a storage space request for the host system, the apparatus identifies a portion of storage resources used to store the data of the proof of space plot, and reallocates the portion to service the host system. Subsequently, the SSD can continue proof of space activities based on the proof of space plot using the data stored in a remaining portion of the storage resources initially allocated to the proof of space plot.

A distributed network that may include multiple links; and multiple physical nodes that in communication with each other via the multiple links, to form multiple redundant paths, wherein at least some of the redundant paths form a daisy chain; wherein the multiple physical nodes comprise output ports configured to interface with external hosts. The multiple physical nodes are configured to supports software defined networking (SDN).

A method for operating a storage device capable of improving reliability of a memory system is provided. The method includes providing a storage device which includes a first component and a second component; receiving, via a host interface of the storage device, a command for requesting failure possibility information about the storage device from an external device; and providing, via the host interface, the failure possibility information about the storage device to the external device in response to the command.

An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.

A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

In one embodiment, a local networking device includes a host interface to receive packets from a local host device, packet processing hardware to receive cryptographic material offloaded from the local host device over the host interface, perform cryptographic operations on the packets based on the cryptographic material, generate datagram transport layer security (DTLS) headers including respective DTLS sequence numbers in hardware, and encapsulate the packets with the DTLS headers in hardware, and a network interface to send the packets with the DTLS headers to a remote networking device over a packet data network.

In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

The embodiment of the invention provides storage equipment for improving storage capacity through multiple main control chips, and relates to the technical field of storage. The storage device comprises a master control component, a slave control component and an inter-chip communication link, each of the master control part and the slave control part comprises a host interface, a host command processing unit, a storage command processing unit, a storage medium management unit and a medium interface controller; the master control part and the slave control part are communicated through an inter-chip communication link; a host interface in the main control component is coupled with a host and receives an IO command sent by the host; the master control component and the slave control component cooperatively process IO commands received by the master control component through a host interface of the master control component through an inter-chip communication link. According to the embodiment of the invention, the master control component and the slave control component cooperatively process the IO command from the host to access the NVM chip, so that the requirements of large-capacity and high-performance storage equipment are met.

The invention relates to a low-power-consumption cross matrix system based on an AXI protocol and a processing method. According to the scheme, the low-power-consumption cross matrix system is composed of a slave interface module, a slave switch module, a host switch module, a host interface module, a gated clock module and a power consumption management module. The slave interface modules are responsible for processing read-write requests and write data sent by the hosts, the read-write requests and the write data are sent to the corresponding host interface modules after being subjected to routing and arbitration processing of the slave switches and the host switches, and finally the data are received and processed by the corresponding slaves; when one or more hosts or slaves connected with the cross matrix are in an idle state, the corresponding interface modules can pause the clock and cut off the power supply without processing read-write requests, and the power consumption management module is responsible for completing the operation and performing power consumption management on the whole system, so that the power consumption of the cross matrix is reduced.

The invention relates to the technical field of data encryption, in particular to a USB multi-port equipment access encryption authentication method and system. Comprising a power supply module 100, a master control MCU unit 200, an analog signal switching unit 300, a USB expansion unit 400, a plugging detection unit 500 and a host interface unit 600, and the master control MCU unit 200 is connected with the analog signal switching unit 300, the USB expansion unit 400, the plugging detection unit 500 and the host interface unit 600 and used for achieving signal control and state management; the method does not depend on operating system permission or user behaviors, software installation is not needed, identification, authentication and control operations are completed completely through hardware, and non-bypassing performance is achieved. The problems that a traditional white list strategy is easy to bypass, needs to depend on authorization of an operating system and lacks physical isolation are effectively solved. The system supports upgrade authentication algorithms such as RSA, ECC and the like, supports a log recording function and a remote communication management module, can realize strategy adjustment through a firmware upgrade mechanism, and meets access management and control requirements of different scenes.

Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

The invention discloses a protocol conversion device and method for a manned aircraft control rudder. Aiming at the problem that the existing general control rudder is difficult to be compatible with the mainstream flight control protocol of the manned aircraft, the technical scheme of the invention can convert the control rudder protocol into the SBUS / PPM protocol. Firstly, the control rudder serves as the control rudder of the aircraft and inputs a control signal into the protocol conversion unit through the USB line, then the protocol conversion unit reads in the control signal through the USB Host interface, and the microprocessor analyzes the signal, extracts the numerical value of each channel and carries out linear mapping. And the microprocessor simultaneously performs SBUS / PPM coding according to the mapped numerical values and outputs a signal, wherein each byte of an SBUS / PPM coding frame is realized through a timer. And finally, the flight controller automatically selects and analyzes the SBUS / PPM signals according to requirements.

A smart memory module includes at least one memory device connected to at least one channel, a controller configured to control the at least one memory device, and a host interface circuit configured to perform peer-to-peer (P2P) communication with an external device, and to receive, from a host device, a live migration request. The controller is configured to perform, in response to the live migration request, a migration operation of transmitting buffer data to a target device through the P2P communication under a buffer-full condition.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

The invention belongs to the field of integrated circuit design, and provides a novel transaction ID coding method applied to an AXI protocol. Address decoding is carried out in advance in an AXI host interface, gating signals of all slaves are compiled into transaction IDs in a one-hot code mode, and therefore coding of all transaction IDs can be completed in the host interface instead of expanding the bit width of ID coding step by step in next-level interconnection. The address decoder is located on the critical path of the interconnection matrix in a traditional interconnection architecture, the address decoder is moved into the host interface, the delay of the critical path in the interconnection matrix is shortened, the dominant frequency of the system can be improved, address decoding is not needed in the interconnection matrix any more, combinational logic in the interconnection matrix can be simplified, and the system reliability is improved. The design complexity is reduced, meanwhile, the data cache position needing to be returned in an order-preserving mode can be closer to a host end, the memory access efficiency is improved, and the problem of a memory wall is effectively relieved.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.