207 results about "Host interface" patented technology

Technologies for configuring multiple virtual bridges and interface mappings in a Service Function Chaining (SFC) architecture are described. A DPU can include memory to store a configuration file specifying the virtual bridges and interface mappings, and a processing device operatively coupled to the memory. The processing device, according to the configuration file, generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU, and the second virtual bridge is controlled by a user-defined logic. The processing device adds add one or more host interfaces to the second virtual bridge, a first service interface to the first virtual bridge to operatively couple to the first network service, and one or more virtual ports between the first virtual bridge and the second virtual bridge.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

The invention relates to the technical field of data encryption, in particular to a USB multi-port equipment access encryption authentication method and system. Comprising a power supply module 100, a master control MCU unit 200, an analog signal switching unit 300, a USB expansion unit 400, a plugging detection unit 500 and a host interface unit 600, and the master control MCU unit 200 is connected with the analog signal switching unit 300, the USB expansion unit 400, the plugging detection unit 500 and the host interface unit 600 and used for achieving signal control and state management; the method does not depend on operating system permission or user behaviors, software installation is not needed, identification, authentication and control operations are completed completely through hardware, and non-bypassing performance is achieved. The problems that a traditional white list strategy is easy to bypass, needs to depend on authorization of an operating system and lacks physical isolation are effectively solved. The system supports upgrade authentication algorithms such as RSA, ECC and the like, supports a log recording function and a remote communication management module, can realize strategy adjustment through a firmware upgrade mechanism, and meets access management and control requirements of different scenes.

Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

The invention discloses computer peripheral interface management and control equipment based on fingerprint identification. The computer peripheral interface management and control equipment comprises an FPGA main controller, a fingerprint identification module, a user interaction module, a peripheral interface output module, a host interface input module and a power management module, in the working process, the fingerprint identification module compares user fingerprint information, confirms the identity and notifies the FPGA main controller, a USB input interface and an HDMI input interface of the host interface input module are connected with a USB output interface, an HDMI output interface and a VGA output interface of the peripheral interface output module, and a user is notified through a state indicator lamp of the user interaction module; and when the user leaves, a locking key of the user interaction module is clicked, and after receiving a locking key signal, the FPGA main controller cuts off USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) input interfaces of the host interface input module and USB, HDMI and VGA (Video Graphics Array) output interfaces of the peripheral interface output module, and notifies the user through a state indicator lamp of the user interaction module. External connection of the computer peripheral interface can be cut off through one key, and attack of a hardware layer can be defended.

The application discloses a kind of method and device that SSD control chip self-adapting abnormal stop IO, it is related to SSD technical field, comprising: obtaining the fatal error interrupt signal generated by multiple function modules in SSD control chip, global stop flow enable signal is generated by hardware logic circuit;In response to this signal, synchronously control host interface side stops transmitting data to host, and control flash interface side stops reading and writing NAND flash to erase operation.By pure hardware circuit, the fast convergence of error signal and the generation of global stop flow instruction are realized, the extremely fast response of nanosecond to microsecond level is achieved, and the defect of large delay of software dependent scheme is fundamentally overcome.Two ends stop flow are triggered synchronously using single enable signal, the atomicity and cooperativity of operation are ensured, and the risk of data inconsistency is eliminated.The mechanism is independent of central processing unit and firmware operation, and can still be independently and reliably executed in the extreme case of core component failure, significantly improving the data integrity and system reliability of SSD.

A storage controller, a client system, and a method of operating a storage controller are disclosed. The client system includes a client host device and a client storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control read and write operations to the storage memory, and a homomorphic encryption and decryption accelerator configured to: based on receiving a read request from the client host device, perform homomorphic encryption on first plaintext data read from the storage memory to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client host device through the host interface; and based on receiving a write request from the client host device, perform homomorphic decryption on second homomorphic ciphertext data received through the host interface to generate second plaintext data, and write the second plaintext data into the storage memory.

A computer data storage device connected to a host computer through a host interface is disclosed. The computer data storage device contains a storage unit which stores data and includes a user area and a security area; a user input / output unit which receives an input relating to an operation mode of the computer data storage device, that is, a normal mode and a management mode, and related information from a user and displays same; and a control unit which communicates with the host computer and is connected to the storage unit and the user input / output device so as to control the operation mode. The control unit is configured to, when the host computer is to change structure information of the user area, generate recovery information for preserving data stored in the user area and store same in the security area.

An integrated circuit includes a host interface, operatively coupled to a host device executing a tenant operating system (OS) on bare metal, and one or more hardware accelerators, operatively coupled to the host interface. The one or more hardware accelerators encrypt a swap file retrieved from the host device and initiate transfer of the encrypted swap file to a network storage device coupled to a cloud-based server. A central processing unit (CPU) is operatively coupled to the host interface and, with the one or more hardware accelerators, are to host a hardware-accelerated snapshot client that coordinates snapshot activities, associated with the encrypted swap file, between a snapshot manager, hosted by the cloud-based server, and a snapshot user interface executed on the host device.

A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.

An integrated circuit (IC) chip and / or system includes a processing core and an input / output (I / O) controller, coupled to a host interface, to detect a plurality of state transitions in a data signal received over a system management bus (SMBUS) of the host interface and generate an interrupt responsive to detecting each state transition. An interrupt controller routes each interrupt to the processing core. The processing core, in response to receipt of each respective interrupt, retrieves a corresponding state transition received over the SMBUS and stores, in a memory, the corresponding state transition.

A storage system includes a host device and a storage device that are connected to each other through a main link and a sub link. The storage device includes a nonvolatile memory device configured to store data and a storage controller package configured to control the nonvolatile memory device under control of the host device. The storage controller package includes an on-chip bus, a host interface connected to the on-chip bus and the main link, a memory interface connected to the on-chip bus and the nonvolatile memory device, a storage processor connected to the on-chip bus, and configured to perform an in-band communication with the host device through the on-chip bus, the host interface and the main link, and a microcontroller connected to the on-chip bus and the sub link, and configured to perform an out-of-band communication with the host device through the sub link.

A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

This disclosure relates to a controller for controlling a memory device and a method of operating the controller. The controller may include: a host interface adapted to acquire a write command received from a host; and a processor adapted to control a write operation of the memory device in response to the acquired write command, wherein, when the workload of the processor's background operations is greater than the workload of the host write operation, the host interface is further adapted to: determine a delay time amount, and provide the completion response to the host after delaying the write command by the delay time amount.

According to one embodiment, a host interface circuit includes a physical layer that performs communication with a host, and a protocol control circuit that determines a transfer rate between the physical layer and the host. When a temperature detected by a temperature sensor becomes equal to or higher than a first temperature, the protocol control circuit changes the transfer rate from a first transfer rate to a second transfer rate. The protocol control circuit transitions to a first mode in which a change of the transfer rate based on a first request from the host is prohibited.

A data storage device includes: a data storage medium; a processor comprising a plurality of processor cores; a plurality of application acceleration black-box (AABB) slots including reconfigurable logic blocks, interconnects, and memories; a host interface that receives a host command from a remote application running on a remote host computer, wherein the host command includes an image file including a register-transfer level (RTL) bitstream and a firmware driver; and a configuration controller that downloads the RTL bitstream to an AABB slot of the plurality of AABB slots and reconfigure the AABB slot, and load the firmware driver to a processor core of the processor. The processor core loaded with the firmware driver runs a data acceleration process of the remote application to access and process data stored in the data storage medium using the RTL bitstream downloaded in the AABB slot.

The embodiment of the invention provides a control component for managing a namespace key, and relates to the technical field of storage. The control component comprises a host interface and a host command processing unit, and the host command processing unit comprises a key management unit and an encryption / decryption unit; the key management unit is coupled with the host interface, receives a custom command which is sent by a host and indicates key management through the host interface, processes the custom command and manages a namespace key corresponding to a specified namespace; the encryption / decryption unit is coupled with the key management unit, and the encryption / decryption unit carries out encryption operation on data written into the specified namespace or carries out decryption operation on data read from the specified namespace according to the namespace key. In the embodiment, only the host command processing unit senses the namespace secret key, other units cannot sense the namespace secret key, and although different namespace secret keys exist, the data organization on the data path and the NVM chip cannot be influenced.

The invention discloses an airborne network data integrity receiving system and method based on a time linked list. The system comprises a link state monitoring unit, a data error diagnosis unit, a receiving management unit, a time linked list management unit, a repeated frame judgment unit, a received message time linked list, a management register set and a host interface management unit. The link state monitoring unit and the data error diagnosis unit are sequentially connected to the receiving management unit, the time linked list management unit, the repeated frame judgment unit, the management register group and the received message time linked list are all connected to the receiving management unit, and the management register group is further connected to the host interface management unit; and the time linked list management unit and the repeated frame judgment unit are connected to the received message time linked list. According to the invention, network link state monitoring, data error diagnosis and repeated data frame hardware identification, judgment and integrity receiving functions under a time redundancy mechanism in an airborne complex environment are realized.

The application discloses a micro-instruction processor based on an extensible NAND interface and a method thereof; the processor adopts: a longitudinal link which, by configuring an adaptive module, an instruction storage module, an extensible instruction set module and an interface decoding and executing module, completes configuration, instruction and execution, realizes complete programmability of control logic, the adaptive module actively reads configuration information in an initialization stage, and generates a complete running context in combination with metadata provided by external firmware; a transverse link which adopts a host interface, a data memory module, a data preprocessing module, a physical layer interface and a storage medium, and constructs a high-throughput and low-delay data link. The link focuses on efficient flow of I / O data, and ensures that a host request can quickly and reliably reach a NAND flash medium. The technical scheme of the application can be compatible with NAND flash of different brands and different models, and effectively reduces the adaptation cost of a storage controller.

The application relates to an adaptation method and device of a VST plug-in, a network live broadcast system, computer equipment and a computer readable storage medium; the method comprises the following steps: after a host is started, scanning file information of the VST plug-in to identify corresponding version information; when a user opens the VST plug-in, creating a main window on a host interface according to the version information, creating a first window within the range of the main window, and creating a second window of the VST plug-in on the first window; when the user performs a first operation on the main window, calling the first window and the second window to perform the first operation; when the user performs a second operation on the second window, calling the main window to perform the second operation; according to the technical scheme, the host software can independently adapt to VST plug-ins of various versions, the use efficiency of the VST plug-in is improved, the complexity of the user in the audio processing process is reduced, and the user application experience is improved.

The invention relates to a data storage device and a memory controller. The data storage device comprises a memory device and a host interface. The host interface communicates with a host device and includes a first circuit and a second circuit. The first circuit is disposed on a signal receiving path and operates in a first power domain. The first circuit receives, from a host device, a plurality of signals including a clock signal provided by the host device. The second circuit is disposed on a signal transmission path and operates in a first power domain. The second circuit outputs data read from the memory device according to the clock signal. The first circuit is coupled to the second circuit, and the clock signal is directly provided to the second circuit by the first circuit.

Digital microphone arrangement (100) configured to be integrated into a host device, the assembly comprising: a housing (110) which has a host interface (113); a transducer (102) for microelectromechanical systems (MEMS) which is arranged in the housing; an integrated circuit (103, 200) arranged in the housing, the integrated circuit comprising: a signal processing circuit (201) coupled to an output of the converter; an interface protocol circuit (202) coupled to an output of the signal processing circuit; a first output driver circuit (203) coupled to the interface protocol circuit and comprising a corresponding plurality of parallel driver stages (230), wherein each driver stage has a driver (231) and a configurable resistor (232, 300) which couples an output (233) of the driver to a first contact (290) of the host interface, wherein the configurable resistors of the first output driver circuit form a first series termination resistor (Z O ) form; and a controller (204, 501) coupled to and configured with the first output driver circuit to set a resistance of at least one configurable resistance to compensate for process error deviations, such that the configurable resistance of at least one driver stage is different from the configurable resistance of at least one other driver stage of the first output driver circuit.