109 results about "Host interface" patented technology

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

The application discloses a kind of method and device that SSD control chip self-adapting abnormal stop IO, it is related to SSD technical field, comprising: obtaining the fatal error interrupt signal generated by multiple function modules in SSD control chip, global stop flow enable signal is generated by hardware logic circuit;In response to this signal, synchronously control host interface side stops transmitting data to host, and control flash interface side stops reading and writing NAND flash to erase operation.By pure hardware circuit, the fast convergence of error signal and the generation of global stop flow instruction are realized, the extremely fast response of nanosecond to microsecond level is achieved, and the defect of large delay of software dependent scheme is fundamentally overcome.Two ends stop flow are triggered synchronously using single enable signal, the atomicity and cooperativity of operation are ensured, and the risk of data inconsistency is eliminated.The mechanism is independent of central processing unit and firmware operation, and can still be independently and reliably executed in the extreme case of core component failure, significantly improving the data integrity and system reliability of SSD.

A storage controller, a client system, and a method of operating a storage controller are disclosed. The client system includes a client host device and a client storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control read and write operations to the storage memory, and a homomorphic encryption and decryption accelerator configured to: based on receiving a read request from the client host device, perform homomorphic encryption on first plaintext data read from the storage memory to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client host device through the host interface; and based on receiving a write request from the client host device, perform homomorphic decryption on second homomorphic ciphertext data received through the host interface to generate second plaintext data, and write the second plaintext data into the storage memory.

A computer data storage device connected to a host computer through a host interface is disclosed. The computer data storage device contains a storage unit which stores data and includes a user area and a security area; a user input / output unit which receives an input relating to an operation mode of the computer data storage device, that is, a normal mode and a management mode, and related information from a user and displays same; and a control unit which communicates with the host computer and is connected to the storage unit and the user input / output device so as to control the operation mode. The control unit is configured to, when the host computer is to change structure information of the user area, generate recovery information for preserving data stored in the user area and store same in the security area.

An integrated circuit (IC) chip and / or system includes a processing core and an input / output (I / O) controller, coupled to a host interface, to detect a plurality of state transitions in a data signal received over a system management bus (SMBUS) of the host interface and generate an interrupt responsive to detecting each state transition. An interrupt controller routes each interrupt to the processing core. The processing core, in response to receipt of each respective interrupt, retrieves a corresponding state transition received over the SMBUS and stores, in a memory, the corresponding state transition.

A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.

This disclosure relates to a controller for controlling a memory device and a method of operating the controller. The controller may include: a host interface adapted to acquire a write command received from a host; and a processor adapted to control a write operation of the memory device in response to the acquired write command, wherein, when the workload of the processor's background operations is greater than the workload of the host write operation, the host interface is further adapted to: determine a delay time amount, and provide the completion response to the host after delaying the write command by the delay time amount.

The application discloses a micro-instruction processor based on an extensible NAND interface and a method thereof; the processor adopts: a longitudinal link which, by configuring an adaptive module, an instruction storage module, an extensible instruction set module and an interface decoding and executing module, completes configuration, instruction and execution, realizes complete programmability of control logic, the adaptive module actively reads configuration information in an initialization stage, and generates a complete running context in combination with metadata provided by external firmware; a transverse link which adopts a host interface, a data memory module, a data preprocessing module, a physical layer interface and a storage medium, and constructs a high-throughput and low-delay data link. The link focuses on efficient flow of I / O data, and ensures that a host request can quickly and reliably reach a NAND flash medium. The technical scheme of the application can be compatible with NAND flash of different brands and different models, and effectively reduces the adaptation cost of a storage controller.

The invention relates to a data storage device and a memory controller. The data storage device comprises a memory device and a host interface. The host interface communicates with a host device and includes a first circuit and a second circuit. The first circuit is disposed on a signal receiving path and operates in a first power domain. The first circuit receives, from a host device, a plurality of signals including a clock signal provided by the host device. The second circuit is disposed on a signal transmission path and operates in a first power domain. The second circuit outputs data read from the memory device according to the clock signal. The first circuit is coupled to the second circuit, and the clock signal is directly provided to the second circuit by the first circuit.

Digital microphone arrangement (100) configured to be integrated into a host device, the assembly comprising: a housing (110) which has a host interface (113); a transducer (102) for microelectromechanical systems (MEMS) which is arranged in the housing; an integrated circuit (103, 200) arranged in the housing, the integrated circuit comprising: a signal processing circuit (201) coupled to an output of the converter; an interface protocol circuit (202) coupled to an output of the signal processing circuit; a first output driver circuit (203) coupled to the interface protocol circuit and comprising a corresponding plurality of parallel driver stages (230), wherein each driver stage has a driver (231) and a configurable resistor (232, 300) which couples an output (233) of the driver to a first contact (290) of the host interface, wherein the configurable resistors of the first output driver circuit form a first series termination resistor (Z O ) form; and a controller (204, 501) coupled to and configured with the first output driver circuit to set a resistance of at least one configurable resistance to compensate for process error deviations, such that the configurable resistance of at least one driver stage is different from the configurable resistance of at least one other driver stage of the first output driver circuit.

An apparatus includes a host interface, a network interface, and a programmable circuitry communicably coupled to the host interface and the network interface. The programmable circuitry can include one or more processors to implement network interface functionality, and a discrete trusted platform module (dTPM) to enable the one or more processors to establish a secure boot mechanism for the apparatus, wherein the one or more processors are to instantiate a virtual TPM (vTPM) manager that is associated with the dTPM, the vTPM manager to host vTPM instances corresponding to one or more virtualized environments hosted on at least one of the programmable circuitry or a host device communicable coupled to the apparatus.

The invention relates to the technical field of on-chip communication, in particular to a multicast AXI crossbar switch design method and device adaptive to an ML accelerator, a host initiates AXI transmission, slaves respond to the AXI transmission, in a multicast task, a write request of the host is distributed to a plurality of slaves, each host interface is connected to an AXID Demux module for write request splitting, and the write request is transmitted to the host interface through the AXI Demux module. Each slave interface is connected to an AXIMux module so as to be connected with different AXI hosts; the whole crossbar switch is configured with an address mapping table Address Map, a complete address space is divided into a plurality of address intervals, and each address space is mapped to one slave; when a host initiates a write request, a target address is compared with an address mapping rule in an address mapping table, so that the request is matched to a corresponding slave, an AXI related bus signal is transmitted to the corresponding slave in an original mode, and only AW, W and B channels of the AXI are involved for multicast transactions. Compared with the prior art, the method has the advantages that the performance can be ensured, the transmission efficiency is remarkably improved, the multicast function is supported, and the power consumption delay overhead is controlled within an acceptable range.

The examples described in this document relate to a network interface device. In some examples, the network interface device includes: a network interface, a direct memory access (DMA) circuitry, a host interface, memory, one or more processors, and a circuitry designed to: based on an operating configuration specifying standalone operation, cause the network interface device to operate in standalone mode to run one or more applications; and based on an operating configuration specifying companion operation, cause the network interface device to operate in companion mode to provide at least one host system with access to one or more hardware resources that the network interface device can access.

This document describes an error management system for storage devices. While error messages are primarily managed by a controller and sent as a warning via the host interface, the controller can have a hardware component for independently managing certain error messages to which it may be particularly prone, and warns of these via a timeout signal. This allows for the management of these error messages even if the controller fails due to various faults.

The invention discloses a graphics card docking station capable of switching and connecting input interfaces, which comprises a main board, and an OCuLink interface, a lightning interface, a PCIe signal multiplexing chipset, a selection switch and a PCIeX16 slot are integrated on the main board; the OCuLink interface and the thunder and lightning interface respectively output two groups of independent PCIe signals, the PCIe signals comprise a data signal, a clock signal and a control signal, the mainboard integrates the OCuLink interface and the thunder and lightning interface at the same time, free switching of the two interfaces is realized through a signal adaptation conversion function of the PCIe signal multiplexing chipset and a switching control function of the selection switch, and the conversion efficiency is improved. The method is suitable for all computer hosts with OCuLink interfaces or thunder and lightning interfaces in the market, a user does not need to purchase a display card docking station again due to the fact that the types of the host interfaces are changed, the use cost is reduced, and the application range is expanded.

The present disclosure describes apparatuses and methods for implementing a pipelined processor with configurable grouping of processor elements. In aspects, an apparatus comprises a host interface configured for communication with a host system, a media interface configured to enable access to storage media, and a plurality of processor elements operably coupled to at least one of the host interface and the media interface. The plurality of processor elements is organized into multiple stages of a pipelined processor for processing data access commands associated with the host system. In various implementations, the plurality of processor elements can be selectively grouped to form the multiple stages of the pipelined processor and loaded with microcode to implement respective functions of each stage of the pipelined processor. By so doing, the pipelined processor may be configured based on various parameters to improve processing performance when processing the data access commands of the host system.

The invention discloses an enterprise console dynamic expansion system and method based on hybrid discovery and zero-trust security. The system comprises a) a service registration and discovery module which supports third-party software services (such as business process automation tools n8n, Node-RED and the like) and software service active registration, service announcement and adaptive hybrid discovery in hardware equipment; b) a context-aware extension matching engine, which takes user-role-site-equipment-data five-dimensional contexts as function matching conditions at the same time; c) a zero-trust security control module which establishes three-level attribute-based access control of'site-equipment-data 'and continuously calculates a real-time risk score; d) the system is rendered dynamically, the remote component is mounted to a host interface slot in a one-time session token mode through a remote component dynamic loading technology, and hot replacement is kept in the life cycle without restarting the host; and e) a device service adapter supporting registration and discovery of resource-constrained devices through a lightweight protocol. According to the scheme, zero-code dynamic extension, multi-tenant isolation and zero-trust security can be achieved, and the method is suitable for the multi-site environment of the Internet of Things.

This invention relates to an FPGA-based BiSS-C protocol host interface and its implementation method. The host interface includes: a serial port instruction parsing module for receiving and parsing serial port instructions issued by a host computer; a pulse trigger control module for generating a corresponding number of trigger pulses according to the parsed instruction type; a clock generation module for generating a MA clock signal conforming to the BiSS-C protocol timing under the drive of the trigger pulses; a parameter latching module for latching address parameters and / or data parameters; a data decoding module for sampling and decoding the SLO signal from the BiSS-C slave device under the synchronization of the MA clock signal; and a CRC check module for performing cyclic redundancy check on the decoded data. This host interface realizes the parsing and response to host computer commands through a custom serial port instruction set, and supports multiple working modes such as read angle and register read / write.

The utility model provides a photovoltaic inverter interface expansion conversion circuit. The photovoltaic inverter interface expansion conversion circuit comprises a main control chip, an RS485 slave, a first RS485 host, a second RS485 host, a digital isolator, a photovoltaic inverter access end, an inverter data disassembly rod access end and a collector data input end. The photovoltaic inverter access end comprises a power supply input end and an RS485 slave interface; the inverter data disassembly rod access end comprises a power supply output end and a first RS485 host interface; the data input end of the collector comprises a second RS485 host interface; the input end of the RS485 slave is connected with the RS485 slave interface, the output end of the RS485 slave is connected with the input end of the digital isolator, and the output end of the digital isolator is connected with the main control chip. According to the scheme, two channels are supported to realize simultaneous communication without mutual influence by adopting hardware isolation and matching with program software.

Disclosed herein are related to a system and a method for offloading distributed parity calculations from a server including a plurality of solid-state drives (SSDs) in communication with a host via a host interface. Each SSD includes a processor. The processor of each SSD may be configured to access a host address space via the host interface, determine parity information for data stored across a plurality of buffers in the host address space, and output the parity information to the host interface.

The application provides a fast application card monitoring method and device and a storage medium. The method monitors the execution sequence of each node interface of a host call, the execution sequence of an unordered interface, and the execution sequence of a node method, obtains host interface call link information, compares the link information with preset link information, and reports an error code in the case of link information error, thereby greatly improving the troubleshooting efficiency of fast application card abnormal problems.

In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose a device emulation function to the host device, maintain a peripheral device cache, invalidate a cache entry in peripheral device cache in response to receiving a cache invalidation from a backend function, execute a translation function to translate between a format of the device emulation function and a format of the backend function, receive the cache invalidation from the backend function, translate the cache invalidation to the format of the device emulation function, and 10 provide the translated cache invalidation function to the device emulation function being executed by a processor of the host device.

The invention relates to cache coherency. In one embodiment, a device includes a host interface to be connected to a host device via a data communication bus; and at least one processing core to expose the device emulation functionality to the host device; maintaining a peripheral equipment cache; invalidating a cache entry in the peripheral cache in response to receiving a cache invalidation from the back-end function; a conversion function is executed to convert between a format of the device emulation function and a format of the back-end function, receive a cache failure from the back-end function, convert the cache failure to the format of the device emulation function, and provide the converted cache failure function to the device emulation function being executed by the host device processor.

The present application belongs to the technical field of protecting computer hardware and data security, and more particularly to a USB mass storage device security isolation system and a use method thereof. The system comprises: a device interface unit for device management and enumeration, metadata analysis and processing, and data interaction control; a host interface unit for access control policy execution and virtual view planning, standard USB mass storage device simulation, and host request protocol conversion; a mapping unit for constructing and maintaining a virtual-real address mapping table, completing conversion of virtual logical allocation unit numbers to device logical allocation unit numbers, and performing dynamic allocation and management of storage space according to an idle virtual logical allocation unit bitmap and an idle device logical allocation unit bitmap; and an isolation scheduling unit responsible for issuing operation instructions and delivering messages between the units. The present application constructs a pure virtual disk view presented to the host, thereby shielding the host from perceiving restricted files.

A memory sub-system having: a host interface operable on a connection from the host interface to a host system outside of the memory sub-system; random access memory cells configured to provide a memory space accessible to the host system over the connection via a memory access protocol; non-volatile memory cells configured to provide a storage space accessible to the host system over the connection via a storage access protocol; and a controller configured to execute a storage access request, received from the host system over the connection according to the storage access protocol, to read data into the memory space from a logical block address in the storage space. The controller can also execute a storage access request, received over the connection according to the storage access protocol, to write data available in the memory space to a logical block address in the storage space.

This invention relates to the field of computer storage expansion technology, and discloses a storage adaptation system and storage adaptation control method, comprising: a host interface for communicating with a host system; multiple storage interfaces for connecting multiple storage devices; a power control module configured to provide time-sequential power supply to the multiple storage interfaces to stagger the power-on times of the multiple storage devices; and a main control module configured to respond to the host's device enumeration request through the host interface before all the multiple storage devices enter the ready state, causing the host to wait, thereby shielding the host from the differences in the ready times of the storage devices caused by the time-sequential power supply. This invention avoids power surges at the physical level by staggering power supply, and at the logical level by using the enumeration synchronization mechanism of the main control module to shield the host from the timing differences of physical power-on, ensuring that the host can fully identify all storage devices and ensuring the normal operation of the expansion function.