289 results about "Host interface" patented technology

The invention discloses a shared cache system applied to a real-time network terminal chip. The shared cache system comprises queue management, enqueue scheduling control, dequeue scheduling control, write bus control, read bus control, a data cache, a register module, an RXFIFO module and a TXFIFO module. According to the cache allocation strategy, the variable-length data is stored by using the fixed-length unit. The user can customize and configure the private space, the residual space is the shared space, and the storage utilization rate is high. The shared cache is mainly used for storing data packets sent by an external application layer through a host interface. And storing the received data packet, extracting frame information according to a network flow protocol, and directly discarding frames which do not meet the protocol. The shared cache is provided with a dynamic cache structure, the state of each queue can be updated in real time, frame loss is prevented, and the data stream processing capacity is improved. And meanwhile, complex hybrid scheduling of a real-time network is met. The whole shared cache is subjected to anti-radiation reinforcement, the scene requirement of space navigation application is met, and high reliability is achieved.

Technologies for configuring multiple virtual bridges and interface mappings in a Service Function Chaining (SFC) architecture are described. A DPU can include memory to store a configuration file specifying the virtual bridges and interface mappings, and a processing device operatively coupled to the memory. The processing device, according to the configuration file, generates a first virtual bridge and a second virtual bridge. The first virtual bridge is controlled by a first network service hosted on the DPU, and the second virtual bridge is controlled by a user-defined logic. The processing device adds add one or more host interfaces to the second virtual bridge, a first service interface to the first virtual bridge to operatively couple to the first network service, and one or more virtual ports between the first virtual bridge and the second virtual bridge.

Apparatuses, systems, and techniques for classifying a candidate uniform resource locator (URL) as a malicious URL using a machine learning (ML) detection system. An integrated circuit is coupled to physical memory of a host device via a host interface. The integrated circuit hosts a hardware-accelerated security service that obtains a snapshot of data stored in the physical memory and extracts a set of features from the snapshot. The security service classifies the candidate URL as a malicious URL using the set of features and outputs an indication of the malicious URL.

One embodiment provides a graphics processor comprising a host interface, a plurality of processing resources coupled with the host interface, a memory controller coupled with the plurality of processing resources and memory including error correction circuitry, and circuitry coupled with the memory controller and configured to facilitate integration of the graphics processor into a trusted execution environment. The circuitry is additionally configured to remap a region of the memory associated with the trusted execution environment in response to detection of an uncorrectable error by the error correction circuitry.

A data transmission method is provided. The data transmission method may be applied to an apparatus. The data transmission method may include the following steps. The modem of an apparatus may receive or transmit data packets from or to the host device of the apparatus through a host interface in an event that the modem is in a first mode during the period. Then, the modem may store the data packets in a buffer in an event that the modem is in a second mode during the period. The host interface is in an active mode in an event that the modem is in the first mode, and the host interface is in a low power low-power mode in an event that the modem is in the second mode.

A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

A network interface controller (NIC) capable of facilitating efficient data request management is provided. The NIC can be equipped with a command queue, a message chopping unit (MCU), and a traffic management logic block. During operation, the command queue can store a command issued via a host interface. The MCU can then determine a type of the command and a length of a response of the command. If the command is a data request, the traffic management logic block can determine whether the length of the response is within a threshold. If the length exceeds the threshold, the traffic management logic block can pace the command such that the response is within the threshold.

The invention relates to the technical field of data encryption, in particular to a USB multi-port equipment access encryption authentication method and system. Comprising a power supply module 100, a master control MCU unit 200, an analog signal switching unit 300, a USB expansion unit 400, a plugging detection unit 500 and a host interface unit 600, and the master control MCU unit 200 is connected with the analog signal switching unit 300, the USB expansion unit 400, the plugging detection unit 500 and the host interface unit 600 and used for achieving signal control and state management; the method does not depend on operating system permission or user behaviors, software installation is not needed, identification, authentication and control operations are completed completely through hardware, and non-bypassing performance is achieved. The problems that a traditional white list strategy is easy to bypass, needs to depend on authorization of an operating system and lacks physical isolation are effectively solved. The system supports upgrade authentication algorithms such as RSA, ECC and the like, supports a log recording function and a remote communication management module, can realize strategy adjustment through a firmware upgrade mechanism, and meets access management and control requirements of different scenes.

Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

The invention discloses a protocol conversion device and method for a manned aircraft control rudder. Aiming at the problem that the existing general control rudder is difficult to be compatible with the mainstream flight control protocol of the manned aircraft, the technical scheme of the invention can convert the control rudder protocol into the SBUS / PPM protocol. Firstly, the control rudder serves as the control rudder of the aircraft and inputs a control signal into the protocol conversion unit through the USB line, then the protocol conversion unit reads in the control signal through the USB Host interface, and the microprocessor analyzes the signal, extracts the numerical value of each channel and carries out linear mapping. And the microprocessor simultaneously performs SBUS / PPM coding according to the mapped numerical values and outputs a signal, wherein each byte of an SBUS / PPM coding frame is realized through a timer. And finally, the flight controller automatically selects and analyzes the SBUS / PPM signals according to requirements.

A smart memory module includes at least one memory device connected to at least one channel, a controller configured to control the at least one memory device, and a host interface circuit configured to perform peer-to-peer (P2P) communication with an external device, and to receive, from a host device, a live migration request. The controller is configured to perform, in response to the live migration request, a migration operation of transmitting buffer data to a target device through the P2P communication under a buffer-full condition.

The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

In one embodiment, a system includes a networking device including a network interface to receive network packets having headers including datagram transport layer security (DTLS) headers from a remote device over a packet data network, packet processing circuitry to identify first packets of the received packets for DTLS processing in the packet processing circuitry, identify second packets of the received packets to bypass DTLS processing in the packet processing circuitry and to be provided to software to perform DTLS processing on the second packets, and perform DTLS processing on the first packets, and a host interface to provide the DTLS processed first packets to the software, and provide the second packets to the software to perform DTLS processing on the second packets.

The invention discloses a control system supporting concurrent access of multiple hosts, a storage device and a medium, and relates to the technical field of data storage, the system runs on a control module externally connected with the storage device, and the system comprises a communication connection management unit used for establishing connection with multiple hosts through at least two host interfaces; the access request receiving unit is used for receiving access requests sent by different hosts through an uplink port of the multi-host switching chip, and the access arbitration and scheduling unit is used for carrying out real-time arbitration and unified scheduling on the requests according to a preset strategy; and the instruction forwarding and execution unit forwards an arbitrated instruction to the storage unit for execution through a downlink port, and the system further integrates a cache consistency management unit, a configurable arbitration strategy unit, a multi-mode storage space management unit and the like, so that the data consistency, the access efficiency and the system reliability during multi-host concurrent access are ensured. According to the scheme, efficient and safe parallel access of a plurality of hosts to a single storage device is realized.

The invention belongs to the technical field of semiconductors, and particularly relates to a dual-mode computing memory controller and a memory system for a PIM-DRAM. The dual-mode computing memory controller used for the PIM-DRAM comprises an address conversion module used for processing address mapping between a host and a PIM core; the command translation module is used for converting the host command into a PIM operation instruction; the command generation module is used for generating an address mapping command; the data translation module is used for managing data streams among the DDR bus, the on-chip bus and the DRAM; the multi-mode state machine is used for dynamically switching to a memory mode or a PIM mode according to different memory commands sent by the host; and the dual-mode computing access module is used for selecting an access space of the DRAM according to the address mapping command or the data route. According to the method, efficient and low-delay PIM operation is achieved by dynamically switching the memory and the calculation mode, meanwhile, the method is compatible with a traditional DDR protocol and can be directly integrated to an existing system, and a host interface does not need to be modified.

A storage device may include a plurality of non-volatile memories, a host interface configured to receive at least one packet including a TRIM command from a host device, and the host interface configured to determine a trim path for processing the TRIM command by comparing a first trim range threshold value and a trim range of the TRIM command, a trim manage module configured to generate status data by monitoring the at least one packet, the trim manage module configure to determine the first trim range threshold value based on the status data, and a processor configured to process the TRIM command based on the trim path.

An electronic device includes a slave interface configured for coupling to a machine controller of a machine via a multi-drop bus (MDB), a host interface configured for coupling to a first peripheral device of the machine, and memory storing one or more programs to be executed by the one or more processors and comprising instructions for: registering the electronic device as a slave to the machine controller, registering the first peripheral device as a slave to the electronic device, receiving from a mobile device a request to access signals generated by the first peripheral device, validating the request, and sending a reset command to the first peripheral device via the host interface, the reset command including a directive to update a signal destination address of the first peripheral device from a controller address of the machine controller to a device address of the electronic device.

Examples described in this document relate to a network interface device. In some examples, the network interface device includes a host interface; direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry may be configured to: based on received telemetry data from at least one switch: select a next-hop network interface device from among a plurality of network interface devices based on the received telemetry data.

The invention relates to the technical field of solid-state storage, and discloses an end-to-end data path protection method and system for a high-capacity solid-state hard disk, and the method comprises the steps: carrying out the real-time lightweight feature extraction of a data block; generating a dynamic feature matrix from the feature vectors, performing bit operation between the data blocks and the dynamic feature matrix, and performing LDPC coding on an intermediate data matrix; constructing mapping table entries for protecting the data blocks in the high-capacity solid state disk, and performing feature matrix nesting protection on the mapping table entries; and writing the protection data block and the protection mapping table item into the high-capacity solid state disk, and reading the protection data block and the protection mapping table item from the high-capacity solid state disk. According to the method, the dynamic matrix can be generated by fusing the data entropy value, the key mode and the physical state in real time, ECC strength self-adaption is achieved, user data features are embedded into a mapping table item, the same protection process is reused, a bidirectional verification chain is constructed, a feature matrix is bound from an NAND physical layer to a host interface in a full-link mode, and protection breakpoints are eliminated.

A storage product manufactured as a computer component and configured to have: a secure memory region to store cryptographic keys; a network interface; a local storage device having a storage capacity accessible via the network interface; and a host interface to be connected to a local host system. The local host system can control access, made via the network interface, to the storage capacity without receiving a portion of storage access messages received in the network interface. The storage product includes an access controller configured to determine whether a message, received in the network interface from the computer network or in the host interface from the local host system, has a valid verification code according to the cryptographic keys; and if not, the message can be rejected, deleted, discarded, or ignored without further processing.

The invention belongs to the technical field of automatic testing, and particularly relates to a pressure testing method, system and device for automobile OTA upgrading and a storage medium. The method aims to solve the technical problems that in the prior art, expansibility of a traditional testing method cannot meet the testing requirement of increasing range, and scripts need to be continuously changed to achieve pressure testing. Comprising the following steps: configuring an OTA upgrade pressure test task, and obtaining an image template of a vehicle-mounted host interface; establishing connection with a vehicle-end host through an ADB line; setting a pressure test frequency of the OTA upgrade pressure test task, automatically performing a pressure test according to the pressure test frequency by using an automatic pressure test program, identifying a target element on a vehicle end host interface through an image identification method based on the image template, and executing a pressure test operation according to the identified target element; and after the set pressure test times are reached, generating a pressure test report through the automatic pressure test program.

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input / output (I / O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input / output (I / O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.

The invention discloses computer peripheral interface management and control equipment based on fingerprint identification. The computer peripheral interface management and control equipment comprises an FPGA main controller, a fingerprint identification module, a user interaction module, a peripheral interface output module, a host interface input module and a power management module, in the working process, the fingerprint identification module compares user fingerprint information, confirms the identity and notifies the FPGA main controller, a USB input interface and an HDMI input interface of the host interface input module are connected with a USB output interface, an HDMI output interface and a VGA output interface of the peripheral interface output module, and a user is notified through a state indicator lamp of the user interaction module; and when the user leaves, a locking key of the user interaction module is clicked, and after receiving a locking key signal, the FPGA main controller cuts off USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) input interfaces of the host interface input module and USB, HDMI and VGA (Video Graphics Array) output interfaces of the peripheral interface output module, and notifies the user through a state indicator lamp of the user interaction module. External connection of the computer peripheral interface can be cut off through one key, and attack of a hardware layer can be defended.

The application discloses a kind of method and device that SSD control chip self-adapting abnormal stop IO, it is related to SSD technical field, comprising: obtaining the fatal error interrupt signal generated by multiple function modules in SSD control chip, global stop flow enable signal is generated by hardware logic circuit;In response to this signal, synchronously control host interface side stops transmitting data to host, and control flash interface side stops reading and writing NAND flash to erase operation.By pure hardware circuit, the fast convergence of error signal and the generation of global stop flow instruction are realized, the extremely fast response of nanosecond to microsecond level is achieved, and the defect of large delay of software dependent scheme is fundamentally overcome.Two ends stop flow are triggered synchronously using single enable signal, the atomicity and cooperativity of operation are ensured, and the risk of data inconsistency is eliminated.The mechanism is independent of central processing unit and firmware operation, and can still be independently and reliably executed in the extreme case of core component failure, significantly improving the data integrity and system reliability of SSD.

A memory system includes a plurality of volatile memory devices and a memory controller. The memory controller causes different amounts of error correction parity information to be generated depending on a request from a host device and depending on failed memory cell counts. The memory controller includes an error correction level (ECL) manager configured to receive cache line data from the host device through the host interface, and output an error correction code (ECC) control signal indicating one of a first correction level and a second correction level. The correction levels are based on cell reliability information and data reliability request information. The data reliability request information is associated with the cache line data. An ECC engine generates first parity symbols associated with the cache line data, and may, depending on the ECC control signal, generate additional parity symbols.

A storage controller, a client system, and a method of operating a storage controller are disclosed. The client system includes a client host device and a client storage device including a storage controller and a storage memory. The storage controller includes a host interface, a processor configured to control read and write operations to the storage memory, and a homomorphic encryption and decryption accelerator configured to: based on receiving a read request from the client host device, perform homomorphic encryption on first plaintext data read from the storage memory to generate first homomorphic ciphertext data, and provide the first homomorphic ciphertext data to the client host device through the host interface; and based on receiving a write request from the client host device, perform homomorphic decryption on second homomorphic ciphertext data received through the host interface to generate second plaintext data, and write the second plaintext data into the storage memory.

Embodiments of the present disclosure implement hardware-based snoop logic streaming timers for input / output (I / O) communications between a host and a shared network adapter in a computing system. The disclosed embodiments describe a hardware-based snoop logic and snoop logic timer function control of input / output (I / O) processor monitoring a defined memory area to detect a completion queue entry being written to a completion queue, and implementing streaming timers and interpacket timers, based on the completion queue entry and predefined configuration information for an associated host interface connection, to provide streaming data status, interpacket arrival times, and streaming timer expiration for the associated host interface connection.