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2202 results about "Direct memory access" patented technology

Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory (random-access memory), independent of the central processing unit (CPU).

Data exchange methods for a switch which selectively forms a communication channel between a processing unit and multiple devices

A switch is presented including a host input / output (I / O) port adapted for coupling to a controller, multiple device I / O ports each adapted for coupling to at least one device, and logic coupled between the host I / O port and the device I / O ports configured to selectively form a communication channel between the host I / O port and one of the device I / O ports. The switch may operate in a connected mode and a disconnected mode. When in the switch is in the disconnected mode, the logic may not form a communication channel between the host I / O port and any of the device I / O ports. In an ATA embodiment, the switch may comply with an AT attachment (ATA) standard, and thus be an ATA switch. The host I / O port may be adapted for coupling to an ATA controller, the device I / O ports may be adapted for coupling to at least one ATA device, and the logic may selectively form an ATA communication channel between the host I / O port and one of the device I / O ports. Several methods for exchanging data between a processing unit coupled to the host I / O port of the switch and one or more devices coupled to device I / O ports of the switch are described. Several methods for performing direct memory access (DMA) transfers to move data between a memory of the processing unit and one or more of the devices are also described.
Owner:ORACLE INT CORP

Intelligent controller accessed through addressable virtual space

File operations on files in a peripheral system are controlled by an intelligent controller with a file processor. The files are accessed as if the intelligent controller were an addressable virtual storage space. This is accomplished first by communicating controller commands for the intelligent controller through read/write commands addressed to a Command Region of a virtual storage device. The controller commands set up a Mapped Data Region in the virtual storage device for use in controlling data transfer operations to and from the peripheral system. With the Mapped Data Regions set up, blocks of data are transferred between the host and the intelligent controller in response to read/write commands addressed to the Mapped Data Region of the virtual storage device.In an additional feature of the invention file operations are communicated between host and controller through a device driver at the host and a device emulator at the intelligent controller. If the address in the device write/read command is pointing to the Command Region of the virtual storage device, a Command Region process interprets and implements the controller operation required by the controller command embedded in the device write/read command. One of these controller commands causes the Command Region processor to map a requested file to a Mapped Data Region in the virtual storage device. If the address detected by the detecting operation is in a Mapped Data Region, a Mapped Data Region process is called. The Mapped Data Region process reads or writes requested data of a file mapped to the Mapped Data Region addressed by the read/write command. This mapped file read or write is accomplished as a transfer of data over a data path separate from a control path. In an additional feature of the invention, the data transfer between host system and intelligent controller is accomplished by performing a direct memory access transfer of data.
Owner:CA TECH INC

Communications interface adapter for a computer system including posting of system interrupt status

To facilitate access of interrupt status information, interrupt posting status. POST-STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST-STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST-STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST-STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST-STAT registers. A host system software driver accesses the interrupt posting status POST-STAT registers via a bus access operation, changes a bit in a POST-STAT register, and monitors the result of the access and bit change in the mirror of the POST-STAT register in the system memory without a further bus read access. Advantageously, multiple accesses through the bus to verify when the written value status is correct is eliminated.
Owner:ADAPTEC +1
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