379 results about "Direct memory access" patented technology

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

Techniques to reduce direct memory access (DMA) overhead may include retrieving an address translation descriptor from a descriptor queue of a DMA engine, and updating an address translation table in the DMA engine with address translation information obtained from the location indicated by the address translation descriptor. A set of memory descriptors is then obtained from the descriptor queue. The set of memory descriptors can be processed by determining that the addresses in the set of memory descriptors are to be translated using the address translation table, and performing memory access operations by using the address translation table to translate the addresses in the set of memory descriptors.

The invention provides an efficient regional ocean forecasting method, and belongs to the technical field of ocean forecasting. A regional ocean mode four-dimensional variational assimilation system is constructed, and an adjoint mode calculation framework is established; after calculation modules are grouped according to dependency dimensions, a slave core parallel scheme is designed, and data transmission and calculation assembly line overlapping are realized by adopting a direct memory access step access and double-buffering technology; introducing a multi-scale time step adaptive integral algorithm and a gradient convergence acceleration model, predicting an optimal convergence path according to a historical iteration trajectory, dynamically adjusting a search direction and a step factor, completing four-dimensional variation assimilation, outputting an optimized ocean initial field, and performing forward integral forecasting to generate ocean state field variable forecasting data; the technical problem of insufficient timeliness of regional ocean forecasting caused by low calculation efficiency of the adjoint mode is solved.

The invention relates to a naked eye 3D binocular image acquisition and real-time processing system based on hardware synchronous triggering, and belongs to the technical field of image processing and three-dimensional display. According to the system, a hardware synchronous triggering mechanism is adopted, a time sequence synchronous control unit is used for sending a synchronous pulse signal to a binocular image sensor, and strict synchronization of left and right viewpoint image acquisition is ensured. The image signal processing unit processes collected original data, the stereo parallax correction module performs epipolar correction, and the sub-pixel interleaving module generates a composite view frame according to grating parameters of the display terminal. The system realizes high-speed data transmission through a double-buffer direct memory access DMA mechanism. The problems of visual tearing and weak stereoscopic impression caused by asynchronous binocular image acquisition in the prior art are solved, nanosecond-level synchronization precision is realized, optical crosstalk is reduced, and smoothness and comfort of stereoscopic display are ensured.

The invention discloses a data scheduling and control method based on mainboard memory straight-through, and relates to the technical field of computer hardware, the method comprises the following steps: pre-allocating a straight-through memory area for mounting equipment in a firmware initialization stage, establishing a mapping relation between equipment identification and a physical address of an exclusive memory segment, and through address translation and access control rules of a firmware layer, the device bypasses a system cache level and accesses the exclusive memory segment in a direct memory access mode. Constructing a firmware scheduling table based on the mapping relation to manage access requests of all devices, monitoring transmission delay in real time, and dynamically adjusting priority weight and bandwidth allocation in the scheduling table according to a monitoring result; and sequencing the requests according to the updated scheduling table to complete scheduling and control of the memory access behavior of the equipment. According to the method and the device, the delay bottleneck caused by multi-level copying and firmware scheduling lag in mainboard data forwarding is effectively solved.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

A data processing method using a scatter gather direct memory access (SG DMA), the method comprising: obtaining information for a rule table for specific subtasks of a SG DMA from a host, deriving the rule table for the specific subtasks based on the information, deriving source addresses, destination addresses and data sizes for the specific subtasks based on the rule table, and performing a SG DMA operation to transfer data of the data sizes located at the source addresses of a first memory to data spaces of the data sizes located at the destination addresses of a second memory.

A direct memory access controller (DMAC) includes a virtual channel, a physical channel, and a context manager. The virtual channel is configured to generate a flow control signal for executing a direct memory access (DMA) command. The physical channel includes read and write control logic to initiate data transmission from the source device to the destination device in accordance with the DMA command in response to the flow control signal. In one embodiment, a context manager includes: allocation logic configured to arbitrate between allocation requests from virtual channels and to allocate physical channels to selected virtual channels; and routing logic configured to route a flow control signal from the selected virtual channel to the allocated physical channel, and to route a status signal between the allocated physical channel and the selected virtual channel.

The invention discloses a multichannel ultrasonic transducer phased array driving method based on direct memory access. The method comprises a waveform data buffer length determination step, a data path construction step, a phase parameter calculation step, a waveform data synthesis step and a DMA driving step. An independent DMA channel is configured for each GPIO port or each group of GPIO ports corresponding to the transducer array by utilizing the DMA characteristic of a universal microcontroller, and buffer data is transmitted to the output data registers of the GPIO ports automatically and periodically by DMA hardware, so that multi-channel driving signals with accurate frequency and controllable phases are generated in parallel under the condition that CPU (Central Processing Unit) intervention is not needed. According to the invention, high-precision time sequence control comparable with an FPGA (Field Programmable Gate Array) scheme is realized with extremely low hardware cost and CPU (Central Processing Unit) resource occupation, the problem of time sequence jitter of an existing MCU (Microprogrammed Control Unit) scheme is solved, and the method has high stability, high efficiency and excellent expandability.

Examples described herein relate to a network interface device that includes: a host interface; a direct memory access (DMA) circuitry; a network interface to receive, in at least one packet, time data associated with at least one of multiple layers, wherein the multiple layers provide inputs to a collective operation associated with a large language model (LLM); and circuitry. The circuitry is to based, at least in part, on the time data associated with the multiple layers, identify a first operation of a first layer of the multiple layers as a late completing process relative to times to completion of multiple first operations of other layers and based on the first operation being identified as a late completing process, perform a remedial action to adjust at least one configuration of a first device to execute a second operation of the first layer.

A direct memory access (DMA) router including interrupt inputs, action groups and a DMA router engine. Each interrupt input is configured to receive a corresponding interrupt signal. Each action group is associated with a corresponding interrupt input and is configured with at least one DMA action, in which each DMA action is configured to select a DMA controller and a corresponding channel. The DMA router is configured to initiate a transfer using a selected channel of a selected DMA controller for at least one DMA action listed in an action group associated with a corresponding interrupt input triggered by assertion of a corresponding interrupt signal. The DMA actions may indicate dependencies, such that the DMA router may initiate a second DMA action only after completion of a first DMA action within the same action group based upon the indicated dependency.

A system receives, by a network interface card (NIC), inputs including an instruction to read or write a payload of a message, a tracker state indicating a round of processing, and a datatype descriptor defining organization of the message payload. The system identifies a current context and a processing state for the instruction. If the datatype descriptor indicates a first type, the system: obtains the current context associated with the first type from a host memory or a cache of the NIC; and creates direct memory access (DMA) instructions corresponding to the received instruction by executing operations in a nested loop. If the datatype descriptor indicates a second type, the system: obtains the current context associated with the second type by fetching vector entries from a buffer of the NIC; and creates the DMA instructions corresponding to the received instruction based on addresses and lengths in the vector entries.

The embodiment of the invention provides a big data storage optimization method based on a zero-copy collaboration technology and related equipment, and belongs to the technical field of big data storage. The method comprises a zero-copy data transmission module used for directly writing a data stream into a front-end buffer area of an annular structure through a direct memory access technology, and adopting a zero-copy algorithm based on pointer offset to parallelly separate data of each channel in a multi-thread environment; the intelligent data reduction module is used for deleting duplicated data from the data and then compressing the duplicated data; and the hybrid storage management module is used for managing the hybrid partition storage architecture and dynamically adjusting the distribution of the data in the hybrid partition storage architecture according to the data access mode. The CPU copy frequency is reduced through the zero copy technology, the data transmission efficiency is remarkably improved by combining the data reduction and intelligent layering strategies, the occupied storage space is reduced, and meanwhile the data safety and compliance are guaranteed.

The invention discloses a low-delay hardware implementation method and device for communication between CPUs, and relates to the technical field of computers. The method comprises the following steps: receiving initialization configuration information from a sending CPU (Central Processing Unit), including an initial address and a space size of a memory of the sending CPU and an initial address and a space size of a memory of a receiving CPU; and monitoring a sending tail pointer updated by the sending CPU, and determining whether to read the to-be-sent data from the internal memory of the sending CPU to the internal cache of the hardware communication module based on the initialization configuration information, the sending tail pointer and a sending head pointer maintained by the hardware communication module. And monitoring a receiving head pointer updated by the receiving CPU, and determining whether to write the to-be-written data in the internal cache into the memory of the receiving CPU based on the initialization configuration information, the receiving head pointer and a receiving tail pointer maintained by the hardware communication module. And the hardware communication module transmits data between the sending CPU memory and the receiving CPU memory in a direct memory access mode.

The present invention relates to a system (101) and method for primary storage write traffic management, which can improve the overall system on chip (SoC) data traffic efficiency between the processor (103), direct memory access (DMA) channel (111) and the main memory (113), by minimizing the latency to write the data to the main memory (113). This is done by reducing the number of writes from the processor (103) to the main memory (113) without sacrificing data consistency between the processor (103) and the DMA channel (111).

A system includes a component configured to send data in a first data format. The system includes a direct memory access (DMA) engine configured to receive the data in the first data format and convert the first data format to a second data format, wherein the second data format is associated with a data format of a machine learning (ML) hardware, wherein the second data format is different from the first data format. The ML hardware is configured to receive the data in the second format and perform at least one ML operation on the received data in the second format. The received data in the second data format is stored on an on-chip memory (OCM) of the ML hardware.

A DMA controller iteratively loads regions of tensor data from global memory to a shared memory of a processor to generate an output from matrix multiplication in a format in which rows of data are contiguous in memory. In a first iteration, the DMA controller loads a first region of data that includes a plurality of rows, each row separated by a tile stride from the preceding row, from the tile to a first contiguous region of the shared memory. In a second iteration, the DMA controller loads a second region of data that includes a plurality of rows, each row separated by a tile stride from the preceding row, from the tile to a second contiguous region of the shared memory. The second region of data is offset from the first region of data in global memory by a configurable offset.

In various examples, systems and methods are disclosed that relate to linking and performing direct memory access (DMA) transfers. In one example, an accelerator can generate data associated with a descriptor that represents multiple DMA transfers associated with a plurality of DMA transfer types. The accelerator can provide the data associated with the descriptor to a device (or group of devices) involved in performing the DMA transfers as a set of linked DMA transfers. In response to receiving the data associated with the descriptor, the device(s) that receive the data associated with the descriptor can be configured to perform DMA transfers and allow for movement of the data specified by the descriptor to be moved from source memory to destination memory.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.

The invention discloses a solid state disk-based data transmission method and device, a medium and a product, and relates to the field of solid state disks. According to the method, a data layout description header is obtained from a host memory in a direct memory access mode according to a target memory initial address; analyzing the data layout description header through a flash translation layer of the solid state disk, identifying each data segment entry, and extracting length information and life cycle attribute tags of corresponding data segments from each data segment entry; based on the life cycle attribute tag, planning a corresponding physical flash memory page for each data segment as a target write address of the data segment; and based on the target write-in address, controlling the solid state disk to execute DMA operation segment by segment according to the sequence of data segment entries in the data layout description head until the write-in of the total data length is completed. By implementing the technical scheme provided by the invention, the data storage efficiency of the solid state disk is improved.

A data processing method, apparatus and system based on a para-virtualization device are provided. The method comprises: acquiring a plurality of pieces of initial data which are stored in a completion queue of a para-virtualization device, wherein the plurality of pieces of initial data are used for representing description information of original data which has been processed by the para-virtualization device, but has not been submitted to a host; determining a plurality of pieces of first data, which meet a preset condition, among the plurality of pieces of initial data; performing an aggregation operation on the plurality of pieces of first data, so as to generate a first aggregation result; and sending to a memory of the host a direct memory access request that carries the first aggregation result.

The invention discloses a log management method, device and equipment and a storage medium, is applied to solid state disk equipment, and relates to the technical field of computers, and the log management method comprises the steps that in the power-on initialization process, host memory demand information is reported to a host, so that the host returns a cache allocation result based on the host memory demand information; when a log export instruction sent by a host is received through a local out-of-band command processing component, determining a to-be-exported log and a segmented loop export strategy in combination with a local flash memory; completing a log export operation by using a segmented loop export strategy, the to-be-exported log, the cache allocation result and a local preset direct memory access engine to obtain instruction completion information; and feeding back instruction completion information to the host, so that the host reads the log in the local memory based on the instruction completion information to trigger log processing operation. According to the log exporting method and device, the problems existing in existing related schemes can be effectively solved, and therefore log exporting is efficiently, stably and reliably achieved.

An integrated circuit (IC) device includes a functional circuit and a distributed management circuit that includes a plurality of configuration interface manager (CIM) circuits that receive respective programming partitions as configuration packets over a first communication channel (e.g., a network-on-chip or NoC), the configuration packets being configured to communicate with the functional circuit. And performing management operations on the respective regions of the functional circuit in parallel with each other based on the respective configuration packets, the management operations including providing configuration parameters to the respective regions of the functional circuit. The configuration packets may be streamed from the central manager to the CIM circuitry and / or read by a direct memory access (DMA) engine of the CIM circuitry. The central manager may configure the CIM circuitry and the NoC over a second communication channel (e.g., a global communication ring interconnect) during the initialization phase. The CIM circuitry may include respective packet processors, random access memories, authentication circuitry, error detection circuitry, and interconnect circuitry having a standardized bus width.

An example system-on-chip (SoC) device for a communication system includes a peripheral component interconnect express (PCIe) interface configured to receive data from a backhaul field programmable gate array (FPGA) of the communication system, and a producer port linked with a consumer port through direct memory access (DMA). Data received by the PCIe interface is assigned to the producer port. The device includes dual hardware media access controls (MACs) configured to consume the data assigned to the producer port, and at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz.

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

This application provides a memory management apparatus and method for an intelligent processor. The memory management apparatus includes a prefetch circuit, a setting circuit, and a mapping circuit. The prefetch circuit obtains raw data via a direct memory access circuit. The raw data indicates a mapping relationship between a first virtual address and a plurality of physical addresses of a memory. The setting circuit parses the raw data to sequentially map each of the physical addresses to a plurality of second virtual addresses including the first virtual address and issues a write request. The mapping circuit stores the mapping relationship between each physical address and the corresponding second virtual address as a first mapping table according to the write request, and accesses the memory using the first mapping table according to at least one read request corresponding to at least one channel of the direct memory access circuit.

The application relates to the technical field of power equipment state monitoring, and discloses an SF6 density monitoring system with multi-element data communication, which comprises an electric energy management module, a super capacitor, an acquisition module, a zero-crossing detection circuit, a communication module, a switching circuit and a microcontroller. The zero-crossing detection circuit is connected to a secondary voltage signal loop of a power grid and captures a phase zero-crossing point; the microcontroller synchronously reads temperature and pressure parameters in response to the zero-crossing point signal, so as to suppress power frequency transient interference. The microcontroller compensates the pressure by using the temperature parameter and calculates a change slope, and executes joint determination in combination with the terminal voltage of the super capacitor. The microcontroller controls the switching circuit to be turned on to supply power for the communication module, and uses a direct memory access controller to concurrently transmit data messages to the communication module for sending. The application improves the anti-interference capability of bottom-layer data sampling, eliminates leakage false alarms caused by environmental temperature fluctuation, and effectively reduces the overall operation power consumption of the system.

A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.