878 results about "Direct memory access" patented technology

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

The invention discloses an address mapping method in DPU local storage virtualization, which comprises the following steps: a virtual machine calls a system call interface provided by an address mapping configuration management module on a host side to perform mapping configuration of a virtual machine physical address and a host physical address, and issues the virtual machine physical address and length to a virtual address mapping module of a DPU; the virtual address mapping module manages global direct memory access address resources, firstly allocates a global direct memory access address on a host side, then maps a virtual machine physical address to the allocated global direct memory access address in a mapping page table of the DPU, and returns the virtual machine physical address to the address mapping configuration management module; and the address mapping configuration management module obtains the distributed global direct memory access address, and maps the distributed global direct memory access address to a host physical address in the IOMMU. According to the method, by optimizing address mapping, the efficient and flexible local storage virtualization service can be realized while the data reliability is ensured.

The invention relates to the technical field of network communication, and discloses a vehicle-mounted edge computing data recording system and method based on protocol adaptive analysis, and the system comprises a multi-protocol network access controller which is used for capturing an original data frame and extracting a physical feature triple; the identification analysis engine is used for executing hash operation on the triple to generate a physical feature code and retrieving a physical logic address mapping table; the direct memory access controller is used for responding to a target memory address pointer hit by retrieval and directly writing a data load into an input buffer area of the functional operation module, and by constructing a direct addressing mechanism based on Hash mapping, thorough decoupling of vehicle-mounted heterogeneous network physical topology and edge computing logic is achieved.

One aspect of the instant disclosure may provide a system and method for processing scatter-gather direct memory access (S-G DMA) instructions. During operation, the system may receive an S-G DMA instruction associated with a message and gather instruction context for the S-G DMA instruction. An S-G DMA processor may process the S-G DMA instruction based on the gathered instruction context and determine whether there exists a pending S-G DMA instruction associated with the message. In response to the presence of the pending S-G DMA instruction, the system stores the instruction context in a hot context cache at an address corresponding to the pending S-G DMA instruction. In response to the absence of the pending S-G DMA instruction, the system stores the instruction context in a cold context cache.

Examples described herein include one or more processors; a network interface; and a direct memory access (DMA) engine communicatively coupled to the one or more processors. In some examples, the DMA engine is to receive a DMA data access request and based on an address in the DMA data access request corresponding to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device. In some examples, if the source address corresponds to a local memory device and the destination address corresponds to a remote memory device, the DMA engine is to cause the network interface to generate at least one packet for transmission to the remote memory device.

The invention discloses an accelerator for accelerating the reasoning process of an unstructured sparse large language model and an operation method of the accelerator. The accelerator comprises a processor module, a direct memory access module, a memory controller module, a DDR memory module, an interconnection bus module, a calculation core module and a router module. The interconnection bus module is connected with the direct memory access module, the memory controller module and the computing core module; the processor module is connected with the direct memory access module; the DDR memory module is connected with the memory controller module; the router module is connected with the computing core module and the adjacent router module; and the calculation core module obtains to-be-calculated data from the off-chip DDR memory module through the interconnection bus module. According to the method, the limit that data reuse is carried out only along a single row or a single column on a traditional systolic array is broken through, cross-row and cross-column data reuse is achieved, the pressure of hardware equipment is relieved, the positions of non-zero elements are coded through bit masks, and the calculation efficiency is improved.

The invention belongs to the technical field of data transmission and processing, and discloses a zero-copy-based multi-thread high-throughput data stream channel separation method and system, and the method comprises the steps: directly writing a mixed data stream into a front-end buffer region configured as an annular structure through a data receiving module by adopting direct memory access; then, a multi-thread processing module dynamically allocates a plurality of processing threads from a thread pool to separate channel data in parallel, each thread adopts a zero copy algorithm based on pointer offset, positions the channel data in a memory, creates pointer reference and associates the channel data to a corresponding rear-end buffer area, and logic separation is achieved without physical copy; and finally, the data storage module efficiently writes the separated data into persistent storage in an asynchronous I / O mode. According to the method, zero-copy, multi-thread parallel and two-stage dynamic buffering strategies are combined, the data separation efficiency is remarkably improved, CPU occupation and memory bandwidth are greatly reduced, and the real-time performance and stability of high-throughput data processing are guaranteed.

The invention discloses a data transmission method and device, equipment and a medium, and relates to the technical field of computers. By adopting a redundancy architecture of multiple direct memory access channels and combining a channel transmission mode based on a trigger condition and a target screening strategy, the data transmission efficiency is improved. The appropriate target direct memory access channel is selected from the multiple direct memory access channels to execute the data transmission task, so that when a certain direct memory access channel has an error, the system can be automatically switched to other direct memory access channels to continue to execute the data transmission task; overall interruption of the non-transparent bridge link caused by a single direct memory access channel fault is avoided, meanwhile, for the direct memory access fault, the fault channel can be accurately repaired by adopting a fault-level-based hierarchical repair strategy, the whole non-transparent bridge link and all devices do not need to be reinitialized, and the fault channel repair efficiency is improved. The fault processing time is greatly shortened, the fault recovery efficiency is effectively improved, and the continuity of cross-storage node data transmission is guaranteed.

The invention provides a data interaction method and device based on a shared memory, virtual electronic equipment and a storage medium, and the method comprises the steps: responding to a detected packet sending request of a first application for a first protocol stack of first virtual network equipment, and calling a first packet sending function; encapsulating the to-be-sent data into a first data packet based on the first packet sending function; obtaining a storage address of the first data packet, and mapping the storage address in a mode of directly accessing a mapping interface by a memory to obtain a mapped physical address; and filling the physical address into a corresponding position of the descriptor of the first virtual network equipment, and updating the position of a tail pointer of the descriptor. The RC and the EP are registered as the virtual network card through the network driving technology, so that the communication function can be realized through the PCIE slot and by means of the PCIE connecting line, data message transmission can be realized without the aid of peripheral equipment such as the network card, the stability of data transmission is improved, and the configuration cost of hardware is saved.

The invention provides a memory resource access method and device, an address translation method and device, electronic equipment and a storage medium. According to the embodiment of the invention, a virtual machine management component can be used for firstly obtaining a direct memory access request of external equipment to a memory resource mounted under a virtual machine; and searching a target physical address corresponding to the target virtual address of the target memory resource from the data processing unit, so that the external equipment accesses the target memory resource by accessing the target physical address. Wherein a physical address translated by the virtual machine management component for the virtual address of the memory resource in advance is stored in the data processing unit, and the data processing unit performs data communication with the virtual machine management component through a communication drive simulated in the virtual machine management component. By adopting the scheme, the congestion of the shared memory resource (IOTLB) of the memory management unit possibly caused by excessive address query can be avoided, the consumption of the shared memory resource is reduced, and the utilization rate of the shared memory resource is improved.

Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.

The invention provides a memory resource management method and electronic equipment, relates to the technical field of electronics, and is used for reducing memory resource waste caused by memory occupied by an application running in a background. The method is applied to the electronic equipment, a target application is installed in the electronic equipment, and the electronic equipment comprises a memory, a graphics processing unit (GPU) driver and a direct memory access cache (DMABUF) driver. The method comprises the following steps: in response to a first operation of switching a target application from a foreground to a background, obtaining an initial preset memory page applied by the target application from a memory; wherein the initial preset memory page comprises a memory page applied by the target application through the GPU driver and / or the DMABUF driver. And compressing the initial preset memory page to obtain a compressed preset memory page, and storing the compressed preset memory page to a virtual disk of the memory. And releasing the initial preset memory page in the memory.

The invention discloses a communication method and system of a computer system, equipment, a product and a storage medium, relates to the field of computers, and aims to solve the problem that a single-channel architecture can become a bottleneck of system performance, the method comprises the following steps: identifying a plurality of direct memory access controllers and a plurality of non-transparent bridging equipment in a first computer system; determining a current target non-transparent bridging device corresponding to each direct memory access controller in the plurality of non-transparent bridging devices; and for each direct memory access controller, carrying out binding operation on the direct memory access controller and the corresponding current target non-transparent bridging equipment, so that the direct memory access controller accesses the second computer system through the corresponding current target non-transparent bridging equipment. According to the invention, the data transmission load can be dispersed to a plurality of communication links, and all data are prevented from being transmitted through the same communication link, so that the throughput of the system is improved, the possibility of bottleneck is reduced, and the data processing capability and performance of the whole system are improved.

Mechanisms for unordered input / output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input / output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input / output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input / output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input / output direct memory access operation request is for a write operation.

The invention relates to the technical field of industrial communication networks, in particular to a method for quickly forwarding messages from a PCIE (Peripheral Component Interface Express) interface to a WIA (Wireless Interface Architecture) interface, which comprises the following steps of: simultaneously receiving PCIE messages and WIA-FA protocol messages through a hardware logic circuit; analyzing the message in a data link layer to obtain an analysis result comprising data load and address information; packaging the analysis result according to a pre-configuration rule to generate a data frame conforming to a target protocol; and constructing a sending descriptor for the generated data frame, and sending the data frame from a corresponding interface through a direct memory access mechanism. According to the method, parallel analysis and protocol conversion of messages are achieved through a hardware logic circuit, fast address conversion is achieved through a pre-configured address mapping table, and zero-copy data transmission is achieved through a direct memory access mechanism. According to the invention, software protocol stack processing is replaced by a hardware processing flow, so that communication delay and CPU resource consumption are effectively reduced.

The embodiment of the invention provides a data transmission method and device and a storage medium. In the embodiment of the invention, a new direct memory access interface is provided, in implementation, an agent module is provided for network card equipment, and a task management queue and a memory management queue are provided between the agent module and an application as a direct memory access channel between the agent module and the application; in the data transmission process of the two ends, on one hand, the two ends can adopt a bypass kernel and zero copy technology to improve the data transmission efficiency based on the respective task management queues, and on the other hand, the two ends actively implement memory management for data storage based on the respective memory management queues, and interaction of memory management with the opposite end is not needed; the interactive operation of the two ends in the data transmission process can be reduced, and the transmission delay can be further reduced on the basis of achieving direct memory access.

Techniques to reduce direct memory access (DMA) overhead may include retrieving an address translation descriptor from a descriptor queue of a DMA engine, and updating an address translation table in the DMA engine with address translation information obtained from the location indicated by the address translation descriptor. A set of memory descriptors is then obtained from the descriptor queue. The set of memory descriptors can be processed by determining that the addresses in the set of memory descriptors are to be translated using the address translation table, and performing memory access operations by using the address translation table to translate the addresses in the set of memory descriptors.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

A power converter controlled by a micro-controller unit (MCU) is effectively synchronized by using a signal received by a hardware subsystem of the MCU. The synchronization signal can control multiple power converters and can be generated by one power converter or a synchronization controller with generation of the synchronization signal generated using a hardware subsystem of an MCU, namely a hardware timer. The timer can be used to obtain a switch state from a memory table using direct memory access (DMA).

The invention provides a sparse approximate inverse Shenwei parallel preprocessing method and system for electromagnetic scattering, and relates to the technical field of processor parallel computing, and the method comprises the steps: carrying out the performance hotspot analysis of a sparse approximate inverse preprocessor in an electromagnetic scattering simulation process, and determining a hotspot function of the sparse approximate inverse preprocessor; extracting a sparse matrix vector multiplication operation of a hotspot function, performing master-slave core parallel calculation on the sparse matrix vector multiplication operation, migrating the sparse matrix vector multiplication operation to slave core calculation, and accelerating hotspot calculation by using a heterogeneous parallel sparse approximate inverse algorithm; parallel computing of master-slave core intensive numerical computing tasks is achieved; in the parallel computing process, the slave cores communicate with the master core in a direct memory access mode, and during the period, the master core is in a waiting state to ensure data consistency and communication synchronization until all the slave cores compute distributed tasks.

The invention relates to a video acquisition and transmission method and device for converting a 10-gigabit network into a PCIe (Peripheral Component Interconnect Express) interface. The method comprises the following steps: receiving a video stream through a double 10-gigabit network optical module, carrying out protocol analysis and preprocessing through an FPGA (Field Programmable Gate Array), realizing multi-path alternate reading and writing by utilizing DDR3 ping-pong cache, dynamically distributing the video stream to multiple devices through a three-path PCIe 3.0 * 4 interface and an XDMA (Extensible Direct Memory Access), and optimizing the transmission priority in combination with a load state. The device comprises two paths of SFP + optical modules, a Xilinx Virtex7 series FPGA chip (integrated with a 10-gigabit network MAC, a PCIe XDMA IP core and a DDR3 controller), three paths of PCIe 3.0 * 4 interfaces and an external DDR3 memory. The system has the advantages that the double 10-gigabit network input and multi-PCIe channel collaborative architecture breaks through the single-channel bandwidth bottleneck; the intelligent ping-pong cache and the AXI arbitration strategy reduce the data conflict risk; and dynamic bandwidth allocation optimizes real-time performance.

The present application discloses a method and apparatus for direct memory access (DMA) between accelerator cards, and an accelerator card, an acceleration platform and a nonvolatile readable storage medium in the technical field of computers. According to the present application, a first accelerator card can actively initiate DMA, directly writes data into a memory of a second accelerator card in a DMA mode on the basis of idle memory information of the second accelerator card of a data destination end recorded in the first accelerator card, without inquiring an idle memory address of the second accelerator card before DMA, and without waiting for the second accelerator card to initiate DMA. The scheme realizes a direct DMA write operation of different accelerator cards in a hardware level, and solves the problem of DMA operation between accelerator cards.

The invention provides an efficient regional ocean forecasting method, and belongs to the technical field of ocean forecasting. A regional ocean mode four-dimensional variational assimilation system is constructed, and an adjoint mode calculation framework is established; after calculation modules are grouped according to dependency dimensions, a slave core parallel scheme is designed, and data transmission and calculation assembly line overlapping are realized by adopting a direct memory access step access and double-buffering technology; introducing a multi-scale time step adaptive integral algorithm and a gradient convergence acceleration model, predicting an optimal convergence path according to a historical iteration trajectory, dynamically adjusting a search direction and a step factor, completing four-dimensional variation assimilation, outputting an optimized ocean initial field, and performing forward integral forecasting to generate ocean state field variable forecasting data; the technical problem of insufficient timeliness of regional ocean forecasting caused by low calculation efficiency of the adjoint mode is solved.

The invention relates to a naked eye 3D binocular image acquisition and real-time processing system based on hardware synchronous triggering, and belongs to the technical field of image processing and three-dimensional display. According to the system, a hardware synchronous triggering mechanism is adopted, a time sequence synchronous control unit is used for sending a synchronous pulse signal to a binocular image sensor, and strict synchronization of left and right viewpoint image acquisition is ensured. The image signal processing unit processes collected original data, the stereo parallax correction module performs epipolar correction, and the sub-pixel interleaving module generates a composite view frame according to grating parameters of the display terminal. The system realizes high-speed data transmission through a double-buffer direct memory access DMA mechanism. The problems of visual tearing and weak stereoscopic impression caused by asynchronous binocular image acquisition in the prior art are solved, nanosecond-level synchronization precision is realized, optical crosstalk is reduced, and smoothness and comfort of stereoscopic display are ensured.

Techniques are described to perform hierarchical collective compute operations on a plurality of processing nodes for a distributed computation of a neural network. Each processing node can include a plurality of processing ranks that are assigned corresponding rank identifiers (IDs). The hierarchical collective compute operation can include direct memory access (DMA) transfers to perform an inter-node collective compute operation of non-contiguous memory regions across the processing nodes based on the rank IDs, and an intra-node collective compute operation of non-contiguous memory regions within each of the processing nodes based on the rank IDs.

The embodiment of the invention provides a data transmission method and device, a storage medium and electronic equipment, and relates to the field of computers, the data transmission method is applied to a first system on chip in a plurality of systems on chip in a computing platform, and the plurality of systems on chip further comprise a second system on chip. Comprising the steps that under the condition that target data is about to be sent to the second system-on-chip, the target data is stored in a target direct memory access memory in the computing platform, and the target direct memory access memory is a direct memory access memory corresponding to the first system-on-chip and the second system-on-chip; and sending a notification message to the second system-on-chip based on an Ethernet communication link between the first system-on-chip and the second system-on-chip, the notification message being used for indicating the second system-on-chip to acquire the target data from the target direct memory access memory.

Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOM MU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

The invention discloses a data scheduling and control method based on mainboard memory straight-through, and relates to the technical field of computer hardware, the method comprises the following steps: pre-allocating a straight-through memory area for mounting equipment in a firmware initialization stage, establishing a mapping relation between equipment identification and a physical address of an exclusive memory segment, and through address translation and access control rules of a firmware layer, the device bypasses a system cache level and accesses the exclusive memory segment in a direct memory access mode. Constructing a firmware scheduling table based on the mapping relation to manage access requests of all devices, monitoring transmission delay in real time, and dynamically adjusting priority weight and bandwidth allocation in the scheduling table according to a monitoring result; and sequencing the requests according to the updated scheduling table to complete scheduling and control of the memory access behavior of the equipment. According to the method and the device, the delay bottleneck caused by multi-level copying and firmware scheduling lag in mainboard data forwarding is effectively solved.

Adaptive system probe action to minimize input / output dirty data transfers is described. In one or more implementations, a system includes a processor, a memory configured to store data, and a cache configured to store a portion of the data stored in the memory for execution by the processor. The system also includes a cache coherence controller including a cache line history. The cache coherence controller is configured detect a direct memory access request from an input / output device. The direct memory access request is associated with an input / output operation involving the data. The cache coherence controller is further configured to identify a cache line associated with the direct memory access request, and, in response to the cache line history including a dirty data transfer record corresponding to the cache line, selectively send a probe to the cache based on a state of the cache line.