1462 results about "Input/output" patented technology

A value chain network control tower system comprises a processor and memory configured to execute a know your model system that manages the complete lifecycle of Al models in enterprise environments. The know your model system performs model intake and registration actions including model documentation collection, registration procedures, metadata collection, input / output interface standardization, legal and licensing validation checks, and security validation. The system conducts comprehensive model evaluation and risk assessment actions by analyzing foundational properties, task performance, safety and risk management, alignment and compliance characteristics, operational metrics, and tooling transparency capabilities. The know your model system executes model deployment actions through automated environment validation, predeployment approval processes, and controlled production deployment with continuous monitoring.

The invention relates to the technical field of storage control, in particular to a memory control method, which comprises the following steps: acquiring a target logic address in response to a reading request from a host system; determining a data access mode associated with the target logic address in real time based on the historical access information, wherein the data access mode at least comprises a continuous mode, a random mode and a hotspot mode; according to the determined data access mode, triggering a data prefetching strategy and a flash translation layer query strategy matched with the access mode; obtaining target data from a memory module based on a data prefetching strategy and a flash translation layer query strategy; and scheduling the cache resources and the input / output bandwidth according to a predetermined resource management strategy, and returning the target data to the host system. The prefetching accuracy and the cache utilization rate are improved.

The invention discloses a coupling iterative algorithm library and a reactor multi-physical field coupling calculation program construction method. The coupling iterative algorithm library comprises an open source library layer used for integrating a plurality of numerical calculation libraries and providing an input / output interface for a reactor multi-physics field coupling framework and each numerical calculation library; the core algorithm layer is used for integrating a plurality of coupling iteration algorithms and a plurality of acceleration algorithms related to each coupling iteration algorithm; the interface layer is used for providing a data interaction interface between a nuclear reactor multi-physics field coupling calculation program and the core algorithm layer; and the iterative algorithm template layer is used for forming an iterative solution process control template function based on the open source library layer, the core algorithm layer and the interface layer, and the iterative solution process control template function is used for constructing a nuclear reactor multi-physics field coupling calculation program based on the process control parameters set in the input file. According to the coupling iterative algorithm library, the development efficiency and the development quality of a nuclear reactor multi-physics field coupling calculation program can be improved.

The invention relates to the technical field of distributed computing and computing power scheduling, in particular to a computing power resource fusion method based on a distributed flow pipeline, which comprises the following steps of: disassembling a user computing power request into a flow pipeline unit for packaging computing logic, an input / output interface and a resource demand label; meanwhile, computing power types, real-time load rates, memory occupancy rates, network round-trip delays, geographic positioning and energy consumption data of cloud edge end nodes are collected, a hierarchical topology network framework is constructed based on the collected data, node computing power available values are calculated, an inter-node transmission cost matrix is generated, a fault probability prediction model is constructed, and a fault probability prediction model is constructed. And finally, analyzing a data dependency relationship of the pipeline unit through a four-dimensional joint decision engine, executing dynamic mapping, and preferentially mapping the high-computing-power demand unit to a GPU cluster node, so as to realize non-interruption reconstruction during pipeline topology operation. And the global computing power resource utilization rate, the task operation efficiency and the service stability are improved.

The present disclosure provides a computer-implemented system for automated augmentation of differential equation models. The system stores differential equations representing mechanistic behavior of physical or computational processes and constructs a hybrid computational solver by embedding a trainable universal approximator with adjustable parameters into the differential equations, where approximator outputs augment time derivatives during numerical integration. An iterative training process adjusts parameters through numerical integration, monitors integration failures, assigns infinite penalty values to loss functions when failures occur, and computes gradients using automatic differentiation otherwise. The system computes sensitivity metrics via Jacobian matrix evaluation, classifies input / output subsets as significant based on threshold-exceeding sensitivity metrics, generates a reduced approximator operating on classified subsets, and replaces the universal approximator with the reduced version to create an optimized solver.

The embodiment of the invention discloses an internal memory, a chip and related electronic equipment. A target computing unit of the internal memory comprises a plurality of groups of primary multipliers, a plurality of adder trees and a plurality of secondary multipliers, one group of first-level multipliers is connected with one second-level multiplier through one adder tree; the group of first-level multipliers comprises a plurality of pairs of first multipliers, and each adder tree comprises a first adder, a second adder and a third adder; each pair of first multipliers respectively receive data to perform multiplication operation, and respectively input output results into the first adder to perform addition operation; each second adder receives the output results of the plurality of first adders or the second adder at the upper level to carry out addition operation, and respectively inputs the output results to the second adder at the lower level or the third adder; and each third adder receives the output results of the plurality of second adders to carry out addition operation, and inputs the output results to the secondary multiplier to carry out multiplication operation. By implementing the embodiment of the invention, the memory computing capability can be improved.

The invention discloses a POL power supply automatic test method based on modular design, and belongs to the technical field of power supply test. The method comprises the following steps: firstly, under the control of an upper computer, automatically reading POL power supply basic parameters including key characteristic parameters such as input / output voltage, rated current and frequency from a preset Excel table, and establishing a judgment reference for testing; then, instrument initialization is completed, communication connection with test equipment such as an oscilloscope, an electronic load and a direct-current power supply is established, and configuration of initialization function parameters is completed; then, executing a measurement task of each core parameter of the POL power supply to be tested, and in the test process, executing a parallel measurement management mechanism, namely configuring each instrument parameter and channel state in real time according to a specific test item, and triggering a retry or interrupt logic under the conditions of communication abnormality, data timeout and the like until the test recovers a running state; and finally, after the test is completed, performing Excel storage and interaction on the standardized test data and the waveform screenshot, and finally safely exiting. According to the POL power supply automatic test method based on the modular design, the whole test process is divided into a plurality of serial or parallel function processing units such as parameter reading, instrument initialization, test execution and test management, data storage and interaction and the like, and high efficiency and usability of a test system are achieved.

A power consumption prediction and management method and system based on a solid state disk, a medium and a product relate to the field of solid state disks. The method comprises the following steps: predicting the workload intensity of a host in a first preset time window based on an I / O (Input / Output) instruction stream to obtain an expected host workload curve, and determining an expected host idle time period; calculating an expected host power consumption value in the expected host idle time period; extracting internal state parameters of the solid state disk according to the historical operation log data; establishing a background task triggering probability model, and calculating the triggering probability of starting the high-power-consumption background task by the solid state disk in a first preset time window; performing power consumption conflict judgment according to the expected host power consumption value and the triggering probability, and generating a comprehensive predicted power consumption value; and based on the comprehensive predicted power consumption value, determining an optimal target power consumption state, and instructing the solid state disk to be switched to the optimal target power consumption state. By implementing the technical scheme provided by the invention, the stability of state switching of the solid state disk is improved.

The invention discloses a broadband low-power-consumption receiving and transmitting shared phase shifter which comprises a differential signal common port, a frequency sampling and control circuit, a dual-mode orthogonal generation circuit and a passive vector modulation synthesis circuit. The differential signal common port comprises a common input / output port interface of RF + and RF-differential radio frequency signals; the frequency sampling and control circuit is composed of a frequency sampling circuit, a frequency detection circuit and a logic control unit. The dual-mode orthogonal generation circuit is composed of a frequency selection change-over switch, a multi-phase filter, a coupling transformer, a matching network 1 and a matching network 2. The passive vector modulation synthesis circuit is composed of two passive vector modulation arrays and two combining / power dividing circuits.

Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input / output (I / O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input / output lines and many arrays of memory cells. Each array of memory cells can include respective local input / output (LIO) lines coupled to a global input / output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input / output lines to the logic device.

The present invention relates to the technical field of text layout. Disclosed are a text format adjustment method and system based on large language model code generation. The method comprises: constructing an API vector knowledge base on the basis of a development document of target software, the API vector knowledge base comprising vector representations of text format adjustment attributes and knowledge snippets of the text format adjustment attributes; acquiring a user format adjustment requirement; vectorizing the user format adjustment requirement, and by matching a vector representation of the user format adjustment requirement with the vector representations of the text format adjustment attributes, obtaining the knowledge snippet and an input / output example of the corresponding text format adjustment attribute; and embedding the user format adjustment requirement and the knowledge snippet and input / output example of the corresponding text format adjustment attribute into a code generation prompt word template, and generating a text format adjustment result on the basis of a large language model. The present invention can reduce the workload of developing and designing text format templates, and can more flexibly accommodate various format requirements.

The invention provides a PXE network card initialization method and device compatible with 64-bit addressing and a medium, and relates to the technical field of network card initialization, and the method comprises the steps: discovering a network card device; reading a PCI configuration space of the network card equipment, obtaining information of an extended ROM base address register, and mapping a network card Option ROM to a memory shadow region; when the access of the memory mapping input and output mode fails, the initialization code performs read-write operation on the hardware register through a self-defined capability structure in a PCI configuration space of the network card equipment; based on the successfully accessed hardware register, network card hardware initialization is completed, and a PXE protocol stack structural body is established in a memory; registering system firmware as PXE starting equipment, and entering a protocol interaction stage with a PXE server; according to the invention, smooth development of a subsequent network boot flow is guaranteed, and the deployment success rate and the system stability in a large-scale batch installation scene are improved.

The invention relates to the technical field of computers, and belongs to a BIOS (Basic Input / Output System) and BMC (Baseboard Management Controller)-based GPU (Graphics Processing Unit) resource intelligent dynamic optimization method and system. A four-layer collaborative architecture of a firmware layer (BIOS), a management controller layer (BMC), a system layer (operating system kernel) and a hardware layer (GPU equipment) is adopted, and the architecture is a cross-layer closed-loop optimization architecture. An optimization decision function is decoupled from an operating system kernel and is deployed in an independent hardware management unit, namely a baseboard management controller (BMC). The system collects GPU operation data in real time through an operation system kernel space and sends the GPU operation data to a BMC; an intelligent optimization engine deployed in the BMC analyzes and calculates the data to generate an optimal GPU resource scheduling strategy; the strategy is returned to an operating system kernel and finally executed by a hardware layer, and intelligent dynamic optimization of GPU resources is achieved through cross-level interaction. Therefore, a continuous intelligent closed-loop optimization link of'deployment-data acquisition-intelligent decision-making-strategy execution 'is formed.

The invention discloses a microprocessor dynamic power consumption optimization system based on deep learning, which belongs to the technical field of microprocessor power consumption management, and comprises a working load feature extraction module, a neural network prediction module, a dynamic core distribution module and a particle size power supply management module, the working load feature extraction module extracts feature parameters of calculation intensity, memory access intensity and input and output intensity of an application program in real time through a hardware circuit; the neural network prediction module predicts future power consumption and performance requirements based on a deep reinforcement learning network; the dynamic core distribution module intelligently selects an optimal core combination; the particle size power supply management module independently executes dynamic voltage frequency regulation on each core; according to the invention, accurate power consumption optimization of the heterogeneous multi-core processor is realized through deep coupling and closed-loop cooperation of the four modules, and compared with the prior art, the energy efficiency ratio is improved by more than 40%, and the power consumption prediction error is reduced to be within 5%.

The invention discloses a source code reconstruction method and device, equipment and a medium. The method comprises the following steps: acquiring a to-be-processed source code and reconstruction performance description content; determining at least one target code snippet in the to-be-processed source code according to a code reconstruction standard; according to the to-be-processed source code, generating a calling relation and an input and output relation corresponding to the to-be-processed source code; aiming at each target code snippet, reconstructing the target code snippets according to the calling relation and the input and output relation to obtain reconstructed code snippets; and replacing the target code snippets in the to-be-processed source codes with the reconstructed code snippets, wherein the to-be-processed source codes before replacement and the to-be-processed source codes after replacement have the same functions. According to the embodiment of the invention, the source code upgrading efficiency and automation degree of the original system can be improved.

An example method may include determining whether a preemption flag associated with a first input / output (I / O) handling thread is equal to a first value indicating that preemption of the first I / O queue handling thread is forthcoming, wherein the first I / O queue handling thread is executing on a first processor, the first I / O queue handling thread is associated with a first set of one or more queue identifiers, and each queue identifier identifies a queue being handled by the first I / O queue handling thread, and, responsive to determining that the preemption flag is equal to the first value, transferring the first set of one or more queue identifiers to a second I / O queue handling thread executing on a second processor. Transferring the first set of queue identifiers may include removing the one or more queue identifiers from the first set.

The invention discloses a training method of an inference deployment configuration performance prediction model of a large language model and an inference deployment configuration recommendation method and device.The method comprises the steps that a first structural feature, a first interaction feature and throughput performance data under different structural parameters and configuration parameters of a sample model are obtained; comprising structure parameters, configuration parameters and operation resource quantization parameters of the large language model; taking the throughput performance data as a regression target, and training a regression model by using the first structural feature and the first interaction feature to obtain a reasoning deployment configuration regression model; the reasoning deployment configuration regression model is used for predicting throughput performance data of the large language model under given configuration. According to the method, systematic modeling is carried out on a complex mapping relation among a model structure, input and output characteristics, a parallel strategy, concurrent configuration and throughput performance, and the performance is accurately predicted in a data driving mode, so that optimal configuration is recommended, and efficient and reusable language model reasoning deployment optimization is realized.

Systems and methods for providing a Basic Input / Output System (BIOS) password retention system that may be used for motherboard replacement are disclosed. According to one embodiment, an Information Handling System (IHS) includes computer-executable instructions to, when a replacement motherboard is booted on the HIS, obtain An encrypted BIOS password associated with a previous motherboard that has been removed from the IHS, configure the BIOS password on the replacement motherboard without providing a clear text version of the BIOS pw, and complete booting of the IHS into a normal mode of operation.

A store and compute sub-system of a database system, wherein the store and compute sub-system includes pluralities of computing nodes of a plurality of computing device clusters, wherein a set of computing nodes of the pluralities of computing nodes is operable to implement a first input / output (IO) pipeline for a first segment of a plurality of segments of a dataset to support execution of a query, wherein, the first IO pipeline functions to convert long-term storage (LTS) data of the first segment into first query ready raw data. The set of computing nodes is further operable to implement a second IO pipeline for a second segment of the plurality of segments of the dataset to support execution of the query, wherein, the second IO pipeline functions to convert LTS data of the second segment into second query ready raw data.

The invention provides a file system management method based on pre-distribution and direct addressing and a related device, and relates to the technical field of computers. The technical problems of high access delay and high I / O (Input / Output) overhead caused by chain traversal and dynamic allocation of a traditional file system are solved by pre-allocating all index metadata at one time in a file creation stage, converting file offset by adopting a direct addressing mechanism, and implementing flattened namespace management and decoupling metadata and data operation; the method has the advantages that the file system access efficiency is improved, the I / O operation frequency is reduced, and quick addressing is realized.

A high-efficiency power electronic voltage regulating device with a reclosing function is connected in series with a low-voltage line and comprises a silicon controlled bypass switch, a series power unit, a parallel power unit, an input filtering unit, an output filtering unit, a controller, a topology change-over switch, a mechanical bypass switch, an input switch, an output switch and the like. Under a normal working condition, power is supplied to a user through the silicon controlled bypass switch; through an AI pre-judgment technology, a power grid voltage drop or increase trend is pre-judged, and a series power unit is conducted in advance; a topology change-over switch is connected to form a boost or buck topology, and when the voltage of a power grid is too low or too high, the normal voltage of a user is ensured through PR closed-loop control; when the rear-end line / load breaks down, reclosing control is carried out; and voltage upper and lower limits are adjusted remotely. The device utilizes the AI pre-judgment technology, has the characteristics of stable voltage, no need of input / output commutation and the like, solves the problems of over-high and over-low voltage and automatic reclosing in fault, and improves the high power supply quality and the power supply reliability of users.

The present application relates to a data processing method and apparatus, a server, and a storage medium. The data processing method is applied to a storage server, the storage server includes a network interface card and a solid-state drive, and the solid-state drive includes a controller memory buffer. The method includes: receiving, by the network interface card, a data operation command which is sent by a host, the data operation command carrying input / output data; sending the input / output data to the solid-state drive according to the data operation command by the network interface card; and operating on the controller memory buffer according to the input / output data by the solid-state drive. By adopting this method, data transmission may bypass the CPU of the storage server, thus reducing the consumption of CPU resources.

Systems and methods for providing a bios entitlement retention system that may be used for motherboard replacement using system devices are disclosed. According to one embodiment, an Information Handling System (IHS) includes computer-executable instructions to, when a replacement motherboard is booted for the first time, attach to a system device that stores one or more Basic Input / Output System (BIOS) entitlements associated with the IHS, configure a BIOS on the replacement motherboard using the BIOS entitlements, and complete booting of the IHS into a normal mode of operation.

A novel functional panel that is highly convenient, useful, or reliable is provided. The functional panel includes a first element, a first reflective film, and an insulating film. The first element includes a first electrode, a second electrode, and a layer containing a light-emitting material; the layer containing a light-emitting material includes a region interposed between the first electrode and the second electrode; the first electrode has a light-transmitting property; and the first electrode has a first thickness. The first electrode is interposed between a region of the first reflective film and the layer containing a light-emitting material, and the first reflective film has a second thickness. The insulating film includes a first opening portion, and the first opening portion overlaps with the first electrode. The insulating film has a first step-like cross-sectional shape, and the first step-like cross-sectional shape surrounds the first opening portion. The first step-like cross-sectional shape includes a first step, and the first step is larger than or equal to a thickness obtained by adding the second thickness to the first thickness.

Examples herein describe revocable cryptographic keys. An integrated circuit includes an input / output interface configured to receive inputs including plaintext user keys, metadata, and revocation bits. Cryptographic circuitry is configured to read a key from a first memory. Plaintext user keys are encrypted based on the key to provide encrypted user keys. Metadata is encrypted based on the key to provide encrypted metadata. Revocation bits are encrypted based on the key to provide encrypted revocation bits. A Galois / Counter Mode (GCM) tag is computed based on the key. A processor is configured to write the encrypted user keys, the encrypted metadata, the encrypted revocation bits, and the GCM tag to a second memory to provision the plaintext user keys.

The invention provides a data interaction method and a related device, and relates to the technical field of automatic control. The method comprises the following steps: receiving a first configuration parameter of a target input / output module sent by a target communication protocol master station; the data length of the configuration parameters sent by the target communication protocol master station and the address space size of the configuration object dictionary about the input / output module in the device description file based on the coupler are uniformly aligned to the target data length; determining the actual data length of the configuration parameters of the target input / output module according to a preset configuration table; and analyzing the first configuration parameter according to the actual data length of the configuration parameter of the target input / output module to obtain a second configuration parameter which can be identified by the target input / output module, and sending the second configuration parameter to the target input / output module. According to the technical scheme provided by the invention, the problem of how to realize flexible configuration of the rear-end input / output module in the prior art can be solved.

Techniques are provided for identifying anomalous portions of input / output (I / O) paths by monitoring checkpoints of I / O operations through a storage system. One method comprises obtaining checkpoint data associated with designated storage volumes in a storage system that comprises designated storage system components. The checkpoint data may be associated with multiple I / O operations that are processed by the designated storage system components and the checkpoint data for a given I / O operation may comprise checkpoint times indicating respective times that the given I / O operation is processed by a corresponding designated storage system component. A time difference between two checkpoint times may be evaluated to identify anomalous portions of an I / O path between the designated storage system components associated with the two checkpoint times. One or more automated actions may be performed related to the designated storage system components associated with the anomalous portions of the I / O path.

The invention discloses a cross-platform page code generation method based on a large model, and relates to the technical field of front-end development, and the method comprises the following steps: cooperatively analyzing a UI design drawing through a plurality of special large models, and carrying out real-time cross validation and dynamic compensation on an analysis result by adopting a multi-model mutual verification mechanism; based on a predefined standard specification, dynamic adjustment is carried out through a platform adaptation rule base; generating a page object description tree embedded with the input / output processing function; cross-platform page codes are generated through a code generation engine, and sandbox testing and automatic correction are executed; outputting a target platform code by utilizing a unified compiling engine; an adaptive optimization loop is constructed based on test feedback. According to the method, through integration of multi-model collaborative analysis, platform rule dynamic adaptation, sandbox verification and closed-loop optimization, the problems of large analysis deviation, poor cross-platform compatibility, uncontrollable code quality and the like are solved, and end-to-end high-quality automatic generation from a design drawing to multi-platform codes is realized.

Techniques are described herein for security hardened processing devices. For example, a method can include performing a secure boot of a processing device of a computer system. The processing device is configured as a root of trust for a secure boot process. The computer system can include the processing device and a non-volatile memory storing a basic input / output system (BIOS) for the secure boot process. The method can include identifying a set of programmable fuses of the processing device, deriving an encryption key using a value encoded by the set of programmable fuses in the processing device, and authenticating the BIOS to perform the secure boot process using a key derivation algorithm based on the encryption key.