312 results about "Supercomputer" patented technology

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σ_i,jC(i,j)H(i,j)—where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.

A targeted heterogeneous medium in the form of an underground layered formation is gridded into a layered structured grid or a layered semi-unstructured grid. The structured grid can be of the irregular corner-point-geometry grid type or the simple Cartesian grid type. The semi-unstructured grid is areally unstructured, formed by arbitrarily connected control-volumes derived from the dual grid of a suitable triangulation; but the connectivity pattern does not change from layer to layer. Problems with determining fluid movement and other state changes in the formation are solved by exploiting the layered structure of the medium. The techniques are particularly suited for large-scale simulation by parallel processing on a supercomputer with multiple central processing units (CPU's).

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

A method of delivering audio and audio visual works to users of computer terminals includes the steps of: providing a data warehouse of digitized works; providing program means for end user computers to access, select and play at least one of the works; providing means for controlling end user access to the works and for collecting payment for playing at least one of the works; and diverting a portion of the payment for playing the at least one work to the holder of a copyright to the at least one work. The method preferably includes the additional steps of encrypting the works; and providing the end user with program means for deciphering the works. The method still further preferably includes additional the steps of delivering advertising matter to the end user with each work the end user selects and plays; keeping a record of the particular works each end user selects and plays; customizing advertising delivered to the end user to fit within any pattern of work selection by the particular end user. An apparatus for performing the method is also provided, including a computer hive made up of several inter-linked computers having specialized functions, the computers operating in unison to build a supercomputer that has shared disk space and memory, in which each node belongs to the collective and possesses its own business rules and membership to an organization managerial hierarchy.

A fully-parallelized, highly-efficient compositional implicit hydrocarbon reservoir simulator is provided. The simulator is capable of solving giant reservoir models, of the type frequently encountered in the Middle East and elsewhere in the world, with fast turnaround time. The simulator may be implemented in a variety of computer platforms ranging from shared-memory and distributed-memory supercomputers to commercial and self-made clusters of personal computers. The performance capabilities enable analysis of reservoir models in full detail, using both fine geological characterization and detailed individual definition of the hydrocarbon components present in the reservoir fluids.

A telephone interface and voice recognition driven Internet browser system and method for accessing/browsing the Internet on a cable or satellite television includes a phone for receiving a voice signal from a user. The voice signal controls a telephone interface which displays Internet contents on the television via a cable or satellite television channel. The system also includes a voice recognizer, preferably operated on a supercomputer, for recognizing/interpreting/analyzing the voice signal and generating command signals to access/browse the Internet. The voice recognizer is capable of recognizing/interpreting/analyzing voice signals transmitted from a plurality of users in real time. The system further includes a stack of computers and an Internet browser. Each of the stack of computers is capable of accessing/browsing the Internet and retrieving/organizing requested Internet contents via the Internet browser. The requested Internet contents are sent to the user via a cable or satellite television channel.

The invention provides an ultra-scalable supercomputer based on MPU architecture in achieving the well-balanced performance of hundreds of TFLOPS or PFLOPS range in applications. The supercomputer system design includes the interconnect topology and its corresponding routing strategies, the communication subsystem design and implementation, the software and hardware schematic implementations. The supercomputer comprises a plurality of processing nodes powering the parallel processing and Axon nodes connecting computing nodes while implementing the external interconnections. The interconnect topology can be based on MPU architecture and the communication routing logic as required by switching logics is implemented in the FPGA chips while some modular designs for accelerating particular traffic patterns from applications and meliorating the communication overhead are able to be deployed as well.

A method for fabricating copper-faced electronic modules is described. These modules are mechanically robust, thermally accessible for cooling purposes, and capable of supporting high power circuits, including operation at 10 GHz and above. An imprinting method is described for patterning the copper layers of the interconnection circuit, including a variation of the imprinting method to create a special assembly layer having wells filled with solder. The flip chip assembly method comprising stud bumps inserted into wells enables unlimited rework of defective chips. The methods can be applied to multi chip modules that may be connected to other electronic systems or subsystems using feeds through the copper substrate, using a new type of module access cable, or by wireless means. The top copper plate can be replaced with a chamber containing circulating cooling fluid for aggressive cooling that may be required for servers and supercomputers. Application of these methods to create a liquid cooled supercomputer is described.

The invention discloses a low-complexity quantum circuit simulation system, and belongs to the field of quantum computing. The low-complexity quantum circuit simulation system overcomes the technicalproblems in the prior art that the quantum circuit simulation storage space is too large and the calculation time is too long. The system comprises an input module, a storage module and an output module, the storage process of the storage module for data is as follows: (1) a mathematical model is established to represent the operation of a quantum state and quantum logic gate; (2) quantum bits aregrouped and the serial numbers of the quantum bits are rearranged; (3) degree reduction is conducted on a total operation matrix U0, and an output state is calculated. According to the system, a matrix element of a quantum state vector is directly operated by using an connotative inherent law of a quantum logic gate, at the same time, the method has expandability, in the future, a supercomputer can be used to simulate a quantum computer with more bits.

Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

Estimating storm damage on a large scale includes collecting geospatial data from a plurality of sensors disparately situated in a defined geographic area; collecting the geospatial data occurs before and during a determined or simulated significant weather event. Geospatial property attribute information for each of a plurality of real property structures within the defined geographic area is also provided. A supercomputer estimates a magnitude and duration of significant weather event forces at points associated with each of the plurality of real property structures according to a significant weather event model in order to produce at least one model output data set. The model output data set is applied to the geospatial property attribute information and, based on the application of model output data, damage to the plurality of real property structures is automatically estimated.

Systems and methods that employ interactions between quantum computing systems and digital computing systems are described. For an iterative method, a quantum computing system may be designed, operated, and/or adapted to provide a rate of convergence that is greater than the rate of convergence of a digital supercomputer. When the digital supercomputer is iteratively used to evaluate an objective function at a cost incurred of C per iteration, the quantum computing system may be used to provide the input parameter(s) to the objective function and quickly converge on the input parameter(s) that optimize the objective function. Thus, a quantum computing system may be used to minimize the total cost incurred C_T for consumption of digital supercomputer resources when a digital supercomputer is iteratively employed to evaluate an objective function.

Further preferred embodiments of the present invention include methods directed to (a) Active Data Structures, (b) Mobile Devices, (c) Ad-Hoc Device Collections, and (d) Concurrent Massively Parallel Supercomputers. Therein, a distributed, object-oriented database engine utilizing independent, intelligent processing nodes as a cooperative, massively parallel system with redundancy and fault tolerance. Instead of using traditional methods of parallelism as found in most distributed databases, the invention utilizes a messaging system and a series of message processing nodes to determine where attributes and data files associated with objects are stored. The architecture is loosely coupled, each node independently determining if it manages or routes storage and retrieval requests.