37 results about "Global address space" patented technology

A plurality of private address spaces where private addresses may possibly overlap are connected with a global address space. Respective private address spaces possess VLAN-IDs as identification information for VLANs. When connecting the respective private address spaces with the Internet, a duplicate network address translating device performs, with VLAN-ID and the private address of the respective private address spaces in pairs, mutual translation between the private address and global address of the Internet. According to another aspect of the invention, a duplicate addresses-handling server is provided with a routing table which shows the relationship between virtual interfaces corresponding to VLAN-IDs and addresses of the respective private address spaces. A server portion of the duplicate addresses-handling server records, if a request is made from apparatuses of a private address space, the request and VLAN-ID, refers to, if making a response thereto, the routing table, selects a virtual interface which corresponds to the address of the response receiver, and makes a response. A virtual interface processing portion gives an applicable VLAN-ID and carries out an output to a switching hub.

An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address space processor is implemented in software to perform system functions that distinguish between local addresses and global addresses. In the preferred embodiments, the local address space has a size that is a multiple of the size of a segment of global address space. When the hardware indicates a page fault, the address space processor determines whether the address being translated is a local address or a global address. If the address is a local address, the address space processor uses a local directory to process the page fault. If the address is a global address, the address space processor uses a global directory to process the page fault. When the hardware indicates an addressing error because a computed address crosses a global segment boundary, the address space processor determines whether the address is a local address or a global address. If the address is a global address, the address space processor indicates an addressing error. If the address is a local address, the address space processor determines whether the address is within the process' local address space, and indicates an addressing error if the address is outside the process' local address space. Instructions are allowed to operate on both local and global addresses because the address space processor handles either type of address whenever software assistance is required, such as for servicing a page fault or checking a segment boundary crossing. In addition, the address space processor dynamically checks the addressing compatibility of called code before passing control to the called code.

An improved scalability runtime system for a global address space language running on a distributed or shared memory machine uses a directory of shared variables having a data structure for tracking shared variable information that is shared by a plurality of program threads. Allocation and de-allocation routines are used to allocate and de-allocate shared variable entries in the directory of shared variables. Different routines can be used to access different types of shared data. A control structure is used to control access to the shared data such that all threads can access the data at any time. Since all threads see the same objects, synchronization issues are eliminated. In addition, the improved efficiency of the data sharing allows the number of program threads to be vastly increased.

A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

A system and method of management of communication in a potentially unreliable wide-area network that contains one or more nodes connected to said network, each potentially having access to one or more inputs and/or outputs and capable of evaluating said inputs and directing said outputs, a global address space (GAS) accessible by said nodes, and a communication system using said GAS that provides communications between said nodes.

Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Transparency of resources is provided and ordering in an access is guaranteed between nodes on a computer network. In an information processing system in which a plurality of processor units are connected to each other by a switch, a global address space is introduced into which effective addresses of the processor units are mapped and which is shared by the plurality of processor units. In response to an access request packet issued by a processor unit and designating an effective address of a target node, a bridge for routing an input and output bus of a processor unit to an input and output bus of the switch converts the effective address of the target node into a global address by appending to the packet a node identification number identifying the target node, and outputs the access request packet designating the global address to the switch. After an access request packet for a write operation is output, the bridge confirms whether the write operation is completed in a target node.

The present invention provides an architecture and method for increasing the performance and resource utilization of networked storage architectures by use of hardware-based storage element mapping. The architecture utilizes a customized programmable processing element to map host read or write commands to physical storage element commands. The present invention uses a plurality of data structures, such as tables, to map host read and write commands to physical storage elements. The hardware-based storage element mapping controller uses the tables, including a mapping segment descriptor table, to map from global address space addresses to physical storage element addresses.

The invention discloses an address mapping method for large memory devices of Loongson 3A platforms, which comprises the implementation steps: 1) aiming at each CPU (central processing unit) core of a Loongson 3A processor, moving a PCI (peripheral component interconnect) memory space in a CPU address space out of an address range of a system register, and adjusting the size of the PCI memory space; 2) establishing a mapping relation between the PCI memory space being moved in the CPU address space and a memory space in a global address space, and establishing a mapping relation between the memory space in the global address space and a memory space in an HT (hyper transport) address space; and 3) according to the PCI memory space being moved in the CPU address space, updating a PCI memory resource structure body of an operating system. According to the invention, the large memory PCI/PCIE (peripheral component interconnect express) device support of a Loongson 3A platform can be realized, the popularization and application of the Loongson 3A platform can be promoted, and the method has the advantages of good compatibility and wide application range.

The present disclosure facilitates the interoperability between different local applications. Related local data objects are referenced via global objects or reference containers within a global data model or a global address space of an integration solution. The present disclosure assumes that the integration solution is per default in a consistent state, e.g., an engineered or initially configured global address space is regarded as consistent, and all software components that operate within this space assume that the information they access is valid and likewise consistent. The local applications are the only components that can interact with the global address space and introduce invalidations, they are continuously monitored for changes. Invalidation and subsequent synchronization or restoration of consistency is performed upon a particular triggering event related to a change in a local application object (such as an insertion or removal of an object or a modification of an attribute thereof) or related to a changing application or adapter status (component shutdown/startup).

A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.

The invention provides a chip self-test method executed by a self-test system; the method comprises the following steps: the self-test system respectively generates a serial debug command sequential macrodefinition set and a test control scheme macrodefinition set; the self-test system obtains front end logic information of the chip; the self-test system generates a test vector file according to the front end logic information, the sequential macrodefinition set and the test control scheme macrodefinition set; the self-test system writes the test vector file into a tested chip through a test machine, and receives a test result returned by the test machine. The chip self-test method can fast and effectively verify SOC global address space, is simple in operation, easy to realize, and the method has high transplantability and connectivity; in addition, the method can save resources, and reduces test cost; the invention also provides the chip self-test system.