678 results about "Address space" patented technology

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

The invention provides a universal measurement and control system data flow control bus architecture method and system, and relates to the technical field of measurement and control, and the method comprises the steps: distributing independent address spaces for a plurality of driving modules through a main control module, building a parameter mapping table and a buffer region, and enabling a plurality of test channels to share an interrupt signal and store the interrupt signal in an interrupt vector register; generating an interrupt signal based on a relationship between the buffer data volume and a threshold; sequencing according to the channel priority reference value, and dynamically adjusting the priority based on the load rate; and the main control module determines an interrupt source according to the interrupt vector and dynamically adjusts a prefetching strategy according to the measurement and control data flow. The system data processing efficiency and the resource utilization rate are improved.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

The invention provides a chip security key protection method and system capable of resisting side channel attack, and relates to the technical field of chips, which comprises the following steps of: obtaining a key operation request, performing address space mapping based on a dynamic mapping rule to obtain encrypted key data, decrypting the encrypted key data, fragmenting key intermediate data, and allocating an independent processing channel to perform decoupling operation; and injecting a time-varying noise signal to cover the association between the key and the physical characteristics, and finally performing recombination and reverse conversion to generate a final key output. According to the method, side channel attacks such as power consumption analysis and electromagnetic analysis are effectively resisted, and the security of key storage and operation processes is improved.

The invention relates to the technical field of chips, and discloses a hardware accelerator and a data handling method, the hardware accelerator comprises a doorbell processing module, a descriptor cache module and at least one DMA engine module; wherein a target engine module in the at least one DMA engine module is configured to read a target descriptor from effective descriptors in the descriptor cache module and analyze the target descriptor to obtain a source address field, a source address space identifier, a destination address field and a destination address space identifier, and carrying the target data block in the first user space to the second user space based on the source address field, the source address space identifier, the destination address field and the destination address space identifier, wherein the effective descriptor is read from a descriptor ring in the first user space through the doorbell processing module and is written into the descriptor cache module. Therefore, through cooperative work of all the modules, full-hardware acceleration of user mode data carrying is completed, and therefore the data carrying efficiency is remarkably improved.

The embodiment of the invention discloses a test instruction generation method and device, electronic equipment, a medium and a product. The method comprises the steps that hardware constraint information of a specified processor architecture is obtained, and the hardware constraint information comprises a plurality of threads supported by the specified processor architecture, the number of operators to be executed by each thread and an address space corresponding to each thread; for each thread, according to the number of operators to be executed by the thread, calling different operators through each execution engine, and generating a target operator queue corresponding to the thread; determining a test instruction stream corresponding to a target operator queue of the thread according to the address space corresponding to the thread; wherein each target operator in the target operator queue corresponds to one test instruction in the test instruction stream, and an output address of at least one test instruction in the test instruction stream is an input address of a subsequent test instruction; and generating a test instruction file of the specified processor architecture according to the test instruction stream corresponding to each thread.

The invention provides a hot upgrade method for a virtual machine monitor (VMM), which comprises the following steps of: pausing the operation of a virtual machine, storing state information of an original VMM, and reserving a kernel-based virtual machine KVM extension page table and a memory management structure of the original VMM; reserving a page global directory and a virtual memory area VMA corresponding to a virtual machine RAM area according to the memory management structure, and refreshing a process address space described by the memory management structure into a new VMM execution program so as to complete switching of the original VMM into the new VMM; and executing the new VMM, recovering the state information to the new VMM, and inheriting the KVM extension page table by the new VMM to recover the operation of the virtual machine. The invention further provides computer equipment, a computer readable medium and a computer program product.

The invention discloses a storage space management method and device, a storage medium, electronic equipment and a program product, and relates to the technical field of distributed storage, and the method comprises the steps: obtaining a plurality of physical addresses of a plurality of physical storage equipment on a server corresponding to different nodes in a distributed storage system; a plurality of physical addresses are connected in series to generate address space pools corresponding to different servers, and linked lists corresponding to the address space pools are determined; under the condition of determining that the target object initiates the logical volume creation request, determining a target number of logical addresses from the address space pool according to the linked list, and recording a mapping relationship among the logical volume, the logical addresses and a target physical address associated with the logical addresses; the storage space associated with the logical volume is managed based on the mapping relation, the storage space at least comprises two physical storage devices, and the problem that when an existing distributed storage system carries out data storage, metadata access delay is caused by data striping is solved.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention relates to a firmware upgrading method and electronic equipment. The method comprises the following steps: in a first stage of upgrading, constructing upgrading meta-information according to a current partition table and a to-be-upgraded firmware data storage area base address obtained by calculating to-be-upgraded firmware meta-information, and according to a block list description file, updating the to-be-upgraded firmware data storage area base address; in the first-stage upgrade, a partition table file with a preset name in a firmware upgrade package under a preset firmware upgrade package path of an encrypted preset user data partition and all to-be-upgraded firmware mirror image files are stored in an address space determined by a base address of a to-be-upgraded firmware data storage area; and determining a to-be-upgraded firmware data storage space end address and a to-be-upgraded firmware data moving base address according to the guide communication partition address space change mark, and copying data in an address space determined by the to-be-upgraded firmware data storage space end address to the to-be-upgraded firmware data moving base address. According to the invention, under the condition of user data partition encryption, the firmware with any change of the partition table can be safely and reliably upgraded.

The embodiment of the invention provides an input and output memory management unit, a memory access method and related equipment, and the input and output memory management unit comprises an input and output translation bypass buffer which comprises a cache table item used for caching a mapping relation between an equipment virtual address and a system physical address carried by a memory access request; an address space identifier of the equipment sending the memory access request is cached in a label item of the cache table item; and when a memory access request is obtained, querying a cache table item of the input / output translation bypass buffer at least based on the sent address space identifier, so as to obtain a system physical address mapped by the cached equipment virtual address in the address item corresponding to the tag item hit by the query. According to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the function of the input / output translation bypass buffer is realized, the reliability and the safety of determining the physical address of the system between devices can be improved.

The present application relates to the technical field of computers, and provides a memory data access method and apparatus, an electronic device and a readable storage medium. The method comprises: acquiring failure information of a memory component; configuring an address space mapping scheme for the failure information; in response to an initial memory access instruction sent by a processor, extracting a memory access address in the initial memory access instruction; on the basis of the memory access address and the address space mapping scheme, acquiring a plurality of target addresses corresponding to the memory access address, wherein target memory access instructions have one-to-one correspondence to the target addresses; executing the target memory access instructions by means of a memory controller so as to write split data, which is obtained after splitting write data sent by the processor, into the target addresses; and splicing read data read from the target addresses, and then returning to the processor.

Enhanced security for Zero Trust networks is provided by SSH-customized tunnel clients / tunnel servers, a catalog service, and loopback address DNS mechanisms. Systems and methods provide Policy Enforcement Point (PEP) layer enhancements, strategically positioning the PEP between the user and the network resource. It manages network traffic flows and provides moderate control granularity, near-real-time enforcement decisions, low overheads, and broad applicability to TCP / IP traffic through modified tunneling implementations of Secure Shell (SSH). Unique use of SSH tunneling is utilized and adapted to selectively filter tunnel requests based on user entitlements, ensuring secure and authorized access to network resources. This method entails detailed assessment of tunneling requests, DNS manipulation, and the use of loopback address space for traffic redirection, all without requiring modifications to client-side applications. The approach significantly enhances network security by controlling access based on continuous verification of user entitlements, addressing the shortcomings of traditional network security models.

The invention discloses an agent-free honeypot mapping method and device, and relates to the technical field of network security. The method comprises the following steps: analyzing metadata of core switching equipment, and establishing a domain-address mapping matrix; periodically detecting an address space, constructing an IP asset dynamic portrait and generating an asset state map; deploying a cross-domain traffic forwarding protocol stack and a virtual domain identifier mapping rule; deploying a software-defined virtual switching unit and accessing the virtual honeypot probe cluster; allocating idle addresses for the probes and establishing a binding relationship; and periodically detecting and triggering a self-healing process when an address conflict occurs. The device comprises a core exchange and domain management unit, an IP asset detection unit, a network protocol configuration unit, a probe virtualization management unit, an address resource scheduling unit and a system cooperative control unit. According to the method, agency-free and automatic deployment of the honeypot is realized, and the problems that a traditional scheme depends on agency software, deployment is complex and IP conflict processing lags are solved.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

The invention provides a large-scale-oriented IPv6 target address generation method and a large-scale-oriented IPv6 target address generation system. The method comprises the following steps: constructing an IPv6 seed address set based on an IPv6 capacity expansion strategy of sampling distribution and an IPv6 classification strategy based on an address structure; clustering the IPv6 seed address set to construct an IPv6 address space tree so as to generate a low-dimension IPv6 address mode set and a high-dimension IPv6 address mode set; generating an IPv6 target address set in the low-dimension IPv6 address mode space, and removing IPv6 alias addresses in the IPv6 target address set to obtain a non-alias target address set; a non-alias target address set in a low-dimension IPv6 address mode space is detected, an active high-dimension IPv6 address mode is screened out from a high-dimension IPv6 address mode set according to the detected IPv6 active address, an IPv6 target address set is generated in a corresponding space of the active high-dimension IPv6 address mode, IPv6 alias addresses are removed, and the IPv6 address mode is obtained. After a non-alias target address set is obtained, detecting the non-alias target address set and collecting responded IPv6 active addresses; and combining the IPv6 active addresses detected in all the seed address sets to form a final IPv6 active address set.

The invention discloses a process file system access optimization method and device based on an eBPF. The method comprises the following steps: collecting information of a procfs node through an eBPF program, and writing the information into eBPF annular buffer mapping mapped to address spaces of a plurality of user processes; the user process calculates a hash identifier according to the target procfs node path and searches a corresponding mapping item in a shared annular array based on the hash identifier, and the mapping item comprises an annular buffer address pointing to target procfs node information stored in eBPF annular buffer mapping; and if the searching is successful, reading the information of the target procfs node according to the address of the ring buffer. According to the method and the device, the problem of low efficiency of tools in the prior art, such as ps, when the system process information is acquired can be solved on the premise of ensuring the security.

The invention relates to a hot update control method and system for an industrial PLC (Programmable Logic Controller) of a microkernel operating system, belonging to the field of industrial controllers. A shadow instance is created by an isolated address space and is bound with a shadow I / O (Input / Output) mirror image and a shadow communication stack; capturing a containment point in the scanning period, wherein the containment point is located between input sampling completion and output submission; acquiring running state information from the current network instance, converting the running state information, and transmitting the converted running state information to the shadow instance; pre-operating the shadow instance in the isolation channel in an accelerated or constant-speed manner, and switching the I / O channel from the current network instance to a shadow I / O mirror image of the shadow instance at the next restraint point if the verification is passed; and continuing to run in parallel for a certain period, unloading the old instance if the continuous running is qualified, and executing rollback if an exception occurs. Depending on a microkernel operating system, shadow instances are drilled and switched under the controlled priority, the real-time performance and certainty are met, the time delay defect of periodic gap switching is overcome, and updating and switching are completed in a single scanning period or a plurality of scanning periods in an atomic mode.

The invention provides an address management method and device for a heterogeneous system and computer equipment, and relates to the technical field of computers, in particular to the fields of data processing, data transmission and the like. According to the implementation scheme, a second virtual address space of a data transmission module is divided into second sub-virtual address spaces with the same number as that of data processing modules, and the size of the second sub-virtual address spaces is the same as that of first virtual address spaces of the data processing modules; distributing a unique identifier to the data processing module, wherein the unique identifier is a natural number; for the first virtual address space, the first virtual address space is offset by a preset offset through the unique identifier, so that a second sub-virtual address space corresponding to the first virtual address space is determined in the second sub-virtual address space, and the preset offset is a product of the unique identifier and the size of the first virtual address space; and establishing a mapping relationship between the first virtual address space and the corresponding second sub-virtual address space.

The invention discloses an audio test data processing method, system and device based on zero-copy NIO and a dynamic sliding window, and the method comprises the following steps: S1, building a memory mapping file channel, and directly mapping an audio file to a process address space; s2, constructing a double-buffer processing pipeline, and realizing asynchronous decoupling of a collection thread and a calculation thread by adopting a producer-consumer mode; and S3, a dynamic sliding window mechanism is adopted to maintain a real-time audio data interval, and the window size is dynamically adjusted according to a television CPU load. According to the technical scheme of the invention, the problems of high memory occupation, high detection delay and low cross-application data reading efficiency existing in audio testing of a television system in a multi-application concurrent scene are solved.

According to the method, PCIe extended storage equipment is identified by responding to a system starting signal, and initialization and address mapping control logic is executed to construct a first address space addressable by a GPU (Graphics Processing Unit); then, loading model data according to an AI task instruction, and dynamically dividing hot, warm and cold multi-level data popularity levels by monitoring memory access frequency; a migration data block is generated based on the popularity level, a migration data flow is organized and verified through priority scheduling logic, and intelligent data scheduling between extended storage and a GPU video memory is achieved; finally, the resources are released after the task is completed. Therefore, dynamic expansion of the physical video memory capacity is effectively achieved, large-scale AI model localization training is met, dependence on a high-end GPU chip is remarkably reduced, and data safety and system economy are improved.

The invention relates to the technical field of storage system IO performance optimization, and provides a redirection data aggregation method and equipment, and the method comprises the steps: recognizing random small IO data from a written IO request, aggregating and writing back-end storage objects, and constructing a storage mapping relation in an index table; traversing the rear-end storage object in which the random small IO data is stored, and distributing data from the same logic address space to point to the same target rear-end storage object through a hash algorithm; writing the data distributed to point to the same target back-end storage object into the continuous physical space of the target back-end storage object in sequence, and updating the mapping relation in the index table; the step S2 and the step S3 are repeated before a preset termination triggering condition is met, and a hash algorithm different from all previous times is adopted when the step S2 is repeatedly executed each time; when the data are read, the storage mapping relation is obtained from the index table, and the read requests corresponding to the data located in the same back-end storage object are aggregated and then read at a time.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention discloses a management and maintenance method and system for a heterogeneous multi-core processor of a spaceborne computer, and relates to the technical field of space scientificity, and the method comprises the following steps: configuring a global addressing controller through a main core in a power-on initialization stage, and executing address access authority distribution of a heterogeneous multi-core processor core; on the basis of combination of a sub-core storage partition strategy and a heartbeat monitoring reset mechanism, a master core periodically detects the state of a slave core and executes reset operation, and lightweight fault-tolerant management of a heterogeneous multi-core processor is achieved to guarantee continuous operation of a multi-core system under local faults; according to the method, radiation-induced storage errors are corrected based on a master core read-back refreshing strategy, slave core access behaviors are restrained through an address space locking mechanism, a master-slave collaborative reliability maintenance system is formed to ensure on-orbit stable operation of the spaceborne computer, and continuous and stable operation of the heterogeneous multi-core processor of the spaceborne computer in a complex space environment can be ensured.

The invention relates to an operating system environment construction technology, and discloses an ARM (Advanced RISC Machines) processor-oriented micro-kernel operating system confidential computing environment construction method, which is characterized in that a hierarchical system architecture is constructed, a virtual machine monitor and a confidential domain management monitor are decoupled at an ARM exception level EL2, and the virtual machine monitor and the confidential domain management monitor run in mutually isolated address spaces. The RMM is used as an independent module for dynamic loading, a management mechanism of a confidential computing domain is specially used, and the Hypervisor is only responsible for strategy scheduling, so that the defect that the Hypervisor is bloated in function in a traditional scheme is overcome. According to the method, the RMM is loaded through the security startup process during startup, the confidential virtual machine is dynamically created during running, mirror image security verification, memory encryption and other mechanisms are integrated, and finally the security domain is destroyed after the application is finished. The method has the advantages that a flexible and safe confidential computing environment conforming to the minimum privilege principle is provided for the microkernel system, and the method is particularly suitable for embedded scenes with high safety requirements such as the Internet of Things and industrial control.

Provided in the embodiments of the present disclosure are a chip management network configuration method, a chip management network system, a computing device, a storage medium and a computer program product, which are applied to a target chip. The target chip comprises a plurality of different types of chiplets, each chiplet containing one or more modules and being configured with a management network configuration serial number, and the management network configuration serial number being configured on the basis of the type of the chiplet and its encapsulation position in the target chip. The chip management network configuration method comprises: acquiring architecture information of the target chip, at least comprising the management network configuration serial numbers configured for the chiplets; on the basis of the architecture information of the target chip, dividing a preset address space into a plurality of sub-configuration spaces; and, on the basis of the management network configuration serial numbers, allocating corresponding sub-configuration spaces among the plurality of sub-configuration spaces to the target chip and each chiplet in the target chip, wherein the sub-configuration spaces allocated to the modules contained in each chiplet are different.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.