941 results about "Address space" patented technology

The invention discloses an extension equipment function configuration method and device, computer equipment and a storage medium, and relates to the technical field of data processing. According to the method, a hardware and firmware collaborative dynamic configuration framework is constructed, and a receiving queue is adopted at an extension equipment end to trigger a central processing unit firmware processing mechanism; in combination with virtualization design of a shadow configuration space and a shadow register, dynamic reconstruction of configuration parameters and an address mapping strategy during operation is realized; a host end supports configuration space access, base address register remapping and memory data transmission interaction through a transaction generation and routing mechanism driven by an event type. Hardware solidification limitation of traditional extension equipment is broken through through software and hardware decoupling design, the problems that function extension capacity is insufficient, resource dynamic allocation is difficult and protocol updating and virtualization scenes cannot be adapted are solved, and the technical effects of improving configuration reconstruction efficiency and address space utilization rate and supporting virtual function creation are achieved. And the adaptability of the equipment in cloud computing and edge computing environments is enhanced.

A memory management method and apparatus, and a computing device. The method is executed by a GMEM system. When receiving a physical memory range, a memory management unit operation function, and an accelerator device address of an accelerator device, the GMEM system configures a memory management unit operation function interface for the accelerator device, and a device where the GMEM system is located is enabled to use a driver of the accelerator device to manage a memory management unit and a physical memory of the accelerator device by means of the memory management unit operation function interface for the accelerator device, so as to read and write data. In the present application, the GMEM system extends a native memory management interface of an operating system into a heterogeneous memory management interface, supporting programming based on a unified virtual address space, and memory management unit operation function interfaces are configured for different types of accelerator devices, so that the device where the GMEM system is located can support the use of different types of accelerator devices, without the need to consider the compatibility of memory interfaces of different types of accelerator devices.

This invention pertains to a system optimized for reutilizing allocated underutilized or unused allocated DRAM, comprising a first host, a second host, and a resource composer, interconnected via CXL. Both hosts run packaged computing environments (PCEs), which may be containers or virtual machines, and are equipped to handle respective processes, P1 and P2. The resource composer is tasked with receiving data related to P1's memory usage from a kernel module on the first host, identifying underutilized DRAM mapped to P1, and subsequently remapping it to P2's address space on the second host. This process involves the use of CXL.mem commands, which are then translated into appropriate CXL.cache or CXL.io commands for DRAM access based on the mapping.

The invention discloses a memory management method and device and computing equipment. The method is executed by a GMEM system, after the GMEM system receives a physical memory range, a memory management unit operation function and an accelerator device address of the accelerator device, a memory management unit operation function interface is configured for the accelerator device, and the device where the GMEM system is located is enabled to operate the function interface through the accelerator device memory management unit. And managing a memory management unit and a physical memory of the accelerator equipment by utilizing a driver of the accelerator equipment so as to read and write data. According to the GMEM system, a native memory management interface of an operating system is expanded into a heterogeneous memory management interface, programming of a unified virtual address space is supported, and memory management unit operation function interfaces are configured for various types of accelerator devices, so that the device where the GMEM system is located can support the use of the various types of accelerator devices, and the operation efficiency of the accelerator devices is improved. And the compatibility problem of memory interfaces of various types of accelerator equipment does not need to be considered.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The embodiments of the present disclosure provide data processing methods, a computer system, a computer-readable storage medium and a computer program product. A data processing method comprises: acquiring a first control command transmitted by a second service program, and determining a physical address region; applying for a virtual address region from a second virtual address space to which a service data storage region is mapped, and on the basis of the virtual address region, generating a second control command; and establishing a mapping relationship between the virtual address region and the physical address region for a first service program to access the physical address region on the basis of the virtual address region in the second control command acquired from a control command storage region. The technical solution provided in the embodiments of the present disclosure realizes high-speed data transmission between service programs.

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

The invention provides a data transmission efficiency improving method and device, equipment and a storage medium, and the method comprises the steps: carrying out the equipment recognition and address space mapping of expansion card equipment connected with a PCIe interface on a GPU, and obtaining GPU data transmission configuration information; according to the configuration information, carrying out storage space division and transmission channel establishment on the expansion card equipment to obtain a GPU data transmission channel configuration result; scheduling and distributing the GPU data to be transmitted based on the configuration result and a preset CUDA (Compute Unified Device Architecture) shared storage mechanism to obtain a data transmission execution scheme; and starting, controlling, monitoring in real time and dynamically adjusting the transmission process of the data to be transmitted according to the execution scheme and a preset RAID (Redundant Array of Independent Disks) disk array. According to the method, the expansion card equipment and the RAID disk array are introduced, and a CUDA shared storage mechanism is combined, so that the available storage space of the GPU is effectively expanded, the data transmission process is optimized, the data transmission efficiency when the GPU processes a large-scale data set is remarkably improved, and meanwhile, relatively low hardware cost is kept.

The invention provides a universal measurement and control system data flow control bus architecture method and system, and relates to the technical field of measurement and control, and the method comprises the steps: distributing independent address spaces for a plurality of driving modules through a main control module, building a parameter mapping table and a buffer region, and enabling a plurality of test channels to share an interrupt signal and store the interrupt signal in an interrupt vector register; generating an interrupt signal based on a relationship between the buffer data volume and a threshold; sequencing according to the channel priority reference value, and dynamically adjusting the priority based on the load rate; and the main control module determines an interrupt source according to the interrupt vector and dynamically adjusts a prefetching strategy according to the measurement and control data flow. The system data processing efficiency and the resource utilization rate are improved.

The invention relates to the technical field of SOC chips, and discloses an efficient memory management method and system based on an SOC chip, which are used for constructing a complete topological graph and calculating access delay distribution by comprehensively analyzing an internal physical structure of the chip. According to the method, the memory access behavior of each processing core is monitored in real time, dynamic memory partitioning is executed according to the access characteristics and the physical topological structure, and the optimal access area is distributed for the processing core. And when an access hot spot is detected, triggering a data migration mechanism to copy hot spot data to a relatively close memory area. According to the method, a memory address space is recombined by adopting a topology-aware address mapping algorithm, a multi-level cache collaboration mechanism is established, and the working mode of a memory controller is dynamically adjusted according to an application type. Through load balancing monitoring and periodic memory recombination, the memory access delay is effectively reduced, the bandwidth utilization rate is improved, and the overall memory access performance of the SOC chip is optimized.

Systems and methods are disclosed for implementing a Non-Volatile Memory Express (NVMe) driver in a computer system. The method involves mapping a memory buffer into a user mode address space to facilitate data transfer with an NVMe device via direct memory access (DMA). Additionally, a first NVMe queue pair, including a submission queue (SQ) and a completion queue (CQ), is mapped into the user mode address space, allowing a user mode component to submit commands to the NVMe device. The method further enables the user mode component to ring a doorbell at the NVMe device. Finally, an NVMe command is processed in kernel mode using a second NVMe queue pair comprising a second SQ and a second CQ.

The invention provides a chip security key protection method and system capable of resisting side channel attack, and relates to the technical field of chips, which comprises the following steps of: obtaining a key operation request, performing address space mapping based on a dynamic mapping rule to obtain encrypted key data, decrypting the encrypted key data, fragmenting key intermediate data, and allocating an independent processing channel to perform decoupling operation; and injecting a time-varying noise signal to cover the association between the key and the physical characteristics, and finally performing recombination and reverse conversion to generate a final key output. According to the method, side channel attacks such as power consumption analysis and electromagnetic analysis are effectively resisted, and the security of key storage and operation processes is improved.

The embodiment of the invention discloses an address search method and device based on deep learning, a storage medium and a server, and relates to the field of logistics information processing. The method comprises the following steps: firstly, acquiring data such as text addresses, space coordinates, peripheral POIs (Point of Interest) and streetscape pictures from a multi-modal address database; text addresses are decomposed into different levels and converted into corresponding vectors, and then the vectors are spliced into text address vectors. The space coordinates, the POI and the streetscape pictures are also converted into vectors respectively, and the vectors are subjected to weighted summation to generate multi-modal vectors; meanwhile, the text address entity inquires the knowledge base to obtain semantic enhancement information, encodes the semantic enhancement information into a vector, splices the vector with the multi-modal vector to form a final address vector, and stores the final address vector into an address vector library. After the user inputs the query text address, the query vector is generated, the candidate address vector with high similarity is retrieved in the library, and detailed information of the candidate address is displayed on the interactive interface, so that the accuracy and richness of address description are improved, and an efficient address query function is realized.

The invention relates to the technical field of chips, and discloses a hardware accelerator and a data handling method, the hardware accelerator comprises a doorbell processing module, a descriptor cache module and at least one DMA engine module; wherein a target engine module in the at least one DMA engine module is configured to read a target descriptor from effective descriptors in the descriptor cache module and analyze the target descriptor to obtain a source address field, a source address space identifier, a destination address field and a destination address space identifier, and carrying the target data block in the first user space to the second user space based on the source address field, the source address space identifier, the destination address field and the destination address space identifier, wherein the effective descriptor is read from a descriptor ring in the first user space through the doorbell processing module and is written into the descriptor cache module. Therefore, through cooperative work of all the modules, full-hardware acceleration of user mode data carrying is completed, and therefore the data carrying efficiency is remarkably improved.

The embodiment of the invention discloses a test instruction generation method and device, electronic equipment, a medium and a product. The method comprises the steps that hardware constraint information of a specified processor architecture is obtained, and the hardware constraint information comprises a plurality of threads supported by the specified processor architecture, the number of operators to be executed by each thread and an address space corresponding to each thread; for each thread, according to the number of operators to be executed by the thread, calling different operators through each execution engine, and generating a target operator queue corresponding to the thread; determining a test instruction stream corresponding to a target operator queue of the thread according to the address space corresponding to the thread; wherein each target operator in the target operator queue corresponds to one test instruction in the test instruction stream, and an output address of at least one test instruction in the test instruction stream is an input address of a subsequent test instruction; and generating a test instruction file of the specified processor architecture according to the test instruction stream corresponding to each thread.

Dynamic provisioning of resources in a datacenter improves the utilization efficiency of compute, memory, storage, and network resources, while maintaining flexibility to meet changing demands. Embodiments herein disclose protocol-aware provisioning of resources over Compute Express Link (CXL) fabrics, enabling multi-protocol pooling and disaggregation of resources, including memory and workload-specific accelerators such as GPUs and DSAs. In some embodiments, a Resource Provisioning Unit (RPU) facilitates intent-based protocol translations and mappings between address spaces, potentially enabling the creation of large-scale compute-memory fabrics that may utilize both coherent and non-coherent Non-Transparent Bridging (NTB) between multiple protocols in a single system, serving as the underlying infrastructure for executing workloads such as Large-Language Models (LLMs) and Deep Learning Recommendation Models (DLRMs). Some embodiments also optimize low-latency communication between processes running on different nodes by enabling host-to-host memory provisioning for libraries such as OpenMP, Pthreads, or CUDA, which can utilize shared memory.

The invention provides a hot upgrade method for a virtual machine monitor (VMM), which comprises the following steps of: pausing the operation of a virtual machine, storing state information of an original VMM, and reserving a kernel-based virtual machine KVM extension page table and a memory management structure of the original VMM; reserving a page global directory and a virtual memory area VMA corresponding to a virtual machine RAM area according to the memory management structure, and refreshing a process address space described by the memory management structure into a new VMM execution program so as to complete switching of the original VMM into the new VMM; and executing the new VMM, recovering the state information to the new VMM, and inheriting the KVM extension page table by the new VMM to recover the operation of the virtual machine. The invention further provides computer equipment, a computer readable medium and a computer program product.

The invention discloses a storage space management method and device, a storage medium, electronic equipment and a program product, and relates to the technical field of distributed storage, and the method comprises the steps: obtaining a plurality of physical addresses of a plurality of physical storage equipment on a server corresponding to different nodes in a distributed storage system; a plurality of physical addresses are connected in series to generate address space pools corresponding to different servers, and linked lists corresponding to the address space pools are determined; under the condition of determining that the target object initiates the logical volume creation request, determining a target number of logical addresses from the address space pool according to the linked list, and recording a mapping relationship among the logical volume, the logical addresses and a target physical address associated with the logical addresses; the storage space associated with the logical volume is managed based on the mapping relation, the storage space at least comprises two physical storage devices, and the problem that when an existing distributed storage system carries out data storage, metadata access delay is caused by data striping is solved.

In disclosed embodiment, a graphics processor is configured to operate on data in multiple memory spaces. Data cache circuitry may cache data for the graphics processor circuitry, including data from multiple memory spaces. The data cache circuitry may include tag circuitry configured to compare the following information from access requests to the data cache circuitry with tags of entries in the data cache circuitry: memory space information and a tag portion of a requested address. The tag portion of a requested address may be different (e.g., a different set of bit indices within the address) for at least two of the multiple memory spaces. Disclosed techniques may advantageously facilitate caching for disparate clients with different cache line sizes, address spaces, etc., e.g., in unified memory architectures.

The invention relates to the technical field of storage, in particular to a storage array controller, a storage array system and a data processing method. The storage array controller comprises a storage interface control module which is used for receiving and analyzing message data sent by a remote host to obtain an operation command, carrying out scheduling management on the operation command based on a namespace and then transmitting the operation command to a redundancy module; the redundancy module is used for performing redundancy calculation on the data, writing the data into a controller memory, and managing the logic address space of the storage array and the controller memory based on the namespace; and the nonvolatile storage control module responds to the data transmission request of the redundancy module and maps the controller memory to realize data interaction with the storage array, so that the problem of low read-write data processing efficiency of the existing storage array controller can be solved.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention relates to a firmware upgrading method and electronic equipment. The method comprises the following steps: in a first stage of upgrading, constructing upgrading meta-information according to a current partition table and a to-be-upgraded firmware data storage area base address obtained by calculating to-be-upgraded firmware meta-information, and according to a block list description file, updating the to-be-upgraded firmware data storage area base address; in the first-stage upgrade, a partition table file with a preset name in a firmware upgrade package under a preset firmware upgrade package path of an encrypted preset user data partition and all to-be-upgraded firmware mirror image files are stored in an address space determined by a base address of a to-be-upgraded firmware data storage area; and determining a to-be-upgraded firmware data storage space end address and a to-be-upgraded firmware data moving base address according to the guide communication partition address space change mark, and copying data in an address space determined by the to-be-upgraded firmware data storage space end address to the to-be-upgraded firmware data moving base address. According to the invention, under the condition of user data partition encryption, the firmware with any change of the partition table can be safely and reliably upgraded.

A data access method, comprising: receiving a first data access instruction from an upper-level chip; determining a new access address on the basis of an access address in the first data access instruction and address space information of a current chip; and updating the access address in the first data access instruction to the new access address, and then sending to the next-level chip the first data access instruction after update so as to access target data. According to the data access method, cross-chip data access in a multi-chip cascading mode can be realized, and a cascade chip group having a larger addressable range can be flexibly constructed according to requirements, so as to meet different product or application requirements. Further disclosed are a multi-chip cascading method and system, a device, and a storage medium.

The invention discloses a time delay optimization method and device of a network interconnection system, electronic equipment and a medium, and relates to the field of network communication, and the method comprises the steps: adjusting the BAR resource window size of a non-transparent bridge processor in a BIOS based on a firmware file of a target processor, and re-burning the adjusted BIOS to a BMC processor, and initializing each DMA channel in the non-transparent bridge processor to obtain a physical address of each DMA channel, identifying the minimum physical address as a mapping initial address of the BAR, and mapping the mapping initial address and the BAR address space sum to a virtual address space of a user mode so as to access each DMA channel. The problem that the requirements for the overall bandwidth and low delay of the storage controller cannot be met when one DMA channel is started is solved, the data concurrent processing capacity of the non-transparent bridge processor is improved by enabling the four DMA channels and mapping the four DMA channels to the user mode, and therefore the interconnection bandwidth of the controllers is higher, and the interconnection delay of the controllers is lower.

The invention provides a shared cache control system for a high-performance switch. The shared cache control system comprises a plurality of port modules, a plurality of memory allocation modules, a plurality of memory recovery modules, a dynamic channel allocation module and an SRAM (Static Random Access Memory) array, the dynamic channel distribution module is used for cross communication among the port module, the memory distribution module, the memory recovery module and the SRAM array; the port module is used for receiving and transmitting data packets, scheduling other modules to work and performing read-write operation on addresses in the SRAM array; the memory allocation module is used for allocating a memory space address for the data packet and recording an idle state or an occupied state of an SRAM address space by adopting a vector mapping mechanism; and the recovery module is used for requesting the destination port to read the data packet and recovering the memory address space corresponding to the read data packet. The method has the beneficial effect that the switching rate of the shared cache type switch is improved.

The invention provides a data processing method, device and system, and relates to the technical field of computers. According to the data processing method, an access logic address of a user in the storage system is converted into a first physical address and a second physical address, an error correction code is read or written according to the first physical address and the second physical address, and the first physical address and the second physical address correspond to different address spaces of different storage particles in a memory. Under the condition that the storage medium fault area has aggregation characteristics and the fault areas of different storage particles are the same or similar, code words of error correction codes are written or read in different address spaces, namely different bit fault rate areas, in different storage particles, so that the code words of the error correction codes are dispersed in the address spaces of the different bit fault rate areas; the maximum error bit number of the code word of the error correction code can be reduced, the error bit number difference of accessing different address spaces is reduced, the waste of error correction code resources is reduced, and the reliability of a memory is improved while the utilization rate of the error correction code resources is improved.

The embodiment of the invention provides an input and output memory management unit, a memory access method and related equipment, and the input and output memory management unit comprises an input and output translation bypass buffer which comprises a cache table item used for caching a mapping relation between an equipment virtual address and a system physical address carried by a memory access request; an address space identifier of the equipment sending the memory access request is cached in a label item of the cache table item; and when a memory access request is obtained, querying a cache table item of the input / output translation bypass buffer at least based on the sent address space identifier, so as to obtain a system physical address mapped by the cached equipment virtual address in the address item corresponding to the tag item hit by the query. According to the technical scheme provided by the embodiment of the invention, on the basis of ensuring that the function of the input / output translation bypass buffer is realized, the reliability and the safety of determining the physical address of the system between devices can be improved.

The present application relates to the technical field of computers, and provides a memory data access method and apparatus, an electronic device and a readable storage medium. The method comprises: acquiring failure information of a memory component; configuring an address space mapping scheme for the failure information; in response to an initial memory access instruction sent by a processor, extracting a memory access address in the initial memory access instruction; on the basis of the memory access address and the address space mapping scheme, acquiring a plurality of target addresses corresponding to the memory access address, wherein target memory access instructions have one-to-one correspondence to the target addresses; executing the target memory access instructions by means of a memory controller so as to write split data, which is obtained after splitting write data sent by the processor, into the target addresses; and splicing read data read from the target addresses, and then returning to the processor.

Enhanced security for Zero Trust networks is provided by SSH-customized tunnel clients / tunnel servers, a catalog service, and loopback address DNS mechanisms. Systems and methods provide Policy Enforcement Point (PEP) layer enhancements, strategically positioning the PEP between the user and the network resource. It manages network traffic flows and provides moderate control granularity, near-real-time enforcement decisions, low overheads, and broad applicability to TCP / IP traffic through modified tunneling implementations of Secure Shell (SSH). Unique use of SSH tunneling is utilized and adapted to selectively filter tunnel requests based on user entitlements, ensuring secure and authorized access to network resources. This method entails detailed assessment of tunneling requests, DNS manipulation, and the use of loopback address space for traffic redirection, all without requiring modifications to client-side applications. The approach significantly enhances network security by controlling access based on continuous verification of user entitlements, addressing the shortcomings of traditional network security models.