420 results about "Address space" patented technology

The invention provides a chip security key protection method and system capable of resisting side channel attack, and relates to the technical field of chips, which comprises the following steps of: obtaining a key operation request, performing address space mapping based on a dynamic mapping rule to obtain encrypted key data, decrypting the encrypted key data, fragmenting key intermediate data, and allocating an independent processing channel to perform decoupling operation; and injecting a time-varying noise signal to cover the association between the key and the physical characteristics, and finally performing recombination and reverse conversion to generate a final key output. According to the method, side channel attacks such as power consumption analysis and electromagnetic analysis are effectively resisted, and the security of key storage and operation processes is improved.

The invention discloses a simulator detection method and system based on multi-dimensional feature fusion, and relates to the technical field of simulator detection, and the method comprises the steps: collecting the static feature information of a to-be-detected device; reading a memory mapping file of the equipment process in a preset time window, and obtaining a memory address allocation state at each moment to form a time sequence data set; further constructing an address space evolution sequence, and performing domain theory modeling to construct an address space domain; obtaining an address evolution function through a function construction algorithm; generating a regular mark through a natural transformation detection algorithm; performing topological structure analysis and coherence calculation on the address space category to generate address space complexity features; static feature information, regular marks and address space complexity features are integrated through a multi-layer fusion strategy, and simulator detection results are screened, judged and output layer by layer. According to the method, through a complementary collaborative system of static verification, dynamic rules and topology complexity, the anti-avoidance capability and robustness of detection are improved.

The invention discloses an equipment access method, device and equipment based on address space identification. The method is applied to simplifying an equipment memory management unit and comprises the steps of establishing each single-level range table; acquiring an equipment access request, reading an address space identifier and a virtual address from the equipment access request, and matching a corresponding target range table from each single-level range table based on the address space identifier; and calculating a target physical address according to the target range table and the virtual address, and establishing equipment access based on the target physical address. By replacing a traditional multi-level page table with a single-level structure, the data structure design of address mapping is simplified, the dynamic configuration complexity is reduced, and hardware formal verification is facilitated. Through direct matching of the address space identifier, the traditional steps of analyzing the equipment identity identifier and querying the external table item are omitted, and the external memory access frequency is reduced. By calculating the target physical address and establishing access, the hardware address conversion logic is simplified, the hardware implementation cost and power consumption are reduced, and the data transmission efficiency is improved.

The invention discloses a traffic incident detector system based on a domestic intelligent DSP and a detection method. The system comprises a video acquisition unit, a data exchange and storage unit, an intelligent processing core and a communication interaction unit. The intelligent processing core adopts a heterogeneous SoC chip integrating a multi-core DSP, an NPU and an FFT hardware acceleration module, the FFT module is responsible for video frame frequency domain enhancement, the NPU runs a deep learning model to carry out target detection, and the multi-core DSP executes multi-target parallel tracking and event judgment. And the data exchange and storage unit supports direct carrying of data among the modules through a unified physical address space and a DMA mechanism. The method comprises the following steps: carrying out NPU target detection on a video subjected to environment self-adaptive preprocessing; a multi-core DSP is used for tracking a target in parallel and judging an event; and finally, alarm information is generated and reported. Through heterogeneous hardware division and software and hardware cooperation, high-real-time and high-precision edge analysis is realized, and the detection reliability is improved.

The invention relates to a hot update control method and system for an industrial PLC (Programmable Logic Controller) of a microkernel operating system, belonging to the field of industrial controllers. A shadow instance is created by an isolated address space and is bound with a shadow I / O (Input / Output) mirror image and a shadow communication stack; capturing a containment point in the scanning period, wherein the containment point is located between input sampling completion and output submission; acquiring running state information from the current network instance, converting the running state information, and transmitting the converted running state information to the shadow instance; pre-operating the shadow instance in the isolation channel in an accelerated or constant-speed manner, and switching the I / O channel from the current network instance to a shadow I / O mirror image of the shadow instance at the next restraint point if the verification is passed; and continuing to run in parallel for a certain period, unloading the old instance if the continuous running is qualified, and executing rollback if an exception occurs. Depending on a microkernel operating system, shadow instances are drilled and switched under the controlled priority, the real-time performance and certainty are met, the time delay defect of periodic gap switching is overcome, and updating and switching are completed in a single scanning period or a plurality of scanning periods in an atomic mode.

According to the method, PCIe extended storage equipment is identified by responding to a system starting signal, and initialization and address mapping control logic is executed to construct a first address space addressable by a GPU (Graphics Processing Unit); then, loading model data according to an AI task instruction, and dynamically dividing hot, warm and cold multi-level data popularity levels by monitoring memory access frequency; a migration data block is generated based on the popularity level, a migration data flow is organized and verified through priority scheduling logic, and intelligent data scheduling between extended storage and a GPU video memory is achieved; finally, the resources are released after the task is completed. Therefore, dynamic expansion of the physical video memory capacity is effectively achieved, large-scale AI model localization training is met, dependence on a high-end GPU chip is remarkably reduced, and data safety and system economy are improved.

The invention provides a multi-core processor chip and a storage access method and device of the multi-core processor chip, and relates to the technical field of computer processors, the multi-core processor chip comprises at least one processor core, the processor core comprises a general processor core, a first address space mapping module and a first core interconnection interface, the universal processor core supports high-speed cache consistency; at least one input / output core grain, wherein the input / output core grain comprises a memory interface, a directory, a second address space mapping module and a second core grain interconnection interface; both the first address space mapping module and the second address space mapping module store an address space mapping table, and the address space mapping table stores a mapping relationship between a memory address accessed by a processor core grain and a memory interface of an input / output core grain; the directory stores cache consistency information of the cache blocks corresponding to the memory interfaces of the input / output core grain and other input / output core grains corresponding to the directory.

The invention relates to an operating system environment construction technology, and discloses an ARM (Advanced RISC Machines) processor-oriented micro-kernel operating system confidential computing environment construction method, which is characterized in that a hierarchical system architecture is constructed, a virtual machine monitor and a confidential domain management monitor are decoupled at an ARM exception level EL2, and the virtual machine monitor and the confidential domain management monitor run in mutually isolated address spaces. The RMM is used as an independent module for dynamic loading, a management mechanism of a confidential computing domain is specially used, and the Hypervisor is only responsible for strategy scheduling, so that the defect that the Hypervisor is bloated in function in a traditional scheme is overcome. According to the method, the RMM is loaded through the security startup process during startup, the confidential virtual machine is dynamically created during running, mirror image security verification, memory encryption and other mechanisms are integrated, and finally the security domain is destroyed after the application is finished. The method has the advantages that a flexible and safe confidential computing environment conforming to the minimum privilege principle is provided for the microkernel system, and the method is particularly suitable for embedded scenes with high safety requirements such as the Internet of Things and industrial control.

Provided in the embodiments of the present disclosure are a chip management network configuration method, a chip management network system, a computing device, a storage medium and a computer program product, which are applied to a target chip. The target chip comprises a plurality of different types of chiplets, each chiplet containing one or more modules and being configured with a management network configuration serial number, and the management network configuration serial number being configured on the basis of the type of the chiplet and its encapsulation position in the target chip. The chip management network configuration method comprises: acquiring architecture information of the target chip, at least comprising the management network configuration serial numbers configured for the chiplets; on the basis of the architecture information of the target chip, dividing a preset address space into a plurality of sub-configuration spaces; and, on the basis of the management network configuration serial numbers, allocating corresponding sub-configuration spaces among the plurality of sub-configuration spaces to the target chip and each chiplet in the target chip, wherein the sub-configuration spaces allocated to the modules contained in each chiplet are different.

Computer-implemented methods and associated hardware for static trusted execution environment for inter-architecture processor program compatibility are disclosed herein. A device (e.g., a Reduced Instruction Set Computing-Five (RISC-V) device), may emulate a static trusted execution environment (e.g., ARM TrustZone) using physical memory protection (PMP). A regular world may have access to only a portion of an address space of the device, while a secure world may have access to the full address space. A secure world identifier (SWID) may be stored in a configuration status register (CSR) only accessible by a mode (e.g., machine mode). When an entry is added to a translation lookaside buffer (TLB), the SWID may be added as part of a tag to differentiate secure world entries from regular world entries.

The invention discloses an Ethernet-based distributed cache coherence protocol, an implementation method, an implementation device and an implementation system. A plurality of computing nodes are connected through a packet switching network. Each computing node comprises a CPU / GPU (Central Processing Unit / Graphics Processing Unit) and a local cache thereof, and is provided with a cache agent. The far-end memory is organized in home nodes, and each home node manages a part of physical address space and is equipped with a directory controller. When the CPU of the computing node accesses a far-end memory address and does not hit in the local cache, the CA of the computing node replaces the far-end memory address and communicates with the DC managing the address through the network so as to maintain the cache consistency of the data among all the nodes. Based on a cache consistency protocol of a directory, the CXL.cache consistency of a plurality of independent computing nodes can be maintained in a low-overhead and high-reliability mode on a high-delay and lossy packet switching network, and broadcast storm caused by a monitoring protocol is avoided.

The invention discloses an address allocation method and electronic equipment, and relates to the technical field of address allocation, and the method comprises the steps: analyzing an electrical connection netlist, determining a plurality of link entities in a target link, constructing a link topology tree, and generating an address allocation rule set; determining logical addresses of a plurality of link entities; determining actual configuration addresses of a plurality of link entities; performing address conflict verification on the plurality of link entities based on the actually configured addresses and the logic addresses, and judging the link entities as address conflict entities if the link entities do not pass the address conflict verification; a set of modifiable variables and a set of minimum cost modification solutions are determined based on address information for the address conflicting entities. According to the method, the address can be automatically planned and allocated based on the electrical connection netlist, and conflict repair after address conflict verification is realized, so that the problems of insufficient utilization of address space, difficulty in timely discovery of path conflicts, low conflict positioning and repair efficiency and the like in related technologies are solved.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

Cache memory systems employing multiple-level hierarchy cache coherency architecture, and related methods and computer-readable media. A processor-based system includes separate dies that each have a processor and local cache memory logically forming a portion of global cache memory for a system address space. To provide a single point of cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point of cache coherency in the global cache memory. Thus, a cache coherency protocol based on a single point of cache coherency can be implemented. However, the proxy cache controller circuits are also capable of locally servicing memory requests solely within its die, when possible to maintain cache coherency, to provide lower latency memory transactions

The invention discloses a virtual machine monitor system for a resource-limited persistent memory server, which comprises a configuration file module, a CPU (Central Processing Unit) management module, a memory management module, a cache management module, an interrupt management module, a cross-partition communication module and a virtual machine management module. The CPU management module is used for binding a virtual CPU to a physical CPU core, so that computing resources of the virtual machines are dedicated, and meanwhile, the virtual machines are prevented from competing for the CPU; the memory management module is used for dividing a physical memory region according to a configuration file and realizing address space isolation between virtual machines by utilizing two-stage address translation; the cache management module is used for performing isolation control on cache access of a plurality of virtual machines through a coloring mechanism of the last-level cache; and the interrupt management module is used for simulating the universal interrupt controller, and the virtual machine monitor re-injects the interrupt into the target virtual machine according to the configuration file after capturing the hardware interrupt.

The invention provides a data interaction method and a related device, and relates to the technical field of automatic control. The method comprises the following steps: receiving a first configuration parameter of a target input / output module sent by a target communication protocol master station; the data length of the configuration parameters sent by the target communication protocol master station and the address space size of the configuration object dictionary about the input / output module in the device description file based on the coupler are uniformly aligned to the target data length; determining the actual data length of the configuration parameters of the target input / output module according to a preset configuration table; and analyzing the first configuration parameter according to the actual data length of the configuration parameter of the target input / output module to obtain a second configuration parameter which can be identified by the target input / output module, and sending the second configuration parameter to the target input / output module. According to the technical scheme provided by the invention, the problem of how to realize flexible configuration of the rear-end input / output module in the prior art can be solved.

The embodiment of the invention discloses a communication method, device and equipment between Jailhouse virtual machines and a medium, and the method comprises the steps: adding a VNIC module in a Jailhouse source code, and enabling the VNIC module to analyze VNIC configuration and achieve address space mapping, thereby achieving the management of the VNIC; modifying a device tree file of each virtual machine operating system, and adding a memory retention statement which is used for address mapping of the VNIC; driving compatible information is added in the device tree file of each virtual machine operating system, a virtual area mapped by the VNIC is registered based on the memory reservation declaration, and a VNIC interrupt signal is configured; setting a VNIC MAC address in the device tree file according to the number of the virtual machine, and setting a specific bit of the MAC address as the number of the virtual machine for identifying a node to which the communication data flow belongs; and according to the VNIC interrupt signal of the device tree file, modifying an interrupt signal in a memory registration structure body in the configuration file to be consistent with the VNIC interrupt signal of the device tree file, and correspondingly setting an actual memory region mapped by the virtual region.

The invention relates to the technical field of real-time data statistics, and discloses a real-time data statistics method and system.The method comprises the steps that the total memory space size is calculated based on the number of ports of a switch, a shared memory area is applied through a unique key value of the system, and the shared memory area is mapped to a process address space; creating a timer object, and when the period of the timer object expires, triggering a callback function and writing the read statistical data into the shared memory area; and when the front-end application module receives a statistical data acquisition request, calling an access interface function to directly read the port statistical data from a memory address corresponding to the shared memory region. Decoupling of collection and access of port statistical data is achieved, the method is suitable for a network monitoring scene needing high-frequency refreshing of statistical information, and user experience is effectively improved.

Methods are provided comprising: mapping a portion of a local primary memory to an address space of a virtualization instance at a client device, wherein the address space is addressable by a processor of the client device, and wherein the virtualization instance is executed via the processor of the client device; mapping a first portion of external memory to the address space, wherein the external memory is memory that is external to the client device but treated as primary memory at the client device, and wherein a second portion of the external memory is not in any address space addressable by the processor of the client device; providing a performance indication data structure indicating a performance difference between the portion of the local primary memory mapped to the address space and the first portion of external memory mapped to the address space; and causing data to migrate between the external memory and the local primary memory based on the performance indication data structure by the virtualization instance, wherein the data is caused to migrate by the virtualization instance and / or a logic configured to operate with the virtualization instance.

An example method of performing data recovery after a die failure in a memory device includes: identifying, among a plurality of dies of the memory device, a first die experiencing a failure; identifying, by iterating over an address space associated with the first die, a valid data item stored on the first die; responsive to determining that a data recovery workload condition is satisfied, recovering the valid data item; and storing the valid data item on a second die of the plurality of dies.

The invention provides a memory mapping verification method, a management controller, a system and a medium, and relates to the technical field of computers. In the invention, in order to map the memory space of the management controller, a host needs to send an address space remapping request to the management controller, and the request needs to contain information to be verified and address information to be mapped. The management controller can verify the to-be-verified information and the to-be-mapped address information, and only when the to-be-verified information passes verification and a target memory area corresponding to the to-be-mapped address information in a memory of the management controller is located in a preset mappable area, a confirmation response is sent to the host, and the host is allowed to perform address remapping on the target memory area. Therefore, the host can be prevented from randomly accessing any memory area of the management controller, and the security of accessing the memory of the management controller by the host can be improved.

Cache memory systems employing a multi-level hierarchy cache coherency architecture, and related methods and computer readable media. A processor-based system includes multiple independent dies, each die having a processor and a local cache memory that logically forms part of a global cache memory in a system address space. To provide single point cache coherency in the global cache memory, the processor-based system includes a proxy cache controller circuit in each die, and a global cache controller circuit. The global cache controller circuit can communicate with the proxy cache controller circuits to maintain single point cache coherency in the global cache memory. Thus, a single point cache coherency protocol can be implemented. However, the proxy cache controller circuits can also be able to locally service memory requests within their own die only, to provide lower latency memory transactions, while still being able to maintain cache coherency.

A simple configuration aims to reduce MCU vulnerabilities. [Solution] The control device 10 includes an MCU 20. The MCU 20 has a CPU 22, a system bus 26, a storage device 28, and an address translation device 24 that translates addresses between the CPU address space of the CPU 22 and the system bus address space of the system bus 26 in accordance with translation rules set in a special function register 24A. The MCU 20 starts up in an unrestricted mode in which all addresses in the CPU address space are available, and after startup, when a predetermined condition is met, it switches to a restricted mode in which only a portion of the addresses in the CPU address space are available. The special function register 24A allows the translation rules to be set and read when in the unrestricted mode, and does not allow the translation rules to be set or read when in the restricted mode.

In order to solve the problem that under the condition that a PMON program is not changed, the PMON program cannot provide inter-core memory isolation through two addresses of 0 * 8000000000000000 and 0 * 9000000000000000 configured by a direct mapping configuration window, the AMP architecture multi-core real-time operating system deployment method capable of meeting the inter-core memory isolation is designed on a Loongson platform. According to the multi-core deployment method for the AMP architecture operating system based on the Loongson platform disclosed by the invention, by designing a secondary bootstrap program, the mode that a PMON program directly loads an operating system mirror image is changed into the mode that the secondary bootstrap program is firstly loaded, and the operating system is started by the secondary bootstrap program. The secondary bootstrap program configures the MMU through a page table mapping address translation mode, so that operating systems between different cores can run in different address spaces, and an isolated running environment is provided. Once a certain operating system accesses the address space of other core operating systems, the system will report TLB refilling exceptions to prevent other core memories from being damaged, and therefore the inter-core memory isolation is achieved.

The application provides a device and working method for AI chip system architecture verification, including a control center for logic control, timing coordination and data interaction of each module. A pulse writing module generates a writing signal with a special pulse form to realize state programming and conduct adjustment of storage or computing devices. A programming selection module accepts the signal of the pulse writing module, supports the structure requirements of various different memory devices of the measured unit, and performs different selective writing according to different array structures. A decoding module accepts the signal of the programming selection module and the feedback signal of the measured unit to be read, and is used for address space mapping, excitation line management and signal on-off control. The measured unit accepts the writing signal of the decoding module and feeds back the reading signal to the decoding module, and is used for storing neural network weights, logic states or continuous conduct grades. The application provides key test support and decision basis for AI chip system architecture research.

The invention provides an address space management method and a secure container, and relates to the technical field of computers.The method comprises the steps that a two-stage address translation page table EPT corresponding to at least one LibOS process in at least one container instance is constructed; each EPT is used for representing a mapping relation between a user physical address corresponding to each LibOS process and a real physical address so as to construct a mutually isolated virtual address space between different LibOS processes; and based on the VMFUNC instruction, switching the EPT corresponding to the current LibOS process in a user mode so as to switch to the EPT corresponding to the target LibOS process. According to the method, security isolation of multiple LibOS process address spaces can be realized; meanwhile, address space view switching is completed in a user mode by using a VMFUNC instruction, high-performance overhead brought by VM-Exit and system calling is completely avoided, and extremely-low-delay and high-efficiency process and instance switching is achieved.

The invention discloses a dead operation processing method, device and equipment, a medium and a product. The method comprises the following steps: acquiring job names of business jobs of host jobs where current supervision jobs are located from a job address space of a host; based on the job name of each business job, determining the running state and running information of each business job through a host assembly table; and according to the operation state and the operation information, determining a dead service job in each service job. According to the embodiment of the invention, efficient processing of the dead business operation can be realized.

The application discloses a stability test method, device, equipment and storage medium of a DRAM particle. The method comprises the following steps: restarting a test system for a preset number of times, executing a preset test strategy in a universal boot loader stage of each test system starting process, the preset test strategy comprising the following steps: enabling a CPU cache, and configuring the CPU to access the DRAM particle in a non-burst transmission mode; based on hardware configuration information of the DRAM particle, allocating at least two test areas in an address space of the DRAM particle; traversing each working frequency supported by the test system, testing the read-write stability of the DRAM particle in direct read-write under each working frequency based on the at least two test areas, and testing the read-write stability of the DRAM particle after the test system enters a sleep mode and wakes up under each working frequency. The application has the technical effect of providing sufficient test pressure by using the CPU cache and avoiding external interference after the system is completely started, and effectively improves the comprehensiveness and accuracy of the DRAM particle stability test.

This application discloses an instruction processing method, an information processing unit, a chip, and a chip system. The instruction processing method introduces instruction-based encapsulation, mapping, and parsing operations. This allows the first chip to access the memory cells of the second chip without directly overwriting the second chip's large memory address space during the mapping stage. Instead, it encapsulates a data packet based on the target instruction, writes this data packet to the second information processing unit of the second chip through mapping by the switching unit, and then parses it to trigger the actual access to the memory cell. This method occupies only a small mapping address space to complete cross-chip interaction. Compared to existing direct mapping access methods, it effectively reduces mapping space usage, avoids reliance on large BAR spaces or frequent sliding window mechanisms, and improves the applicability, scalability, and processing efficiency of the instruction processing method.

The present application provides a kind of data processing method and data processing device, electronic equipment and non-transient computer readable storage medium, the method includes in response to the decompression instruction of data, the check of received compressed data is executed;In the case where check passes, according to the preset continuous data length, the compressed data is divided into multiple data segments, wherein the compressed data is compressed according to the preset continuous data length;The decompression operation of the multiple data segments in the preset address space is respectively executed, and the decompressed data is obtained;Whether the decompressed data is consistent with the data amount of the original data corresponding to the compressed data is compared;In the case where data amount is consistent, the decompression task of the compressed data is ended.According to embodiment, by dividing compressed data into multiple data segments and performing double check on decompressed data, not only the accuracy of data decoding is improved, but also the speed and efficiency of decompression are improved.