137 results about "Checksum" patented technology

This invention discloses a bypass transmission architecture for encrypted network interface cards (NICs) based on parallel feature extraction. The architecture includes: a packet stream input interface, a control path unit, a data path unit, a decision window merging unit, a fragmentation-aware incremental checksum correction engine unit, and a security control unit. This invention can reduce forwarding latency, improve transmission determinism and resource utilization, and enhance packet forwarding efficiency in high-speed network scenarios. By using a deterministic delay storage module that matches worst-case latency, timing synchronization between control flow and data flow is achieved, reducing the risk of timing races and rule misjudgments. Simultaneously, the fragmentation-aware incremental checksum correction engine reduces the risks of insufficient fragmentation packet compatibility, checksum miscalculations, and resulting packet loss in traditional solutions.

This invention discloses a dynamic checksum extraction circuit construction method for neutral atom quantum computing, belonging to the field of quantum computing technology. It includes: a checksum extraction construction module library generation unit, used to traverse the parameterized checksum extraction circuit space, generate candidate circuits based on the evolution logic of the qubit detection region, and select effective circuits; an offline circuit characteristic characterization unit, used to perform structural screening and preliminary performance screening of effective circuits to obtain feasible circuits, and to characterize the atomic loss tolerance of feasible circuits, generating a loss tolerance distribution for each feasible circuit on the surface code plane; and an online dynamic circuit construction unit, used to calculate the fitness score of each feasible circuit based on the measured atomic loss position and the loss tolerance distribution, dynamically selecting the optimal circuit as the next round of checksum extraction circuit. This invention can dynamically match atomic loss patterns without increasing circuit overhead, effectively suppressing atomic loss errors and improving fault tolerance performance.

The disclosure provides a database consistency verification method and device, electronic equipment and computer readable storage medium, and relates to the field of databases. The database consistency verification method comprises: in response to a verification instruction, performing a verification operation on a first backup library and a second backup library based on a checksum algorithm, wherein a reference code is generated based on the verification operation for the first backup library, and a verification code is generated based on the verification operation for the second backup library; determining the consistency between the first backup library and the second backup library based on the comparison result of the reference code and the verification code; and determining the consistency between the master library and the backup library based on the consistency between the first backup library and the second backup library. Through the technical scheme of the disclosure, the consistency verification can be performed while ensuring the normal operation of the master library, which is conducive to reducing the probability of intrusion into the database, thereby ensuring the high availability and strong consistency of the database.

The application discloses a kind of based on mechanical processing work order verification and intelligent completion method of multi-agent cooperation, comprising: obtaining the multi-source heterogeneous data of mechanical processing field, process semantic embedding model is trained using knowledge distillation technology, extract hidden space representation and construct processing cognitive atlas;Establish a multi-agent collaborative framework, multi-dimensional analysis is carried out on the original work order data, and a multi-layer semantic hypergraph is generated;Based on the process cognitive atlas and the multi-layer semantic hypergraph, the process causal diagram of the work order to be checked is constructed, the processing result distribution is predicted by intervention calculation, and the risk contribution degree is quantified, the root cause elements are located to generate the work order verification report;With the verification report and physical constraint as input, the diffusion model is used for conditional generation and simulation of different decision preferences, and the work completion decision reasoning path set is obtained;Generate candidate completion work order, optimize abnormal scheme through digital twin rehearsal, finally filter and generate the mechanical processing work order that passes verification and completion, improve the efficiency and accuracy of data import.

The application discloses a remote online upgrading method and device of a programmable logic device and a medium, wherein a basic firmware area and a use firmware area which do not overlap each other are divided in a FLASH storage space; a host computer cuts a program to be upgraded into fixed frames, and then continuously sends the frames to an FPGA through a high-speed serial interface; the FPGA decodes the frames through an internal GTX high-speed transceiver according to a preset protocol, obtains continuous effective program data, and buffers the data in an on-chip ROM buffer area; a first-erasing-then-writing operation is performed on the FLASH, and the first-erasing-then-writing operation is checked; through double-mirror management of two programs, a timeout trigger is monitored to trigger a rollback to ensure that a basic function of the program can be run; data is transmitted by using the GTX to accelerate the upgrading speed, and the transmission is ensured to be complete through a CRC check and a retransmission mechanism; a pipeline type data transmission is realized through a ping-pong buffer structure; and the upgrading reliability is increased by comparing FLASH writing data.

This invention discloses a power-loss protection method for the FATFS file system, which is applied to an embedded file storage system using non-volatile memory as the storage medium. The power-loss protection is achieved solely through computer programming technology, and includes the following steps: S1, allocating a region in the file storage medium as a backup area for file write operations; S2, when the file system performs a write operation on any sector in the storage medium, before executing the erase operation on that sector, reading the data of that sector and saving it to the backup area; S3, calculating the CRC checksum, saving the CRC checksum and the sector number of the sector together to the backup area, making the data in the backup area valid; S4, executing the erase operation on the sector to complete the data writing; S5, after completing the writing of the data in that sector, invalidating the data in the backup area; S6, when the embedded file system is powered on again, checking whether the data in the backup area is valid, and if valid, restoring the sector data saved in the backup area and writing it back to the corresponding sector.

This invention discloses an attack tracing method and system for end-to-end data transmission in optical communication, belonging to the field of optical fiber communication technology. The method includes: processing an initial key value using a hash function and DNA encoding to generate a DNA sequence; concatenating the DNA sequence to generate a session key and calculating its hash value; calculating a single-byte XOR checksum of the original data to generate extended data, generating ciphertext based on the extended data, and calculating a digest of the ciphertext; decrypting the ciphertext and performing XOR checksum consistency verification to obtain an event digest; calculating a root hash based on the key digest, parameter digest, ciphertext digest, and event digest, storing the root hash in the block header, and performing attack tracing on the block header to obtain the attack tracing result. This invention introduces four-dimensional chaos and DNA encoding to generate a high-entropy key, dynamically storing and updating the key through blockchain, while simultaneously achieving single-root verifiable attack tracing and quickly locating problematic nodes.

This invention discloses a method for covert processing of spaceborne signals based on Tent mapping, relating to the field of signal processing. In this invention, the transmitter generates a chaotic Tent sequence, which is then transformed by Box-Muller to obtain a Gaussian-distributed first interference signal. The chaotic sequence and the first interference signal are equally divided, and an identification signal containing a synchronization flag and a checksum is constructed based on the quantization value of the first data point of each chaotic sequence segment. An amplitude adjustment coefficient is determined for each segment of the target signal, and the adjusted first interference signal of each segment is superimposed with the corresponding segment of the target signal to obtain a mixed subsequence. An identification signal is added before each mixed subsequence to form a relay signal. At the receiver, a sliding window is used to match the synchronization flag in the received signal to locate the identification signal, the quantization value at the beginning of each segment is parsed, and a second interference subsequence is independently reconstructed. A coarse estimate is obtained by performing a two-dimensional correlation between time delay and frequency offset, and the received target signal is obtained through interference subspace projection cancellation. The method proposed in this invention has low hardware overhead, strong anti-interception capability, and high cancellation accuracy.

The application provides a quick recovery method for file system error caused by abnormal power-off. The method comprises: executing power-on starting flow to determine whether the file system has error, if error occurs, entering abnormal recovery flow; in response to the instruction of entering abnormal recovery flow, determining whether the TAB file is abnormal, if abnormal, continuing to determine, if the TAB_A file checksum verification error, deleting and rebuilding the TAB_A file, copying the TAB_B file to the TAB_A file, and ending the current flow; if the TAB_B file checksum verification error, deleting and rebuilding the TAB_B file, copying the TAB_A file to the TAB_B file, and ending the current flow; if the TAB file is normal, entering the clearing fault user file flow, deleting the corresponding entry information in the TAB_A file and the TAB_B file after completing the flow, and ending the abnormal recovery flow. According to the application, the problem of affecting system performance of the existing abnormal power-off recovery method applied to the file system can be solved.

The application discloses a multi-window display optimization method for an Android application of a Hongmeng platform, and the method comprises the following steps: after an Android container is started, a first shared memory containing multiple partitions is created on the Hongmeng side; when an Android application component is started, the component ID is allocated and bound, the GLES resource is configured, the double-buffer queue and the GLES context are created, the shared image resource handle is generated, and the mapping table of the component ID, the window ID and the texture identification is established; when the component is rendered, the context and the component ID are checked; after the pixel data is rendered, the differential area is calculated and the first data and the checksum are generated and processed; the data header and the first data are written into the shared memory partition, and the Hongmeng side is informed; after the Hongmeng side is verified, the information is extracted to generate the texture identification and the associated Surface buffer; finally, the Android and Hongmeng window data are synthesized and submitted to the display hardware to complete the on-screen display.

According to various embodiments, a data processing device is described which includes a Boolean masked addition processor designed to perform Boolean masked addition and a fault protection circuit designed to generate a checksum for a first part, generate a second checksum part, compare the first checksum part with the second checksum part, and trigger a safety action in response to a mismatch between the first checksum part and the second checksum part.

This application relates to the field of data processing technology and provides a method for changing device parameters, a terminal device, and a storage medium. The method includes: obtaining a user request; obtaining parameter information of the target device based on the user request; performing a feasibility analysis on the user request based on the parameter information to obtain a parameter description of the target parameter to be modified, including a functional explanation of the target parameter and a recommended modification value; processing the target parameter according to the recommended modification value, including at least one of parameter verification and normalization processing, to obtain updated data corresponding to the target parameter; and sending a change instruction to the target device to instruct the target device to update the stored data of the target parameter according to the changed data. The user only needs to input a user request, and the terminal device automatically completes the change of device parameters, enabling faster and more accurate parameter changes.

The application relates to the technical field of power load regulation, and discloses a method and system for dynamic scheduling of charging pile power. The method comprises the following steps: obtaining a real-time data sequence containing a basic load and a charging pile load, and obtaining a load fluctuation trend after denoising by using a Kalman filtering algorithm; calculating an instantaneous change rate of the basic load, and determining a power offset amount that needs to be compensated on the charging pile side when the instantaneous change rate exceeds a preset change threshold; inputting the power offset amount into a proportional-integral-derivative control algorithm to generate a preliminary power scheduling instruction for each charging pile; verifying and amplitude correcting the preliminary power scheduling instruction in combination with an upper limit of a total load of a transformer area to obtain an optimized power scheduling instruction; controlling each charging pile to adjust output power, generating a scheduled total load curve and performing stability verification; and when a verification result does not satisfy a preset safety threshold, updating Kalman filtering algorithm parameters and using the updated Kalman filtering algorithm parameters for subsequent real-time data processing. The method can improve the real-time performance, stability and safety of transformer area load regulation.

A system may include: an input unit providing a data structure storing a computer simulation model package; a first processing unit to store: a binary file or source code comprising a computer simulation model of the technical system; and a text file assigned to the model; a computing unit to derive a first checksum of the binary file or the source code; a second processing unit to store the first checksum in the text file; a generator to generate an instantiation function for verifying the model, run each time the model is instantiated and including: deriving a second checksum from the binary file or source code stored in the package; comparing the second checksum with the first; and generating a comparison result; a third processing unit to store the instantiation function in the data structure as part of the package; and an output to provide the package.

This application relates to a data transmission method, apparatus, computer equipment, storage medium, and program product. The method includes: receiving a first data packet, the first data packet including a first checksum; verifying the first data packet according to the first checksum to obtain a verification result; if the verification result indicates a failed verification, determining a second data packet based on the first data packet, and sending the second data packet to the next node of the target node or storing the second data packet. This method can improve the data packet transmission efficiency.

This invention discloses a cross-language network message encapsulation method based on function signatures, belonging to the field of cross-language network message encapsulation technology, including the following steps: S1, function signature parsing; S2, parameter preparation; S3, intelligent serialization; S4, message header assembly; S5, checksum calculation; S6, message assembly and transmission; S7, cross-language parsing. This cross-language network message encapsulation method based on function signatures uses the high 3 bits of the first byte to identify the data type and the low 5 bits to store control information or decimal values, achieving optimal encoding for values ​​in different ranges. It also maintains an independent string cache table for each communication session, with strings as keys and unique integers as indexes. When transmitting a string for the first time, the index and string are transmitted simultaneously; when transmitting the same string subsequently, only the index is transmitted, allowing the receiving end to quickly look up and restore the string, significantly reducing the amount of duplicate strings transmitted.

This invention discloses a multi-tenant end-to-end data security isolation and control system and method, belonging to the field of vehicle network data security. It aims to solve the problems of easy data crosstalk, discontinuous isolation, unreliable trust benchmarks, and difficulty in compliance traceability in multi-tenant scenarios. The system generates a tenant root identifier (TID) for vehicle enterprise tenants, which, together with the device sub-identifier (DID), forms a tenant identifier chain. This chain is synchronized with a trusted authentication center to establish a vehicle-cloud hardware-level trust root. When the vehicle terminal accesses the system, it completes two-way identity authentication and allocates a dedicated message queue telemetry transmission MQTT topic partition and access permissions according to the TID. The terminal collects time-series vehicle control data and generates encrypted data frames with intrinsic identifiers and checksums for uploading. The access gateway performs dual isolation verification before transparent transmission. Data is forwarded to an independent logical storage partition for isolated storage according to the TID. This invention achieves strong hardware-level isolation, real-time verification, and full traceability throughout the entire end-to-cloud chain, effectively preventing cross-tenant data leakage.

This application relates to the technical field of Computer Numerical Control (NC) systems, specifically to a method, system, device, and storage medium for preventing NC file misloading. The method includes: acquiring an NC file; rendering a two-dimensional preview image in a CAM (Computer-Aided Design) system; converting the two-dimensional preview image into image-encoded data and calculating a first checksum of the NC file according to a preset verification algorithm; determining metadata blocks, adding start and end identifiers to the beginning and end of the metadata blocks respectively, and writing the metadata blocks into the header of the NC file; scanning the file header, extracting the metadata blocks based on the start and end identifiers, and parsing the image-encoded data and the first checksum from the metadata blocks; calculating a second checksum using a preset verification algorithm, and comparing the second checksum with the first checksum. This method can effectively prevent equipment damage or material waste caused by corrupted or maliciously modified NC files.

This application discloses a method, device, electronic device, storage medium, and vehicle for verifying data in an in-vehicle system. The method includes: dividing the software and data in the in-vehicle system into data blocks; performing hash calculations on the data blocks to generate and store hash values; using the hash values ​​as leaf nodes of a Merkle tree to construct the Merkle tree; periodically calculating and verifying the checksum of the Merkle tree during the operation of the in-vehicle system; determining whether the currently calculated checksum matches the previously calculated checksum; if the currently calculated checksum does not match the previously calculated checksum, then reinstalling the system or repairing the data. Through this scheme, data is divided into blocks, and the objects of data verification are set, giving data comparison and verification clear boundaries and directions. The combination of hash algorithms and Merkle tree algorithms facilitates the identification of data matching status and enhances the ability to identify whether data is abnormal.

This invention relates to the field of industrial automation control technology, specifically an AnyControl-based IEC61131-3 controller extension module. It includes a four-layer local extended control architecture consisting of an AnyControl Runtime main control module, an extended communication protocol module, an FPGA communication module, and extension modules. The DI / DO, AI / AO, CAN, and UART interfaces are encapsulated as standardized configuration devices. Standard data frames are designed, including frame header identifiers, address fields, data length, valid data, and CRC16 checksums. A high-speed FPGA data transmission channel is built based on the SPI protocol and LVDS interface, with a transmission rate of no less than 100Mbps, supporting up to 32 cascaded extension modules. Configuration device integration and automatic variable mapping are achieved using XML description files, enabling seamless access to extension modules. Simultaneously, the extended CAN and UART interfaces are mapped as virtual interfaces for localized adaptation. This invention offers high module compatibility, stable data transmission, user-friendly operation, and strong system maintainability and scalability.

This invention discloses a checksum update method, apparatus, electronic device, storage medium, and product, relating to the field of data storage technology. The checksum update method includes: determining a checksum pair of data to be updated, a data identifier, and the current checksum of the disk; splitting the current checksum according to a preset bit width to obtain split checksum components, and splitting the checksum pair to obtain data checksum components; and incrementally updating the checksum components based on the checksum components, the data checksum components, and the data identifier to obtain a new checksum for the disk. This invention enables incremental checksum updates, eliminating the need to reread all data on the disk, significantly reducing data read / write operations and computational overhead, and improving checksum update efficiency in storage scenarios.

This invention discloses a method and device for intelligent address completion, verification, and fraud analysis. The method includes semantic parsing and structural reconstruction of unstructured address information input by the user, outputting standardized address data with a unified format; using a large language model to perform compliance verification and semantic cleansing on the standardized address data; collecting the user's dynamic operation trajectory and filling logs during the address input process, and combining user attributes, machine learning algorithms, and the large language model to mine abnormal behavior patterns. This invention combines multi-pattern string matching, large language model semantic understanding, and machine learning behavior modeling techniques, combined with the data and business characteristics of the consumer finance field, to construct a complete implementation solution for standardizing customer address information and identifying fraud in the consumer finance field, addressing challenges such as incomplete and non-standardized address information, difficulty in verifying authenticity, and strong concealment of fraudulent behavior in high-concurrency scenarios.

The application provides a unit test case automatic generation method and device based on preferred iteration feedback, which comprises the following steps: setting a target module identifier and a target code coverage rate of a test case to be generated; extracting source code of the target module and necessary reference code; encapsulating the source code of the target module, the necessary reference code, a project status, a requirement description and feedback information into a template prompt word, inputting the template prompt word into an AI model to generate a unit test case; performing iteration legality verification and / or correction on the generated unit test case until the unit test case passes the compilation; executing the test case that passes the compilation to obtain a current code coverage rate and un-covered code information; judging whether the code coverage rate of the unit test case that passes the compilation is greater than a cached historical highest coverage rate; and judging whether the code coverage rate of the highest coverage rate test case obtained is greater than the target code coverage rate. The application can efficiently generate a unit test case with high quality, high coverage rate and operability.

This invention relates to an LDPC code decoding method for BeiDou satellite navigation, comprising: Step S1, the receiving end accumulates the output values ​​corresponding to each bit in the codeword generated by the LDPC-CRC concatenated code encoding in the tracking loop to form a corresponding receiving vector; Step S2, performing bit-by-bit hard decision on the receiving vector to obtain a hard decision vector; Step S3, calculating the checksum of the hard decision using a parity check matrix transformed from a 64-element field to a 2-element field to determine whether the hard decision vector includes error bit information; Step S4, when error bit information appears in the hard decision vector, performing LDPC iterative decoding using a bit-flipping algorithm in the 2-element field, iteratively updating the error bits in the hard decision vector according to the error correction vector until the iteration termination condition is met, outputting the decoding result or discarding the receiving vector. This invention reduces decoding complexity and is suitable for practical applications.

The application discloses a substation full-link data management system and method based on source end modeling, relates to the technical field of substation data management, and generates an initial digital model according to substation design drawings and a device parameter list; performs semantic checking and logical consistency checking on the initial digital model by adopting a modeling standard, verifies the rationality of the device by a rule engine; collects a plurality of angle image sequences of a terminal row, analyzes image frequency domain features and space domain features, and analyzes the connection logical relationship of the terminal row; establishes a feature space of device parameters, identifies the difference between entities and the digital model by calculating parameter distribution similarity and topological structure consistency indexes, and marks matching abnormal devices; constructs an influence correlation model between the matching abnormal devices and the influence degree, and generates a correction instruction according to a difference influence factor. The prediction accuracy of the difference occurrence probability is improved.

This invention discloses a method and device for detecting lost RFID target tags in open scenarios. The method, based on an open-scenario RFID system model and the problem definition of tag loss detection, performs an initial round of tag screening using a first filter based on index and a second filter based on sorting. Active tags send their ID checksums, and the number of unexpected tags is estimated. In subsequent rounds, a third filter based on fingerprints is introduced to filter interference. Tags combine the three filters to determine their activity status and recognition eligibility and send a response. Finally, the recognition accuracy is verified, and the process terminates if requirements are met or the maximum number of rounds is reached. If a tag loss is detected, an alarm is triggered promptly. This invention, through multi-filter, multi-round collaborative screening, effectively eliminates interference from unexpected tags, improving the efficiency and accuracy of lost tag identification in open scenarios. It is applicable to asset supervision in various open scenarios such as open-air storage, logistics transit, and open exhibitions.

1. Name of the product in this design: Package (Neiqiu Shenma). 2. Purpose of this design: to carry small items, such as keys, coins, cards, etc. 3. The key design elements of this product are the combination of shape, pattern, and color. 4. The image or photograph that best illustrates the design's key points: a 3D model. 5. The design for which protection is sought includes color. 6. This design is for a thin product, therefore the left view, right view, top view, and bottom view are omitted.

This invention relates to the field of storage technology and discloses a method for storing verification data in a cache device. The method includes: receiving a write request for a target logical address; performing feature extraction operations on the target logical address to generate a rotation displacement factor; traversing multiple candidate data paths within the cache group and calculating the physical index value of the corresponding candidate verification path using its physical index value and the rotation displacement factor; detecting the occupancy status of the candidate data paths and their corresponding candidate verification path physical index values; determining the target data path and the target verification path based on the occupancy status; and writing the data and the generated checksum into the target data path and the target verification path, respectively. This invention establishes a strong mapping between the verification storage location and the logical address, forcibly triggering verification failure when the address addressing is incorrect, preventing silent errors, and improving the storage security of verification data in the cache device.

Methods and systems for improving performance of a decoder in a memory device are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, and determining, based on the noisy codeword, a ones count and a checksum. The method further includes determining, based on the ones count and the checksum, an asymmetric ratio, a first log-likelihood ratio (LLR) value indicative of a bit being zero-valued, and a second LLR value indicative of the bit being one-valued. Then, the method includes generating an LLR sequence by applying the first LLR value and the second LLR value to each element of the noisy codeword, and performing a hard decoding operation on the LLR sequence to generate a candidate version of the transmitted codeword. An example system implements the above-described method using one or more processors.

This invention proposes a high-performance collaborative processing method for ultra-high precision pointing measuring instruments. It consists of a master-slave processor. The master processor ensures periodic update rates through external communication, while the slave processor handles complex algorithms and transmits results to the master to improve its real-time algorithm performance. The master software is designed with a multi-task architecture to ensure real-time performance. A "master-slave interaction task" is periodically initiated, triggering a data reception interrupt on the slave and completing master-slave data interaction. Other tasks handle real-time algorithms and communication. The master-slave interaction task has a timeout exit mechanism, and its execution is determined by the timeout status of other tasks at the timed start. To ensure data transmission reliability, the master-slave communication bus uses unidirectional transmission and reception to avoid transmission conflicts caused by duplex mode. Data transmission uses checksums, and data to be sent in multiple periods is packetized and assigned sequence numbers to avoid duplicate reception or data loss. This invention can be widely applied to embedded platforms using a master-slave dual-processor architecture.