255 results about "Programmable logic device" patented technology

The invention provides a cross-protocol identification data intelligent analysis middleware method and system. The method comprises the following steps: taking multiple industrial communication protocol identifiers in advance to form a metadata set, and constructing a protocol feature element model library containing a non-standard protocol feature template; a programmable logic device is introduced, physical layer signal waveform characteristics are matched, and corresponding communication protocol stacks are dynamically switched at a hardware level according to a matching result; receiving a communication data stream through an electric domain processing unit of the programmable logic device, and generating a protocol analysis logic sequence in combination with a state transition rule of the meta-model library and a mode matching rule of the protocol stack; performing combined operation on the structured feature template and the analysis logic sequence to generate an executable cross-protocol data analysis rule; and when unknown protocol characteristics are detected, triggering dynamic reconstruction of the template, so that the analysis rule is adapted to a newly added protocol. According to the technical scheme provided by the invention, the protocol compatibility development cost in an industrial multi-protocol scene is remarkably reduced.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving documentation and receiving a full text search. The documentation may include user guides, technical specifications, and design files such as HDL code, constraints, timing reports, and / or design assistant / rule violation (DRC) reports. The present disclosure also includes determining semantic search for embedding vectors based on the documentation and the full text search. Furthermore, the present disclosure includes providing the semantic search to a large language model (LLM).

The invention discloses a protocol conversion method and device, a medium and a server system, and relates to the technical field of servers. Once an original protocol type is determined, a dynamic interface routing controller calls a corresponding conversion program stored in a mapping table; and converting the detected heterogeneous bus protocol command into a unified single-line serial bus protocol operation code. As the conversion program and the protocol characteristics are stored in the mapping table, the method has infinite protocol expansion capability, a new protocol can be supported by updating the mapping table and a detection engine without redesigning hardware or modifying codes of an editable logic device, the system design is greatly simplified, and the development cost is reduced. Therefore, the problem that the current programmable logic device can only realize single interface protocol conversion is solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

Embodiments of the present application provide a server, a data transmission method for the server, and a storage medium. The server comprises an extended chip, a front-end I3C bus, and a first programmable logic device; the extended chip comprises a first master I3C interface; the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces; the front-end I3C bus is an I3C bus that connects the first master I3C interface to the first slave I3C interface; the front-end I3C bus is used for performing data transmission between the extended chip and the first programmable logic device; and the extended chip is used for performing data exchange with the first programmable logic device by means of the front-end I3C bus, so as to realize GPIO extension of the extended chip by means of the plurality of GPIO interfaces. The present application solves the problem in the related art of poor adaptability of input / output extension of a server, and achieves the effect of improving the adaptability of input / output extension of a server.

The invention provides an airborne task system comprehensive video display device and method, the system comprises a device main body, the device main body comprises a programmable logic device, a video processing unit, a cache memory and an internal bus; the programmable logic device is configured with a plurality of video interface drivers and data interface drivers and is used for receiving video streams and data streams from external equipment; the programmable logic device is configured to analyze a video stream and a data stream, extract image pixel information and sensor data, and cache the analyzed information to the cache memory; and the video processing unit is configured to read the information from the cache memory, perform fusion processing and video coding, generate a comprehensive display picture and output the comprehensive display picture to at least one display device. According to the comprehensive video display device provided by the invention, efficient processing and real-time display of multi-source airborne data are realized through a special hardware architecture, and the system compatibility and reliability are remarkably improved.

The embodiment of the invention provides a serial port debugging method and a circuit board, and the method comprises the steps: receiving a register access command transmitted by an upper computer through a target serial port, enabling a programmable logic device to directly respond to the register access command of the upper computer, and executing a target access operation on a target register of the programmable logic device, under the condition that the control component fails and cannot normally communicate, the state information of the control component can be obtained by accessing the target register, so that abnormal fault positioning is realized; and the register access result is fed back to the upper computer in real time through the target serial port and the programmable logic device, so that the detailed state information of the control part can be quickly obtained, and the technical problem of serial port debugging failure caused by failure positioning when the control part is abnormal in the prior art is solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.

The invention discloses a signal reading system and method for superconducting microwave multiplexing device detection, and belongs to the field of superconducting microwave multiplexing device detection, and the system comprises a server which can issue a detection configuration instruction to a signal board, receive and return detection data, operate detection software, execute spectrum analysis and data analysis, and generate a detection result; the signal board is provided with a circuit containing a programmable logic device, and the circuit can output accurate intermediate frequency signals and excitation current signals according to instructions of the server, processes output signals of the detected superconducting microwave multiplexing devices mixed by the frequency mixing board through a critical sampling filter bank algorithm to obtain detection data, and transmits the detection data back to the server; and the frequency mixing plate can perform up-conversion on the intermediate frequency signal generated by the signal plate to radio frequency to form a radio frequency detection signal, output the radio frequency detection signal to each detected superconducting microwave multiplexing device, perform down-conversion on the radio frequency response signal returned from each superconducting microwave multiplexing device to intermediate frequency, and output the radio frequency response signal to the signal plate. The system can detect the quality of the device with low computing resources.

The invention discloses an FPGA (Field Programmable Gate Array) configuration architecture and an application method thereof. The architecture comprises FILO modules, a local shared configuration memory area and a distributed parameter storage area established between adjacent FILO module clusters, wherein the distributed parameter storage area is specially used for caching key configuration data of a current task execution period; a configuration memory area is shared globally, a high-bandwidth configuration memory is integrated on the top layer of the FPGA architecture, and all reconfigurable parameter sets of the full task process are stored persistently. And adding a temporary stack pointer and setting a corresponding pointing area. The application method comprises the steps of global configuration preloading, local dynamic loading and FILO module execution. According to the method, the performance, the energy efficiency and the resource utilization rate of the FPGA in a lightweight and dynamic application scene are greatly improved. The method can be widely applied to the field of programmable logic device system structures.

To utilize unused or underutilized input and output pins without significantly impacting power consumption and die area, an adaptive logic module (ALM) of a programmable logic device can be implemented with an additional 2LUT to improve low function packing density and broad function mapping coverage. The 2LUT can also serve as a route-through to provide direct access to ALM registers with or without input inversion. The extended ALM can also utilize route-through configurations of the additional 2LUT to enhance the connectivity of the ALM inputs and outputs.

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

The utility model discloses a programmable logic device test experiment device, which relates to the field of logic device test experiments and comprises a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power supply generation circuit and a liquid crystal display control circuit. According to the experimental device for testing the programmable logic device, through a mode of combining the liquid crystal display screen and the FPGA function test board, a large-scale test machine in traditional test equipment is omitted, so that a test system is more portable, comprehensive coverage test of FPGA chip functions can be realized through compiling a plurality of self-test programs, and the test efficiency is improved. Therefore, not only can the basic logic function of the FPGA be tested, but also the advanced characteristics and boundary conditions of the FPGA can be deeply verified, so that the function correctness of the FPGA chip can be more comprehensively ensured.

A system or method of the present disclosure may provide an electronic device comprising: a memory (504) storing instructions; and a processor (502) that, when executed, is to receive a programmable fabric design of an integrated circuit device (12). The instructions are further to cause the processor (502) to cause the design to be compiled into a configuration (20) during a compilation window. The instructions are further to cause the processor (502) to determine at least some routes (108) of the configuration (20) outside the compilation window.

Techniques are described herein in which a programmable logic device (PLD) is integrated into a baseboard management controller (BMC). A programming-enhanced BMC is powered on by a PLD that is integrated into the programming-enhanced BMC and that is coupled to an internal bus of the programming-enhanced BMC. A configuration file is provided from immutable BMC hardware in the BMC to the PLD based at least on the programming-enhanced BMC being powered on. The configuration file specifies a configuration to be programmatically applied to programmable hardware of the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which causes the programmable hardware to render a peripheral interface that is defined by the configuration file natively on the internal bus of the programming-enhanced BMC.

The invention discloses an NVMe data recording method and system based on an FPGA and a medium. Relates to the technical field of data management. The system is improved on the basis of a traditional NVMe system architecture, a CPU is realized by a programmable logic device FPGA, the system complexity is reduced, and an application is separated from an operating system; meanwhile, based on the characteristics of high flexibility and high-precision timing of the FPGA, the application efficiency of the PCIE interface and the NVMe protocol message is improved, the bandwidth waste is reduced, and the timing system can quickly complete receiving and transmitting of the NVMe protocol message with high precision; according to the NVMe data recording system, method and equipment, synchronization and parallel storage of data of multiple NVMe channels are completed based on the multi-channel synchronization function, the data recording bandwidth is improved, and lightweight high-performance, high-throughput and low-delay SSD read-write is achieved in applications needing high-bandwidth data storage and recording.

The application discloses a remote online upgrading method and device of a programmable logic device and a medium, wherein a basic firmware area and a use firmware area which do not overlap each other are divided in a FLASH storage space; a host computer cuts a program to be upgraded into fixed frames, and then continuously sends the frames to an FPGA through a high-speed serial interface; the FPGA decodes the frames through an internal GTX high-speed transceiver according to a preset protocol, obtains continuous effective program data, and buffers the data in an on-chip ROM buffer area; a first-erasing-then-writing operation is performed on the FLASH, and the first-erasing-then-writing operation is checked; through double-mirror management of two programs, a timeout trigger is monitored to trigger a rollback to ensure that a basic function of the program can be run; data is transmitted by using the GTX to accelerate the upgrading speed, and the transmission is ensured to be complete through a CRC check and a retransmission mechanism; a pipeline type data transmission is realized through a ping-pong buffer structure; and the upgrading reliability is increased by comparing FLASH writing data.

Various techniques are provided to efficiently synchronize clock and data signals in programmable logic devices (PLDs). A method includes configuring a programmable logic device (PLD) having a fabric of programmable logic blocks arranged in a plurality of regions; routing data carry chains in a first direction across the fabric to each of the plurality of regions; placing global clock circuitry at a first edge of the PLD; and routing the global clock to a corresponding first edge of each region via a global clock trunk and a plurality of clock branches, the global clock trunk propagating the global clock signal across the fabric and in each region, in the same direction as the data carry chains.

The invention relates to a chip verification method and system based on a double-FPGA architecture, and the method comprises the steps: deploying a verification platform on a first programmable logic device in a hardware circuit form, deploying a tested design on a second programmable logic device, and enabling the verification platform and the second programmable logic device to be interconnected through a hardware interface; the first programmable logic device comprises a control module, an excitation generation module, an expectation calculation module, an evaluation module, an excitation output module and a response input module; in response to external triggering, the control module jumps from idle to start, controls the excitation generation module to generate excitation, and transmits the excitation to the tested design through the excitation output module; the tested design generates a response signal based on excitation and transmits the response signal to the evaluation module through the response input module; the expectation calculation module receives an excitation calculation expectation result and transmits the result to the evaluation module; and the evaluation module compares the response with the expected result to generate a verification result. The method gets rid of software simulation dependence, shortens verification starting time, is close to a real chip use environment, and improves function verification reliability.

The embodiment of the invention provides a signal time delay control method and device, equipment and a storage medium, and relates to the technical field of signal processing. The method comprises the following steps: in response to a signal sending instruction initiated by a signal sending end, inputting a to-be-sent signal requested to be sent by the signal sending instruction into an input register of a programmable logic device; wherein the signal to be sent comprises at least one sub-signal to be sent; determining a time delay adjustment parameter of the at least one sub-signal to be sent according to the signal identification information of the signal to be sent; and after carrying out time sequence adjustment on the at least one to-be-sent sub-signal according to the time delay adjustment parameter, sending the to-be-sent signal to a signal receiving end through an output register of the programmable logic device. According to the method, the flexibility, diversity and high efficiency of signal time delay control can be improved, the debugging cost of the signal time delay control can be reduced, and the wiring space of a PCB (Printed Circuit Board) is saved.

The real-time video acquisition and processing board card of the PXIe specification comprises a connector assembly, a CameraLink Base receiver, a CameraLink Medium receiver, a CameraLink Full receiver, a TTL IO chip, a differential IO chip, an FPGA nonvolatile flash memory, a field programmable logic device, an FPGA high-speed dynamic random access memory, a DSP nonvolatile flash memory, a digital signal processor, a DSP high-speed dynamic random access memory, a PCIe bus interface and a power management module.

The invention provides a programmable logic device dynamic register configuration device and a control method thereof. The configuration device for the dynamic register of the programmable logic device comprises an external controller used for providing a configuration instruction and configuration data; the main controller is used for receiving and analyzing the configuration data, generating a gating signal and recombining a data packet; at least one multiplexing module, each multiplexing module being configured to include a register block; and one or more stages of sub-controllers are arranged between the main controller and the multiplexing module and are used for further analyzing the data packet and controlling the target register group to complete read-write operation. In addition, the invention further provides a control method corresponding to the configuration device. Some embodiments of the invention aim to solve the problems of high configuration switching time consumption and uncertain configuration switching time in the prior art on the premise of not increasing too much complexity and area overhead.

The invention provides an optical fiber gyroscope capable of dynamically adjusting a light source. The optical fiber gyroscope comprises a light source driving control circuit, a signal processing circuit, a temperature sensor and a light source module, the light source driving control circuit comprises a constant current source module, a temperature control module and a dual-channel digital-to-analog conversion module; the signal processing circuit comprises a programmable logic device; the temperature sensor is connected with the programmable logic device; the programmable logic device is used for generating constant current voltage and temperature control voltage in a digital form according to the environment temperature collected by the temperature sensor, and sending the constant current voltage and the temperature control voltage to the dual-channel digital-to-analog conversion module; the dual-channel digital-to-analog conversion module is used for converting the constant current voltage into a first analog voltage and outputting the first analog voltage to the constant current source module so as to dynamically adjust the output current of the constant current source module, and converting the temperature control voltage into a second analog voltage and outputting the second analog voltage to the temperature control module so as to dynamically adjust the temperature set point of the temperature control module; the output of the constant current source module and the output of the temperature control module are connected with the light source module and used for providing dynamically-adjusted driving current and working temperature for the light source module.

In some examples, a management controller includes a first interface through which the management controller is to provide a support service for any of a plurality of programmable logic devices in an electronic device. The management controller includes a controller processor to receive a code image to perform a programmable logic device update, where the code image comprises an identifier of a programmable logic device. In response to determining that the identifier corresponds to a given programmable logic device that is present in the electronic device, the management processor sets a multiplexer select value to control a multiplexer to connect the first interface of the management controller to the given programmable logic device. The management processor provides the code image to the given programmable logic device through the first interface and the multiplexer to update the given programmable logic device.

Systems and methods for managing remotely programmable logic devices (remote PLDs) are disclosed. An example system includes a remote PLD comprising multiple programmable logic blocks (PLBs) arranged within a PLD structure and programmable inputs / outputs (I / O) connected to the PLD structure. The remote PLD is configured to establish a communication link between the remote PLD and a remote PLD management system node via a communication module of a host device configured to interface with the remote PLD through programmable I / O. The remote PLD is configured to receive a protected configuration image from the remote PLD management system node via the communication link and program the PLD structure according to the protected configuration image.

The application discloses a video coding device, method, system, program product and storage medium, and relates to the technical field of video processing.In the application, the video coding device can be connected with a host through a bus interface, and at least two video channels are arranged between the video coding device and the host.A processor, a programmable logic device, a memory, a direct memory access controller and a channel management register can be arranged in the video coding device.The channel management register stores channel configurations of the video channels, and the programmable logic device is provided with processing units corresponding to the video channels.In actual application, the processor can set an encoder for the processing units of the video channels according to the channel configurations, and the direct memory access controller can allocate transmission bandwidth for the video channels according to the channel configurations.In this way, the original video data of the video channels can be subjected to different coding and transmission processing, so that the flexibility and scalability of multi-video stream processing can be improved.

The application discloses a wafer testing method. The wafer testing method comprises the following steps: obtaining a wafer to be tested and determining testing requirements; setting programmable logic devices between each specified port group of the wafer to be tested; based on the testing requirements, assigning values to each programmable logic device, providing values for each port group, forming a testing template; and testing the testing template by using a wafer testing machine. The above method sets programmable logic devices between the ports of the wafer, provides port data for the wafer to be tested through the programmable logic devices before wafer testing, makes the ports of the wafer to be tested in a specific connection template for realizing the electrical property function to be tested, does not depend on a storage wafer to provide port data, and thus wafer testing can be performed before 3D packaging; if the testing fails, the wafer does not need to be returned to work and disassembled, and therefore the production cost is reduced.