537 results about "Programmable logic device" patented technology

The invention discloses a server cooperative control method, a storage medium and electronic equipment, and relates to the technical field of firmware, and the method comprises the steps: employing a programmable logic device to actively take over the control authority of target equipment based on the operation parameters of a sensing device in a server starting stage, stable operation of equipment before initialization of the substrate management control device is not completed is ensured, a mechanism that a preset communication link and the substrate management control device are subjected to interactive verification is adopted, and the functional integrity and communication reliability of the substrate management control device during permission transfer are ensured through bidirectional communication verification. A dynamic permission recovery strategy based on real-time anomaly detection is adopted, control right reverse switching is triggered through a sensing device and communication link state dual monitoring mechanism, and the purpose of actively taking over equipment management responsibilities when a substrate management control device runs abnormally is achieved. Therefore, double improvement of system fault self-healing capability and equipment control continuity is realized, and the problem of difficulty in cooperative control among heterogeneous units is solved.

The invention provides a cross-protocol identification data intelligent analysis middleware method and system. The method comprises the following steps: taking multiple industrial communication protocol identifiers in advance to form a metadata set, and constructing a protocol feature element model library containing a non-standard protocol feature template; a programmable logic device is introduced, physical layer signal waveform characteristics are matched, and corresponding communication protocol stacks are dynamically switched at a hardware level according to a matching result; receiving a communication data stream through an electric domain processing unit of the programmable logic device, and generating a protocol analysis logic sequence in combination with a state transition rule of the meta-model library and a mode matching rule of the protocol stack; performing combined operation on the structured feature template and the analysis logic sequence to generate an executable cross-protocol data analysis rule; and when unknown protocol characteristics are detected, triggering dynamic reconstruction of the template, so that the analysis rule is adapted to a newly added protocol. According to the technical scheme provided by the invention, the protocol compatibility development cost in an industrial multi-protocol scene is remarkably reduced.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

The invention discloses a management system of a server and the server, relates to the technical field of computers, and realizes efficient interconnection and centralized management between a plurality of computing nodes and a management module by introducing an interface module between the computing module and the management module. Specifically, each computing node comprises a computing unit and a programmable logic device, a plurality of computing nodes are connected through the programmable logic device in the interface module, and the first management module obtains the operation data of each computing node through the interface module, so that the design that one management module manages multiple nodes is realized, the management units can be reduced, and the management efficiency is improved. And the cost is reduced, so that the expandability and the management efficiency of the system are improved.

Various techniques are provided for providing a root of trust chain, updating security protocols, and generating trusted customer configuration bitstreams for a programmable logic device (PLD). In one example, a method includes configuring hardware components of a PLD with an inherently trusted default set of operations immutably stored in a non-volatile memory and comprising a first root of trust for the PLD. The method also includes authenticating, by the hardware components configured with the default set of operations, a customer configuration bitstream comprising an updated set of operations. The method also includes reconfiguring the hardware components to replace the default set of operations with the updated set of operations if the authenticating is successful, wherein the updated set of operations comprise a second root of trust for the PLD. Additional devices, systems and methods are also provided.

Systems and methods for secure booting of secure programmable logic devices (PLDs) are disclosed. An example system includes a secure PLD including programmable logic blocks (PLBs) arranged in a PLD fabric of the secure PLD, and a configuration engine configured to program the PLD fabric according to a configuration image stored in a non-volatile memory (NVM) of the secure PLD and / or coupled through a configuration input / output (I / O) of the secure PLD to the configuration engine. The secure PLD is configured to retrieve a pre-authentication status associated with the configuration image from the NVM, determine or verify the retrieved pre-authentication status associated with the configuration image includes a valid status, and boot the PLD fabric of the secure PLD using the configuration image.

The invention relates to a method and a device for intelligently identifying server configuration and adaptively configuring PCIe (Peripheral Component Interconnect Express) bandwidth. The method comprises the following steps of: configuring a wiring mode of an I / O (Input / Output) expander in each server expansion card connected with a server mainboard and an onboard PCIe slot; starting a server power supply, and after the substrate management controller is initialized, acquiring a register value of an I / O expander on each server expansion card through an IIC communication protocol; the substrate management controller sends register values of all the I / O expanders to the complex programmable logic device; the complex programmable logic device sends register values of all the I / O expanders to a central processing unit of a server through a vGPIO communication protocol; and based on the register value of the I / O expander, the basic input / output system allocates bandwidth and resources to the onboard PCIE slot in each server expansion card. According to the method, the number of the universal server board cards can be reduced, the PCIe bandwidth can be adaptively configured, and the error probability is reduced.

The invention discloses a memory monitoring method, device, system and equipment and a medium, and relates to the technical field of computers. When it is monitored that a hardware error exists in the memory, hardware interruption is triggered through a preset programmable logic device, so that the micro-control unit is awakened to enter a working state; obtaining error data related to hardware errors in a preset target component by using the substrate management controller, and sending the error data to the awakened micro-control unit; and performing error type analysis on the error data based on the awakened micro-control unit, and sending an error processing request triggered based on an error type analysis result to an operating system of a preset target component, so that the operating system responds to the error processing request to obtain a corresponding error processing result. Through the technical scheme of the invention, the memory error can be quickly and accurately detected and timely processed, and the reliability, availability and energy efficiency management of the system are improved.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving documentation and receiving a full text search. The documentation may include user guides, technical specifications, and design files such as HDL code, constraints, timing reports, and / or design assistant / rule violation (DRC) reports. The present disclosure also includes determining semantic search for embedding vectors based on the documentation and the full text search. Furthermore, the present disclosure includes providing the semantic search to a large language model (LLM).

The invention discloses a data communication method, a data communication device, data communication equipment and a medium, relates to the technical field of computers, and is applied to a complex programmable logic device which communicates with a south bridge chip in a preset type server and an external target substrate management controller chip through a simplified pin bus. Comprising the steps that target data sent by a south bridge chip is transmitted to a target substrate management controller chip, and after a TAR signal is monitored, a first synchronous communication signal fed back by the target substrate management controller chip is acquired; converting the first synchronous communication signal into a second synchronous communication signal; and transmitting the second synchronous communication signal to a south bridge chip, so that the south bridge chip communicates with the target substrate management controller chip based on the simplified pin bus after executing the preset short-time waiting operation. According to the application, the communication between the preset type server and the target substrate management controller chip based on the simplified pin bus is realized by connecting the complex programmable logic device in series.

The invention discloses a hard disk access method of a hard disk backboard, a substrate management controller, a server and a storage medium, and relates to the technical field of server hardware management, and the method comprises the following steps: accessing a register of a programmable logic device with a first preset fixed address in a target hard disk backboard, and obtaining topological information of the target hard disk backboard; determining a target hard disk adaptation type of the target hard disk backboard from a plurality of hard disk adaptation types based on the NVME support state of each port contained in the topological information; and accessing the in-place target hard disk based on the access strategy information matched with the target hard disk adaptation type. The problem of high coupling of the BMC code and the hard disk backboard adaptation type is effectively solved, and the flexibility and expandability of server hardware adaptation are improved.

The neural network forward prediction hardware accelerator based on the programmable logic device can be applied to the technical field of neural network hardware acceleration. The accelerator comprises a multi-layer hardware accelerator module unit, and the hardware accelerator module unit comprises an input feature map cache module and a data processing module; the accelerator module units are connected in an assembly line structure mode; multi-channel feature maps can be processed in parallel; and the output data of the hardware accelerator module unit of each layer is stored in the input feature map cache module of the hardware accelerator module unit of the next layer for the operation of the next layer. By adopting an assembly line structure, the throughput rate of the hardware accelerator is improved; a multi-channel parallel processing mode is adopted, and the running speed of a hardware accelerator is increased; and on-chip storage is adopted, so that the off-chip access times are reduced, and the power consumption of the hardware accelerator is reduced.

The invention relates to the technical field of computers, in particular to a server configuration and management method, a server, a program product, equipment and a medium. The server configuration method comprises the steps that in response to starting of a server, a basic input and output system initializes a data space shared by a first mode and a second mode, and initialized data in the data space is called to initialize the first mode and the second mode; the first mode runs in a baseboard management controller, and the second mode runs in an operating system; the substrate management controller or the operating system takes one of the first mode and the second mode as a target detection mode, and feeds back the target detection mode to the programmable logic device; and the programmable logic device gates a path between the fault signal end and the operation main body of the target detection mode, and performs fault detection on the server by using the target detection mode. By adopting the method, various server fault detection modes can be compatible, so that optimization of server performance can be facilitated.

The invention discloses a protocol conversion method and device, a medium and a server system, and relates to the technical field of servers. Once an original protocol type is determined, a dynamic interface routing controller calls a corresponding conversion program stored in a mapping table; and converting the detected heterogeneous bus protocol command into a unified single-line serial bus protocol operation code. As the conversion program and the protocol characteristics are stored in the mapping table, the method has infinite protocol expansion capability, a new protocol can be supported by updating the mapping table and a detection engine without redesigning hardware or modifying codes of an editable logic device, the system design is greatly simplified, and the development cost is reduced. Therefore, the problem that the current programmable logic device can only realize single interface protocol conversion is solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

A mainboard protection system and method are provided. A precision resistor is arranged between an overcurrent protection component and a voltage regulator, and the precision resistor is connected to a current monitoring circuit. The current monitoring circuit is connected to a complex programmable logic device, and transmits, w detecting that a voltage difference of the precision resistor is greater than a set threshold, an early-warning signal to the complex programmable logic device. The complex programmable logic device is connected to a processor and sends, when receiving the early-warning signal, an interrupt signal to the processor. in response to receiving the interrupt signal, the processor cuts off outputting of the overcurrent protection component.

Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.

Systems and methods for provisioning secure programmable logic devices (PLDs) are disclosed. An example secure PLD provisioning system includes an external system comprising a processor and a memory and configured to be coupled to a secure PLD through a configuration input / output (I / O) of the secure PLD. The external system is configured to generate a locked PLD comprising the secure PLD based, at least in part, on a request from a secure PLD customer, wherein the request from the secure PLD customer comprises a customer public key; and to provide a secured unlock package for the locked secure PLD. The external system may also be configured to provide an authenticatable key manifest comprising a customer programming key token and a corresponding programming public key associated with the locked secure PLD, wherein the authenticatable key manifest is signed using a programming private key generated by the locked secure PLD.

The invention discloses a configurable time sequence control system, which relates to the technical field of electronic components, can replace the requirements of most scenes on a time sequence controller, can be directly reused in a development process, can greatly reduce the development workload and can improve the development efficiency. And the time sequence can be flexibly adjusted by adjusting configuration parameters, so that the working difficulty of debugging and maintenance is reduced. The system is constructed by single-channel basic modules, and the maturity and reliability of the system are easy to guarantee. Pure Veri log / VHDL design is adopted, an IP core can be independently packaged and added into an IP library of a programmable logic device integrated development environment, the IP core can be directly called during design and use, and due to the fact that pure logic codes are adopted for implementation, limitation of device models and development platforms is avoided.

A programmable logic device, and a server, which relate to the technical field of chip upgrading. A stage of second multi-path selection switch MUX2 is added before a first multi-path selection switch MUX0 between a complex programmable logic device (CPLD) and a platform controller hub (PCH) flash, in order to establish a hardware path between a baseboard management controller (BMC) and the PCH flash; moreover, a stage of third multi-path selection switch MUX3 is added before a fourth multi-path selection switch MUX1 between the CPLD and a BMC flash, in order to establish a hardware path between the PCH and a BMC chip, i.e., the BMC flash. Thus, a selection signal at the second multi-path selection switch MUX2 and the third multi-path selection switch MUX3 is realized, and the selection signal can be sent to the CPLD so as to complete the switching of a selection path. Therefore, during an upgrading process for BMC / PCH FW, the security of upgrading firmware is ensured, and hardware support is also provided for simplifying the upgrading process.

Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented. In an exemplary aspect, a method of programming a programmable logic device (PLD) is presented, wherein the PLD provides a plurality of available lookup table (LUT) structures. In some embodiments, the method includes mapping a logic design to a selected LUT of a plurality of LUTs of different numbers of inputs, wherein the selected LUT has an associated LUT equation; and mapping the selected LUT to a first LUT structure from the plurality of available LUT structures based on the associated LUT equation.

The invention discloses a board card firmware upgrading system, method, device and equipment of a server and a medium, and relates to the technical field of network equipment, the system comprises a substrate management controller and a plurality of board cards, each board card at least comprises a programmable memory, a programmable logic device, a first identification input circuit and a second identification input circuit, and the CPLD dynamically updates the unique identification of the board card and the firmware version identification through the first identification input circuit and the second identification input circuit. The problem that in the application scene of the server, a plurality of common printed circuit board cards cannot share CPLD FW and EEPROM burning files is solved, so that the problems of FW upgrading omission or errors and the like caused by excessive derivative board cards are avoided, the research and development workload is reduced, and the user experience is improved.

The invention discloses a PCIe interface verification method and a PCIe interface verification system, and relates to the technical field of test.According to the PCIe interface verification method, after a PCIe interface is divided into a PCIe controller and a PCIe physical layer, a simulation PCIe controller can be constructed based on programmable hardware resources in a programmable logic device, and the simulation PCIe controller can be constructed in non-programmable hardware resources of the programmable logic device; at least a portion of the physical layer is selected as a simulated PCIe physical layer. After the simulation PCIe controller and the simulation PCIe physical layer are connected, the simulation PCIe controller and the simulation PCIe physical layer can communicate with each other, namely, the combination of the simulation PCIe controller and the simulation PCIe physical layer can be regarded as a simulation PCIe interface. Therefore, prototype verification of the PCIe interface can be realized based on the simulation PCIe interface, so that the problem that prototype verification cannot be performed on the PCIe interface in some technologies is solved.

The invention discloses a port lighting method and system, a mainboard, a storage medium and electronic equipment, and belongs to the field of network equipment communication, and the method comprises the steps that a CPU of the mainboard carries out port lighting according to the number of serializer / deserializer SerDes interfaces provided for each daughter card slot position and the preset lighting sequence of each daughter card slot position; determining the number and the position of the lighting signal of each sub-card slot position in the whole section of lighting signal code stream; the CPU of the mainboard configures the lighting signal type of each daughter card slot position according to the number of the ports of the daughter cards, and outputs the whole section of lighting signal code stream to a programmable logic device of the mainboard through a switching chip; a programmable logic device of the mainboard intercepts the lighting signals of the sub-card slot positions from the whole section of lighting signal code stream according to the determined number and position, and distributes the lighting signals to the sub-card slot positions; and the programmable logic device of the corresponding daughter card in each daughter card slot receives the lighting signal, analyzes the lighting signal and sends the lighting signal to each port LED lamp for lighting. According to the method and the device, the problem of abnormal port lighting caused by change of the number of ports of the daughter card in a hardware lighting scheme is solved on equipment supporting hot plugging of the daughter card, meanwhile, the occupied CPU resource is low, and the real-time performance is high.

The invention discloses a controller communication system and method, a computer product, equipment and a storage medium, and relates to the technical field of controller communication, and the controller communication system comprises a first controller which is provided with a first processor and a first complex programmable logic device; the second controller is provided with a second processor and a second complex programmable logic device; the first processor is connected with the first complex programmable logic device through a first connecting line, the first complex programmable logic device is connected with the second complex programmable logic device through a second connecting line, and the second complex programmable logic device is connected with the second processor through a third connecting line. A plurality of pins are arranged on the complex programmable logic device; and according to different target fault information types and a link formed by the plurality of pins and the plurality of connection lines corresponding to the different target fault information types, fault information transmission between the controllers is realized. The technical problem of low service switching efficiency between the controllers is solved, and the communication efficiency of the controllers can be improved.

The embodiment of the invention provides a hot plug control system and method for a power supply unit, a storage medium and electronic equipment, and the system comprises a hot plug signal trigger which is used for triggering a hot plug pre-alarm signal which is used for indicating that the power supply unit connected with the hot plug signal trigger is to be pulled out; the programmable logic device is connected with the hot plug signal trigger and used for controlling the efuse circuit to be switched off and controlling the power supply unit to stop outputting electric energy under the condition that the hot plug pre-warning signal is received, and the efuse circuit is connected with the power supply unit and used for controlling the power supply unit to input / output an electric energy path to be switched on and switched off; and the indicating lamp assembly is connected with the power supply unit and is used for detecting residual electric energy of the power supply unit and closing the indicating lamp assembly under the condition that the residual electric energy is lower than a preset threshold value so as to indicate that the power supply unit can be pulled out.

The invention discloses a baseband signal generator based on a programmable logic device, and relates to the technical field of radars, a method is realized by using programmable logic resources in a universal programmable logic device, after an output frequency is generated, a phase parameter is obtained by calculating and accumulating a phase increment, and the output frequency is output. The phase parameter is used as the query address of the sine and cosine lookup table to query and output the digital baseband signal, and the method of directly reading the pre-stored data from the lookup table greatly reduces the calculation amount, saves the operation time and resources of a processor, and especially in a scene where continuous sine and cosine signals need to be generated at a high speed, greatly improves the calculation efficiency. The response speed of the system can be remarkably improved, the signal processing task with the high real-time requirement is met, the system delay time is shortened, the overall power consumption of the system is reduced, the frequency synthesis chip mounted outside the chip is reduced, and the hardware overhead is reduced.

The embodiment of the invention provides a data processing method, which comprises the following steps of: converting an e index calculation task into an index calculation task aiming at a target fixed point number, and splitting the index calculation task aiming at the target fixed point number into a shift task and index calculation aiming at a target decimal part, an index calculation task aiming at the target decimal part is approximate to linear function calculation (namely addition and multiplication based on calculation parameters), so that the calculation process can be greatly simplified, and simple multiplication and addition are executed by utilizing a digital signal processor based on the calculation parameters corresponding to the target decimal part; compared with the prior art, the method has the advantages that operation steps and required computing resources are reduced, all computing resources of one digital signal processor are fully utilized in the process, the whole task process can be performed in series, judgment branches and data rereading do not exist, the overall computing efficiency is improved, and hardware resource consumption is reduced.

Embodiments of the present application provide a server, a data transmission method for the server, and a storage medium. The server comprises an extended chip, a front-end I3C bus, and a first programmable logic device; the extended chip comprises a first master I3C interface; the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces; the front-end I3C bus is an I3C bus that connects the first master I3C interface to the first slave I3C interface; the front-end I3C bus is used for performing data transmission between the extended chip and the first programmable logic device; and the extended chip is used for performing data exchange with the first programmable logic device by means of the front-end I3C bus, so as to realize GPIO extension of the extended chip by means of the plurality of GPIO interfaces. The present application solves the problem in the related art of poor adaptability of input / output extension of a server, and achieves the effect of improving the adaptability of input / output extension of a server.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.