369 results about "Programmable logic device" patented technology

The invention provides a cross-protocol identification data intelligent analysis middleware method and system. The method comprises the following steps: taking multiple industrial communication protocol identifiers in advance to form a metadata set, and constructing a protocol feature element model library containing a non-standard protocol feature template; a programmable logic device is introduced, physical layer signal waveform characteristics are matched, and corresponding communication protocol stacks are dynamically switched at a hardware level according to a matching result; receiving a communication data stream through an electric domain processing unit of the programmable logic device, and generating a protocol analysis logic sequence in combination with a state transition rule of the meta-model library and a mode matching rule of the protocol stack; performing combined operation on the structured feature template and the analysis logic sequence to generate an executable cross-protocol data analysis rule; and when unknown protocol characteristics are detected, triggering dynamic reconstruction of the template, so that the analysis rule is adapted to a newly added protocol. According to the technical scheme provided by the invention, the protocol compatibility development cost in an industrial multi-protocol scene is remarkably reduced.

The invention discloses a parallel processor dynamic resource allocation system and method based on reconfigurable hardware, and relates to the technical field of computer chips, and the system comprises a workload monitoring module which is responsible for monitoring the workload type and the resource demand of a task processed by a parallel processor in real time, and determining the task type and the resource demand by identifying the task type and the resource demand; a monitoring result is fed back to the resource allocation control module; the resource allocation control module is responsible for generating a corresponding resource allocation control signal based on feedback information of the workload monitoring module and dynamically configuring the reconfigurable hardware module; the reconfigurable hardware module is responsible for realizing efficient adaptation to diversified tasks through a plurality of reconfigurable units formed by programmable logic devices according to different working load dynamic reconfiguration functions and connection modes; and the data caching and transmission module is responsible for cross-module data circulation and global data storage. Different task requirements can be accurately adapted, and the resource utilization rate is improved.

The invention discloses a management system of a server and the server, relates to the technical field of computers, and realizes efficient interconnection and centralized management between a plurality of computing nodes and a management module by introducing an interface module between the computing module and the management module. Specifically, each computing node comprises a computing unit and a programmable logic device, a plurality of computing nodes are connected through the programmable logic device in the interface module, and the first management module obtains the operation data of each computing node through the interface module, so that the design that one management module manages multiple nodes is realized, the management units can be reduced, and the management efficiency is improved. And the cost is reduced, so that the expandability and the management efficiency of the system are improved.

Systems or methods of the present disclosure may provide a design tool for adjusting designs implemented on programmable logic devices. The present disclosure includes receiving documentation and receiving a full text search. The documentation may include user guides, technical specifications, and design files such as HDL code, constraints, timing reports, and / or design assistant / rule violation (DRC) reports. The present disclosure also includes determining semantic search for embedding vectors based on the documentation and the full text search. Furthermore, the present disclosure includes providing the semantic search to a large language model (LLM).

The invention discloses a hard disk access method of a hard disk backboard, a substrate management controller, a server and a storage medium, and relates to the technical field of server hardware management, and the method comprises the following steps: accessing a register of a programmable logic device with a first preset fixed address in a target hard disk backboard, and obtaining topological information of the target hard disk backboard; determining a target hard disk adaptation type of the target hard disk backboard from a plurality of hard disk adaptation types based on the NVME support state of each port contained in the topological information; and accessing the in-place target hard disk based on the access strategy information matched with the target hard disk adaptation type. The problem of high coupling of the BMC code and the hard disk backboard adaptation type is effectively solved, and the flexibility and expandability of server hardware adaptation are improved.

The invention discloses a protocol conversion method and device, a medium and a server system, and relates to the technical field of servers. Once an original protocol type is determined, a dynamic interface routing controller calls a corresponding conversion program stored in a mapping table; and converting the detected heterogeneous bus protocol command into a unified single-line serial bus protocol operation code. As the conversion program and the protocol characteristics are stored in the mapping table, the method has infinite protocol expansion capability, a new protocol can be supported by updating the mapping table and a detection engine without redesigning hardware or modifying codes of an editable logic device, the system design is greatly simplified, and the development cost is reduced. Therefore, the problem that the current programmable logic device can only realize single interface protocol conversion is solved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.

Various techniques are provided to implement multi-chip secure and programmable systems and methods. In one example, a multi-chip module system for providing an integrated programmable logic functionality and security functionality. The multi-chip module system includes a first die including a programmable logic device (PLD) configured to provide at least a portion of the programmable logic functionality. The multi-chip system further includes a second die including a security engine configured to perform at least a portion of the security functionality. The security engine is further configured to receive, from the first die, data associated with a first and second configuration image; perform a read operation on a memory for the second configuration image based on the data; and authenticate the second configuration image. The multi-chip system further includes a configuration engine configured to program the PLD according to the first configuration image. Related devices and methods are provided.

Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented. In an exemplary aspect, a method of programming a programmable logic device (PLD) is presented, wherein the PLD provides a plurality of available lookup table (LUT) structures. In some embodiments, the method includes mapping a logic design to a selected LUT of a plurality of LUTs of different numbers of inputs, wherein the selected LUT has an associated LUT equation; and mapping the selected LUT to a first LUT structure from the plurality of available LUT structures based on the associated LUT equation.

The invention discloses a board card firmware upgrading system, method, device and equipment of a server and a medium, and relates to the technical field of network equipment, the system comprises a substrate management controller and a plurality of board cards, each board card at least comprises a programmable memory, a programmable logic device, a first identification input circuit and a second identification input circuit, and the CPLD dynamically updates the unique identification of the board card and the firmware version identification through the first identification input circuit and the second identification input circuit. The problem that in the application scene of the server, a plurality of common printed circuit board cards cannot share CPLD FW and EEPROM burning files is solved, so that the problems of FW upgrading omission or errors and the like caused by excessive derivative board cards are avoided, the research and development workload is reduced, and the user experience is improved.

The invention discloses a PCIe interface verification method and a PCIe interface verification system, and relates to the technical field of test.According to the PCIe interface verification method, after a PCIe interface is divided into a PCIe controller and a PCIe physical layer, a simulation PCIe controller can be constructed based on programmable hardware resources in a programmable logic device, and the simulation PCIe controller can be constructed in non-programmable hardware resources of the programmable logic device; at least a portion of the physical layer is selected as a simulated PCIe physical layer. After the simulation PCIe controller and the simulation PCIe physical layer are connected, the simulation PCIe controller and the simulation PCIe physical layer can communicate with each other, namely, the combination of the simulation PCIe controller and the simulation PCIe physical layer can be regarded as a simulation PCIe interface. Therefore, prototype verification of the PCIe interface can be realized based on the simulation PCIe interface, so that the problem that prototype verification cannot be performed on the PCIe interface in some technologies is solved.

The invention discloses a controller communication system and method, a computer product, equipment and a storage medium, and relates to the technical field of controller communication, and the controller communication system comprises a first controller which is provided with a first processor and a first complex programmable logic device; the second controller is provided with a second processor and a second complex programmable logic device; the first processor is connected with the first complex programmable logic device through a first connecting line, the first complex programmable logic device is connected with the second complex programmable logic device through a second connecting line, and the second complex programmable logic device is connected with the second processor through a third connecting line. A plurality of pins are arranged on the complex programmable logic device; and according to different target fault information types and a link formed by the plurality of pins and the plurality of connection lines corresponding to the different target fault information types, fault information transmission between the controllers is realized. The technical problem of low service switching efficiency between the controllers is solved, and the communication efficiency of the controllers can be improved.

The embodiment of the invention provides a data processing method, which comprises the following steps of: converting an e index calculation task into an index calculation task aiming at a target fixed point number, and splitting the index calculation task aiming at the target fixed point number into a shift task and index calculation aiming at a target decimal part, an index calculation task aiming at the target decimal part is approximate to linear function calculation (namely addition and multiplication based on calculation parameters), so that the calculation process can be greatly simplified, and simple multiplication and addition are executed by utilizing a digital signal processor based on the calculation parameters corresponding to the target decimal part; compared with the prior art, the method has the advantages that operation steps and required computing resources are reduced, all computing resources of one digital signal processor are fully utilized in the process, the whole task process can be performed in series, judgment branches and data rereading do not exist, the overall computing efficiency is improved, and hardware resource consumption is reduced.

Embodiments of the present application provide a server, a data transmission method for the server, and a storage medium. The server comprises an extended chip, a front-end I3C bus, and a first programmable logic device; the extended chip comprises a first master I3C interface; the first programmable logic device comprises a first slave I3C interface and a plurality of GPIO interfaces; the front-end I3C bus is an I3C bus that connects the first master I3C interface to the first slave I3C interface; the front-end I3C bus is used for performing data transmission between the extended chip and the first programmable logic device; and the extended chip is used for performing data exchange with the first programmable logic device by means of the front-end I3C bus, so as to realize GPIO extension of the extended chip by means of the plurality of GPIO interfaces. The present application solves the problem in the related art of poor adaptability of input / output extension of a server, and achieves the effect of improving the adaptability of input / output extension of a server.

Embodiments of the present disclosure include improved logic blocks with combined outputs for programmable logic devices and methods of operating and programming these logic blocks. In an exemplary aspect, a programmable logic device (PLD) is described. In some embodiments, the PLD includes a logic block. The logic block may include a first look-up table (LUT) circuit configured to generate a first output; a second LUT circuit configured to generate a second output; a ripple logic circuit configured to receive the first output and the second output and generate a third output; and a three-to-one multiplexer circuit configured to receive the first output, the second output, and the third output and selectively produce an output of the logic block.

The invention provides an airborne task system comprehensive video display device and method, the system comprises a device main body, the device main body comprises a programmable logic device, a video processing unit, a cache memory and an internal bus; the programmable logic device is configured with a plurality of video interface drivers and data interface drivers and is used for receiving video streams and data streams from external equipment; the programmable logic device is configured to analyze a video stream and a data stream, extract image pixel information and sensor data, and cache the analyzed information to the cache memory; and the video processing unit is configured to read the information from the cache memory, perform fusion processing and video coding, generate a comprehensive display picture and output the comprehensive display picture to at least one display device. According to the comprehensive video display device provided by the invention, efficient processing and real-time display of multi-source airborne data are realized through a special hardware architecture, and the system compatibility and reliability are remarkably improved.

Configurable logic slices for programmable logic devices and methods of using and programming such logic slices and devices are presented herein. In one embodiment, a programmable logic device (PLD) is disclosed that includes a logic slice. The logic slice may include a first look-up table (LUT) configured to generate a first output; and an input switch stage configured to receive the first output and selectively generate a first signal. The logic slice may further include a second LUT configured to receive the first signal and to generate a second output; and a two-to-one multiplexer configured to receive the first output and the second output and selectively produce an output of the logic slice.

The embodiment of the invention provides a serial port debugging method and a circuit board, and the method comprises the steps: receiving a register access command transmitted by an upper computer through a target serial port, enabling a programmable logic device to directly respond to the register access command of the upper computer, and executing a target access operation on a target register of the programmable logic device, under the condition that the control component fails and cannot normally communicate, the state information of the control component can be obtained by accessing the target register, so that abnormal fault positioning is realized; and the register access result is fed back to the upper computer in real time through the target serial port and the programmable logic device, so that the detailed state information of the control part can be quickly obtained, and the technical problem of serial port debugging failure caused by failure positioning when the control part is abnormal in the prior art is solved.

The invention relates to the technical field of servers, in particular to a hard disk alarm method and device of a server, the server and a medium, the method is applied to a substrate management controller in the server, and the server further comprises a backboard and a plurality of hard disks; a complex programmable logic device is arranged on the back plate; the complex programmable logic device and the backboard are connected with the substrate management controller. The method comprises the following steps: reading a target hard disk in-place signal of the complex programmable logic device, wherein the target hard disk is any one of a plurality of hard disks; reading the hard disk state of the target hard disk; determining whether the target hard disk is a fault hard disk according to the in-place signal and the hard disk state of the target hard disk; if the target hard disk is the fault hard disk, alarm information of the target hard disk is output, and the alarm information is used for fault alarm of the target hard disk; the problem that the substrate management controller can still give an alarm under the condition that the card end of the redundant array of independent disks of the hard disk is not recognized is solved, and the accuracy of determining the faulty hard disk is improved.

Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.

The invention discloses a signal reading system and method for superconducting microwave multiplexing device detection, and belongs to the field of superconducting microwave multiplexing device detection, and the system comprises a server which can issue a detection configuration instruction to a signal board, receive and return detection data, operate detection software, execute spectrum analysis and data analysis, and generate a detection result; the signal board is provided with a circuit containing a programmable logic device, and the circuit can output accurate intermediate frequency signals and excitation current signals according to instructions of the server, processes output signals of the detected superconducting microwave multiplexing devices mixed by the frequency mixing board through a critical sampling filter bank algorithm to obtain detection data, and transmits the detection data back to the server; and the frequency mixing plate can perform up-conversion on the intermediate frequency signal generated by the signal plate to radio frequency to form a radio frequency detection signal, output the radio frequency detection signal to each detected superconducting microwave multiplexing device, perform down-conversion on the radio frequency response signal returned from each superconducting microwave multiplexing device to intermediate frequency, and output the radio frequency response signal to the signal plate. The system can detect the quality of the device with low computing resources.

The invention discloses an upgrading method and device of a complex programmable logic device (CPLD), electronic equipment and a medium, and the method comprises the steps: controlling a fifth input / output pin to send a starting signal to a first input / output pin based on a first code if the CPLD has an upgrading demand, sending a starting signal to a second input / output pin through a sixth input / output pin so as to load a second code; and under the condition that the second code is loaded, loading upgrading data of the CPLD based on a baseboard management controller (BMC), sending the upgrading data to a third input / output pin and a fourth input / output pin, and upgrading the CPLD through the upgrading data. Therefore, the problems that in the application scene of the current server, the power-on loading or upgrading process of the CPLD is interrupted by I2C communication of the BMC, loading or upgrading of the CPLD fails, and finally running of the whole server is abnormal are solved, and safe starting and successful upgrading of the CPLD and stable running of the server are guaranteed.

The invention discloses an FPGA (Field Programmable Gate Array) configuration architecture and an application method thereof. The architecture comprises FILO modules, a local shared configuration memory area and a distributed parameter storage area established between adjacent FILO module clusters, wherein the distributed parameter storage area is specially used for caching key configuration data of a current task execution period; a configuration memory area is shared globally, a high-bandwidth configuration memory is integrated on the top layer of the FPGA architecture, and all reconfigurable parameter sets of the full task process are stored persistently. And adding a temporary stack pointer and setting a corresponding pointing area. The application method comprises the steps of global configuration preloading, local dynamic loading and FILO module execution. According to the method, the performance, the energy efficiency and the resource utilization rate of the FPGA in a lightweight and dynamic application scene are greatly improved. The method can be widely applied to the field of programmable logic device system structures.

To utilize unused or underutilized input and output pins without significantly impacting power consumption and die area, an adaptive logic module (ALM) of a programmable logic device can be implemented with an additional 2LUT to improve low function packing density and broad function mapping coverage. The 2LUT can also serve as a route-through to provide direct access to ALM registers with or without input inversion. The extended ALM can also utilize route-through configurations of the additional 2LUT to enhance the connectivity of the ALM inputs and outputs.

A method of identifying error patterns during automated device testing comprises receiving a data pattern from a plurality of capture modules programmed on a programmable logic device, wherein the plurality of capture modules are programmable and operable to selectively capture data traffic to be monitored, and wherein the data traffic comprises a flow of traffic between a DUT and the programmable logic device. The method further comprises comparing the data pattern with known signatures in an error signature database. Also, the method comprises correlating the data pattern with one or more matching known signatures in the error signature database and assigning a score to each of the one or more matching known signatures in the error signature database based a level of correlation.

The utility model discloses a programmable logic device test experiment device, which relates to the field of logic device test experiments and comprises a replaceable FPGA test circuit, a phase-locked loop test circuit, a pulse width modulation test circuit, a chip power supply circuit, a serial port test circuit, a Bank area power supply test circuit, a power supply generation circuit and a liquid crystal display control circuit. According to the experimental device for testing the programmable logic device, through a mode of combining the liquid crystal display screen and the FPGA function test board, a large-scale test machine in traditional test equipment is omitted, so that a test system is more portable, comprehensive coverage test of FPGA chip functions can be realized through compiling a plurality of self-test programs, and the test efficiency is improved. Therefore, not only can the basic logic function of the FPGA be tested, but also the advanced characteristics and boundary conditions of the FPGA can be deeply verified, so that the function correctness of the FPGA chip can be more comprehensively ensured.

A system or method of the present disclosure may provide an electronic device comprising: a memory (504) storing instructions; and a processor (502) that, when executed, is to receive a programmable fabric design of an integrated circuit device (12). The instructions are further to cause the processor (502) to cause the design to be compiled into a configuration (20) during a compilation window. The instructions are further to cause the processor (502) to determine at least some routes (108) of the configuration (20) outside the compilation window.

The present invention discloses an inductive linear absolute position measuring device, which relates to the field of linear position measurement. The inductive linear absolute position measuring device includes a single-track grating scale and a reading head. The reading head includes: a substrate; an induction coil drawn on the substrate. The induction coil includes an S coil array and an R coil array. Each coil array includes n independent complementary coils. Each independent complementary coil is composed of 2 sub-coils wound in opposite directions in series; an excitation coil surrounding the induction coil. The excitation coil is a multi-turn closed coil connected in series; a hardware processing circuit arranged on the substrate, including an excitation signal driving circuit, a selection switch circuit, a demodulation circuit, an operational amplifier circuit and a programmable logic device. Compared with the prior art, the inductive linear absolute position measuring device provided by the present invention is smaller in size, higher in reliability, higher in measurement accuracy, and stable and accurate in measurement.

The present specification relates to the technical field of multimodal imaging and provides a scanning control method, device, and system for photoacoustic and fluorescence dual-modal imaging. The system comprises: a laser; a first data acquisition card for acquiring imaging data of a target in a fluorescence mode; a second data acquisition card for acquiring imaging data of the target in a photoacoustic mode; the first data acquisition card and the second data acquisition card taking the same amount of time to complete single-frame acquisition; and a programmable logic device for, after confirming that the first data acquisition card is in a ready state, synchronously outputting a trigger signal to the first data acquisition card and the second data acquisition card when a specific edge of a laser pulse output by the laser arrives, so that the first data acquisition card and the second data acquisition card operate synchronously.

Techniques are described herein in which a programmable logic device (PLD) is integrated into a baseboard management controller (BMC). A programming-enhanced BMC is powered on by a PLD that is integrated into the programming-enhanced BMC and that is coupled to an internal bus of the programming-enhanced BMC. A configuration file is provided from immutable BMC hardware in the BMC to the PLD based at least on the programming-enhanced BMC being powered on. The configuration file specifies a configuration to be programmatically applied to programmable hardware of the PLD. The programmable hardware of the PLD is programmed by loading the configuration file, which causes the programmable hardware to render a peripheral interface that is defined by the configuration file natively on the internal bus of the programming-enhanced BMC.