13 results about "Digital analog converter" patented technology

A potentiostat architecture includes one or more feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current. At least one of the feedback loops include a comparator configured to sense a voltage difference and output a signal based on the voltage difference, a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control, and a digital to analog convertor configured to receive the signal from the comparator and output feedback digital bits related to a control.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

A source driving circuit and an adjusting method therefor, and a display panel are provided. The source driving circuit includes: a DAC configured to obtain a grayscale value and convert the grayscale value into a grayscale voltage; a differential amplifier having a first input terminal connected to the DAC to obtain the grayscale voltage; a first bias circuit configured to apply a first bias tail current to the differential amplifier; a flip-flop connected to the DAC to obtain the grayscale value and a variation range of the grayscale value; and a second bias circuit connected to the flip-flop and configured to apply a second bias tail current to the differential amplifier in response to the variation range of the grayscale value satisfying a trigger condition.

The application discloses a digital loudspeaker volume control method, device, equipment and medium, relates to the loudspeaker technical field, and is used for solving the problems of quality reduction and complex manufacturing process in the prior art. The method comprises the following steps: receiving a volume adjustment instruction; determining an electric energy signal loaded to a loudspeaker unit in each quantized audio digital stream based on the volume adjustment instruction; the electric energy signal at least comprises an electric energy amplitude signal or an electric energy action time signal; adjusting sound pulse energy output by the loudspeaker unit based on the electric energy amplitude or the electric energy action time, and completing volume adjustment. The scheme realizes volume control of digital sound production based on the electric energy amplitude or the electric energy action time, does not need a digital-analog converter, and does not need multiple transducing element hardware supports. On the basis of not increasing the number of rows of transducing elements, the electric signal energy loaded to the loudspeaker unit is controlled, so that the sound pulse energy output is controlled, and digital volume adjustment is realized.

The application discloses a kind of wideband high-speed digital frequency hopping system and method based on direct frequency generation.The system includes FPGA, digital-analog converter and clock chip, wherein the FPGA has differential high-speed serial interface, is configured as JESD204B high-speed interface;The digital-analog converter captures entire spectrum at a time, built-in DDC digital frequency conversion and FIR filter, support up to 6GHz radio frequency frequency direct generation;The clock chip generates two-way 256MHz differential LVDS clock, and the working clock of FPGA and digital-analog converter is all used 256MHz clock.The method includes baseband IQ signal generation, baseband IQ signal interpolation filtering, odd-even sequence splitting, odd-even sequence digital frequency conversion, odd-even sequence merging sending, digital up-conversion and radio frequency output these steps.The application has high reliability, low cost, small volume, low power consumption, and has excellent anti-interference performance.

A successive approximation analog-to-digital converter includes a resistor digital-to-analog converter, including a plurality of series-connected resistors configured to provide a plurality of non-binary weighted divided voltages, a first capacitor digital-to-analog converter configured to: perform a non-binary Most Significant Bit (MSB) conversion process, using a first redundancy capacitor and a first non-binary weighted MSB capacitor array, for an analog input voltage, and perform a non-binary Least Significant Bit (LSB) conversion process, using a first LSB capacitor to which one of the non-binary weighted divided voltages is applied, thereby sequentially generating a first capacitor digital-to-analog converter output voltage, a second capacitor digital-to-analog converter configured to sequentially generate a second capacitor digital-to-analog converter output voltage, using a second redundancy capacitor, a second non-binary weighted MSB capacitor array, and a second LSB capacitor; and a comparator configured to compare the first capacitor digital-to-analog converter output voltage and the second capacitor digital-to-analog converter output voltage.

Systems and methods provide architectures for various applications, for example, for software defined radios and other high frequency (HF) application. Embodiments can provide novel multi path ΣΔ architectures that form the basis for novel N path Sigma Delta (NΣΔ) modulators, NΣΔ digital to analog converters (NΣΔ DAC) and NΣΔ analog to digital converters (NΣΔ ADC).

This invention discloses a self-calibration method and system for air quality sensors based on time series analysis. It continuously collects measurements during normal sensor operation to form time series data, divides this data into consecutive time periods, and calculates statistical parameters for each time period. By dynamically comparing current parameters with historical parameter sequences, it intelligently identifies significant trends in statistical characteristics to determine if a fundamental drift has occurred. Once drift is confirmed, a pre-set calibration table is consulted based on the trend amplitude and direction to obtain calibration coefficients. Finally, the gain or bias voltage of the sensor's output circuit is adjusted via a digital-to-analog converter to achieve autonomous closed-loop calibration. This invention utilizes only the sensor's own historical data for analysis, eliminating the need for external reference equipment or complex model training. It achieves efficient, low-cost, and real-time online self-calibration, significantly improving the long-term reliability and stability of air quality monitoring data.

The present disclosure relates to a test and / or measurement system for testing a DUT. The test and / or measurement system comprises a first port and a second port, wherein the DUT is connectable between the first and the second port; a signal generator which is configured to generate a digital test signal; a DAC which is configured to convert the digital test signal to an analog test signal; wherein the first port is configured to forward the analog test signal to the DUT, and wherein the second port is configured to receive an analog response signal from the DUT; an ADC which is configured to convert the analog response signal to a digital response signal; and a measurement device which is configured to compare the digital response signal to the digital test signal or to information about the digital test signal; wherein the measurement device is configured to trigger an adaption of an amplitude of the digital test signal based on a result of said comparison.

A capacitive charge-coupling mode analog compute in-memory (CIM) bitcell array is configured to generate an analog output voltage corresponding to a multiply-accumulate (MAC) operation result using a multibit weight. The analog output voltage is inputted to a dual-mode activation module which is selectively operable either in a Deep Neural Network (DNN) mode and a Spiking Neural Network (SNN) mode. The activation module comprises a sample and hold (S&H) circuit, a comparator, a digital-to-analog converter (DAC) which can be reconfigured in accordance with the selected one of the DNN mode and the SNN mode.

The disclosure provides a design of integrating a ferrite-based circulator within the surface mount device (SMD) package for an RF front-end module. The ferrite-based circulator serves as a duplexer. The front-end module contains all relevant transmitting / receiving (T / R) functions within a small footprint having significant power handling. The disclosed front-end module can be interfaced with Analog-to-Digital and Digital-to-Analog converters.