2915 results about "Digital analog converter" patented technology

A processor operates on samples of a digital output signal to determine samples of a digital correction signal. The output signal samples are directed to an output channel for transmission from a speaker. The digital correction signal samples are supplied to a first digital-to-analog converter for conversion into an analog correction signal. The subtraction circuit generates a difference between a first analog signal provided by a microphone and the analog correction signal. The analog correction signal is an estimate of a contribution to the first analog signal due to a direct path transmission between the speaker and the microphone. The processor also receives a digital input signal derived from the difference signal, and, performs acoustic echo cancellation on the digital input signal to obtain a resultant signal. The acoustic echo cancellation is configured to remove contributions to the digital input signal due to reflected path transmissions.

A system and method for creating an integrated digital media management and reproduction device comprised of a database with key data values for a plurality of records, and a module with search controls that include sets of compound parallel attribute queries that can execute instructions for a data category, and concurrently retrieve and display records across a plurality of related categories—thereby revealing the associations between discrete records. The invention also has a plurality of software instantiated media players which, through instructions managed by a “master container” design, function as if they were dynamically aware of user actions and the quantifiable states of each other player object—and respond according to logic rules, visually guiding event workflow. The system has a memory module for storing query information, a processor configured to retrieve data, a display unit for retrieved data and a digital-to-analog converter for providing capability for connection to loudspeakers.

The invention is a switched-matrix output for a multi-channel stimulator. The switch-matrix output system uses groups of switches connectively placed between N number of digital-to-analog convertors (DACs) and M electrode contacts to permit fewer, space-consuming DACs to be used in an implantable stimulator, thereby saving internal stimulator space. One embodiment of the switched matrix output uses switches to activate only one active-electrode subset of M electrode contacts at any one time, so that the total number of DACs contained in the stimulator can be less than the M total number of electrode contacts.

An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform. The nature of the AWG output waveform is flexibly determined by the nature of the data sequence and the frequency at which it is read out of the RAM, the manner in which the PLD routes the data sequence to the DACs, the value of the range data supplied to each DAC, and the output pattern generated by the pattern generator. The flexible AWG architecture permits the AWG to be appropriately configured for various combinations of output waveform frequency, bandwidth and resolution requirements.

A smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end. More specifically, this is provided for by a smart radio incorporating Parascan® varactors embodied within an intelligent adaptive RF front end that comprises at least one tunable antenna; at least one antenna null steering facility associated with said at least on tunable antenna; at least one tunable duplexer receiving the output from and providing input to said at least one antenna null steering facility; a first tunable RF filter receiving the output from said at least one tunable duplexer and providing the input to an analog to digital converter, said analog to digital converter providing the input to a digital signal processor, the output of which is input for a digital to analog converter; a second tunable RF filter receiving the analog output of said digital to analog converter and providing an input to said at least one tunable duplexer.

The Field Programmable Instrument Controller (FPIC) is a stand-alone low to high performance, clocked or unclocked multi-processor that operates as a microcontroller with versatile interface and operating options. The FPIC can also be used as a concurrent processor for a microcontroller or other processor. A tightly coupled Multiple Chip Module design incorporates non-volatile memories, a large field programmable gate array (FPGA), field programmable high precision analog to digital converters, field programmable digital to analog signal generators, and multiple ports of external mass data storage and control processors. The FPIC has an inherently open architecture with in-situ reprogrammability and state preservation capability for discontinuous operations. It is designed to operate in multiple roles, including but not limited to, a high speed parallel digital signal processing; co-processor for precision control feedback during analog or hybrid computing; high speed monitoring for condition based maintenance; and distributed real time process control. The FPIC is characterized by low power with small size and weight.

The invention discloses a continuous Doppler US imaging system orthogonal intrinsic signal generation device, which comprise a field programmable gate array (FPGA), a crystal oscillator, a first digital-analog converter and a second digital-analog converter. The output end of the field programmable gate array (FPGA) is connected with the input ends of the first digital-analog converter and the second digital-analog converter; the crystal oscillator is respectively connected with the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the crystal oscillator is used for supplying synchronizing clock signals to the field programmable gate array (FPGA), the first digital-analog converter and the second digital-analog converter; the field programmable gate array (FPGA) is used for outputting the sine value corresponding to the phase value to the first digital-analog converter according to the input phase value and outputting the cosine value corresponding to the phase value to the second digital-analog converter; the first digital-analog converter is used for converting the sine value into the corresponding analog signals; the second digital-analog converter is used for converting the cosine value into the corresponding analog signals.

A transmission signal and a pilot signal are predistorted by a digital predistorter 13 by use of a power-series model, and the predistorted output is converted by a digital-analog converter 14 to an analog signal. The analog signal is up converted by a frequency converter 15 to an RF-band signal, which is transmitted after being power-amplified by a Doherty amplifier 16. The pilot signal is extracted by a pilot signal extractor 17 from the output from the Doherty amplifier, and the extracted pilot signal is down converted by a frequency converter 18 to a baseband signal. The baseband pilot signal is converted by an analog-digital converter 19 to a digital pilot signal. A control part 21 detects an odd-order distortion component from the digital pilot signal, and based on the detected result, controls parameters of the digital predistorter.

Digital duty cycle correction circuits are provided including a duty cycle detector circuit configured to generate first and second control values associated with a first internal clock signal and a second internal clock signal, respectively. A comparator circuit is also provided and is configured to compare the first control value to the second control value and provide a comparison result. A counter circuit is configured to perform an addition and/or a subtraction operation responsive to the comparison result to provide a digital code. A digital to analog converter is configured to generate third and fourth control values responsive to the digital code. Finally, a duty cycle corrector circuit is configured to receive first and second external clock signals and the first through fourth control values and generate the first and second internal clock signals having a corrected duty cycle. The first and second control values are received over a first path and the third and fourth control values are received over a second path, different from the first path. Related methods of operating duty cycle correction circuits are also provided.

A phase shift and duty cycle correction circuit is disclosed herein as comprising a programmable digital to analog converter (DAC), a storage device (e.g., a capacitor), a charge sub-circuit and dump sub-circuit for charging and discharging the storage device, respectively, a comparator, and a clock driver circuit. A linearly increasing (or ramped) voltage waveform is generated within the storage device by the charging and discharging actions of the charge and dump sub-circuits; a periodic process which is controlled by opposite phases of the input clock. By programming the DAC control input to change the slicing threshold of the ramped waveform, the circuit and method described herein provides a means for programmable phase shifting and duty cycle correction.

Methods and apparatus are described herein that make use of complex tuning, the inherently repetitive nature of sampled signals, and programmable digital filtering to create a flexible digital up-conversion system that utilizes a digital-to-analog converter (DAC) with a fixed effective sample rate while still being adapted for tunability over a wide frequency range. With a knowledge of the fixed effective sample rate of the DAC and a desired frequency of up-conversion and combining complex tuning at baseband and up-sampling by a factor of N with a programmable passband filter configured to select one of a plurality of signal images resulting from the up-sampling, it is possible to translate a baseband input signal to a wide range of frequencies above or below F_s, without changing the sampling rate of the fixed rate DAC used in the up-conversion process.

Consistent with the present disclosure, data, in digital form, is received by a transmit node of an optical communication, and converted to analog signal by a digital-to-analog converter (DAC) to drive a modulator. The modulator, in turn, modulates light at one of a plurality of wavelengths in accordance with the received data forming a plurality of corresponding carriers. The plurality of carriers are then optically combined with a fixed spacing combiner to form a superchannel of a fixed capacity. Accordingly, the number of carriers are selected according to a modulation format and symbol rate to realize the fixed capacity, for example. The superchannel is then transmitted over an optical communication path to a receive node. At the receive node, the superchannel is optically demultiplexed from a plurality of other superchannels. The plurality of carriers are then supplied to a photodetector circuit, which receives additional light at one of the optical signal carrier wavelengths from a local oscillator laser. An analog-to-digital converter (ADC) is provided in the receive node to convert the electrical signals output from the photodetector into digital form. The output from the ADC is then filtered in the electrical domain, such that optical demultiplexing of the carriers is unnecessary.

An adjustable compensation offset voltage is applied to a comparator to vary turn-off timing of a synchronous rectifier. A comparator output indicates when current through an inductor coupled to the synchronous rectifier should be approaching zero. If the synchronous rectifier is turned off before the current through the inductor reaches zero, the compensation offset voltage is adjusted to delay the synchronous rectifier turn-off for the next switching cycle. If the synchronous rectifier is turned off after the current through the inductor reaches zero, the compensation offset voltage is adjusted to advance the synchronous rectifier turn-off for the next switching cycle. An up/down counter, in conjunction with a digital to analog converter, may be used to provide the adjustment to the compensation offset voltage. The adjustable compensation offset voltage improves the accuracy of synchronous rectifier turn-off in relation to a zero inductor current, thereby improving power converter efficiency.

A method for driving a load by using an output stage amplifier in full bridge configuration whose supply is modulated by means of a fast switching power converter, controlled in order to maintain the stage's output common mode at its minimum voltage, is presented. The modulation of the switching power converter output is obtained by a feedback control system regulating directly the voltage of the bridge output stage terminals. This bridge unipolar class H stage allows driving the load with high accuracy and improved efficiency without introducing switching noise and EMI at the load terminals typical of PWM driving. This method can be applied with the same benefits to class AB, pseudo class AB or to class A output stages. When this method is associated with an imposed current driving approach and with a current oversampling digital to analog converter the resulting advantages are very significant for accurate motor control applications.

An earpiece for real-time audio processing of ambient sound includes an ear bud that provides passive noise attenuation to the earpiece such that exterior ambient sound is substantially reduced within an ear of a wearer, an exterior microphone that receives ambient sound and converts the received ambient sound into analog electrical signals, and an analog-to-digital converter that converts the analog electrical signals into digital signals representative of the ambient sounds. The earpiece further includes a digital signal processor that performs a transformation operation on the digital signals according to instructions received from a mobile device, the transformation operation transforms the digital signals into modified digital signals, a digital-to-analog converter that converts the modified digital signals into modified analog electrical signals, and a speaker that outputs the modified analog electrical signals as audio waves.

A method for reducing the complexity of a multi-bit DAC in a sigma-delta ADC. The DAC resolution can be made to be less than that of the quantizer by canceling truncation error present in multi-bit DACs. Truncation errors are introduced by differences between the digital output word of the quantizer and the digital input word of the feedback DAC(s). The truncation error(s) can be cancelled and eliminated from the system transfer function. A preferred embodiment comprises expanding all feedback loops in the ADC, adding an adjusted truncation error for each feedback loop to an inner feedback loop, and then calculating a correction term for each adjusted truncation error. The correction term can be calculated by zeroing all signals except for the adjusted truncation error being canceled and then calculating a truncation error transfer function.

Digital to analog converter circuits and methods are provided for producing an analog output voltage indicative of a digital input signal with at least partial insensitivity to error gradients. Described are split-core resistive elements, which include a plurality of one-dimensional or multi-dimensional resistive strings, that may be used to reduce or substantially eliminate the effects that error gradients have on the linearity of the analog output voltages of a resistive string or interpolating amplifier DACs. The resistor strings that make up the split-core resistive elements are configured in such a manner that combining respective output voltages from each of the resistor strings results in an analog output voltage that is at least partially insensitive to the effects of error gradients.

Provided are a data driving circuit of an organic light emitting display and an organic light emitting display comprising the same. The organic light emitting display comprises a reference pixel controller, a data driver, and a display panel. The reference pixel controller comprises a light detector for detecting an amount of light emission of a reference pixel and outputting a first control signal thereof and a reference current controller for outputting a second control signal controlling an amount of a reference current according to the first control signal. The data driver comprises a current source for outputting a current having the same amount as the reference current according to the second control signal and a digital-analog converter for outputting a data current by scaling the current having the same amount as the reference signal to be proportioned to a data signal. The display panel formed of pixels, each of which comprises an organic light emitting device that emits light in accordance with the data current.

A data driver and a light emitting diode display device including the circuit that cause a pixel current through the light emitting diode to be independent of the threshold voltage of a transistor driving the light emitting diode. The data driver includes a voltage digital-analog converter for generating a data voltage and a current digital-analog converter for generating a sensing current, both corresponding to input data, and a voltage control block for receiving the pixel current that corresponds to the data voltage and is fed back from the pixel to the voltage control block changing the amount of current charging a capacitor in the voltage control block and controlling the data voltage supplied to the pixel. Controlling and adjusting the data voltage helps uniformity in the display brightness regardless of non-uniformity of transistors in each pixel.

A method and apparatus is provided for DC level control in a line card. The method includes receiving a digital input signal, determining a first DC component value of the digital input signal at a first preselected time, and determining a second DC component value of the digital input signal at a second preselected time. The method further includes determining a difference between the first DC component value and the second DC component value. The method includes providing the first DC component value to a digital-to-analog converter in response to determining that the difference is less than a first preselected value. The apparatus includes a digital-to-analog converter and logic. The logic is coupled to the digital-to-analog converter, wherein the logic is capable of receiving a digital input signal, determining a first DC component value of the digital input signal at a first preselected time, and determining a second DC component value of the digital input signal at a second preselected time. The logic is farther capable of determining a difference between the first DC component value and the second DC component value, and providing the first DC component value to the digital-to-analog converter in response to determining that the difference is less than a first preselected value.