187 results about "Digital analog converter" patented technology

The invention provides an electrostatic driving micro-electro-mechanical device and a driving method thereof, the device comprises at least one electrostatic driving micro-electro-mechanical device, the device comprises a rotating support and at least one one-dimensional direction driving unit, and the first one-dimensional direction driving unit comprises a first electrode and a second electrode which are arranged in the first direction of the rotating support; the electrostatic drive micro-electromechanical device is further provided with a controller, the controller outputs digital signals to the digital-analog converter, the digital-analog converter outputs analog signals to the first electrode and the second electrode through the multi-way change-over switch, the multi-way change-over switch comprises a first selection switch, the first selection switch is a single-pole double-throw change-over switch, and the second selection switch is a single-pole double-throw change-over switch. A static contact of the first selection switch receives an analog signal output by the digital-to-analog converter, and a movable contact of the first selection switch selectively outputs the analog signal to the first electrode or the second electrode. The invention further provides a driving method of the driving device. The electrostatic driving micro-electro-mechanical device is compact in structure and low in production cost.

The invention provides a temperature drift compensation method, device and equipment for laser ranging in a low-temperature scene and a medium, and the method comprises the steps: building a temperature-drift model through the fine calibration of a laboratory; laser temperature measured by the double temperature sensors is obtained, the laser chip temperature is obtained through Kalman filtering, and a temperature-drift model is called to calculate the wavelength drift distance and the power drift distance at the current temperature; calculating a TEC target temperature compensation amount according to the wavelength drift amount, and calculating a driving current compensation amount according to the power drift amount; and based on the driving current compensation amount, a digital-to-analog converter is adopted to update laser driving current compensation power drift, so that the problem of low track detection precision by adopting laser ranging in a severe low-temperature environment is solved.

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes an ADC with a continuous time integrator. The continuous time integrator includes an amplifier having an amplifier input and an amplifier output, a capacitor coupled between the amplifier input and the amplifier output, and a resistor. The resistor provides a first current for an integration in response to an analog input. The ADC also includes a DAC configured to generate a second current at an DAC output based on a digital output of the ADC and includes a switch circuit with a first switch circuit terminal coupled with the DAC output and a second switch circuit terminal coupled with the amplifier input. The switch circuit is configured to couple the DAC output with the amplifier input for a summation of the second current with the first current for the integration based on an integration control signal.

An analog to digital converter including a digital to analog converter (DAC), a comparator, and a controller. The DAC includes a sample node and a capacitor array controlled by a digital control input. The comparator compares a voltage of the sample node with a reference voltage to generate a comparison value. The controller presets the digital control input, prompts the DAC to sample the input voltage onto the sample node, resets the digital control input, and performs a conversion by successively adjusting the digital control input based on the comparison value to determine a digital output. A preset value is subtracted from the digital output to provide an adjusted digital output. A sample predictor predicts the next sample to determine the preset value used to adjust the sample node within a full scale range after DAC reset.

A spiking neural network is provided, wherein each neuron of the spiking neural network includes a RC or RLC circuit formed of passive elements. The RC or RLC circuit provides a corresponding spiking function. In some cases, a portion of each neuron of the spiking neural network is implemented in a digital processor and further includes a digital to analog converter between the portion implemented in the digital processor and the RC or RLC circuit. In some cases, the spiking neural network is implemented as a fully analog neural network.

The invention discloses an offset cancellation circuit, which comprises a signal conditioning unit used for processing an input signal and outputting a first current signal, an offset cancellation unit used for removing offset current in the first current signal and outputting a second current signal, and a signal processing unit used for processing the second current signal and eliminating offset voltage, the detuning elimination unit specifically comprises a chopper, a digital analog converter, a successive approximation register logic module and a comparator which are connected in sequence, and through multi-level detuning elimination, the precision of the whole circuit is improved, the processing capacity for weak signals is enhanced, the anti-interference capacity is improved, and noise is reduced; the method ensures the stability of long-time operation, and has a wide application prospect in the field of high-precision signal processing.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention discloses a lunar exploration cubesat measurement and control responder system and a transmitting signal coherent carrier generation method thereof, and the system comprises a frequency mixer, a receiving local oscillator phase-locked loop, an intermediate frequency sampling analog-to-digital converter, a voltage-controlled oscillator, a digital-to-analog converter, a transmitting local oscillator phase-locked loop and a carrier tracking loop. Wherein the frequency mixer generates an intermediate-frequency signal according to radio frequency input and a local oscillation signal, the intermediate-frequency signal is output to the intermediate-frequency sampling analog-to-digital converter after band-pass filtering, and the intermediate-frequency sampling analog-to-digital converter outputs the intermediate-frequency signal to the carrier tracking loop after the intermediate-frequency signal is subjected to down-conversion processing of an X-band radio frequency signal; the carrier tracking loop outputs a digital signal to the digital-to-analog converter to generate an analog voltage for controlling the voltage-controlled oscillator; the voltage-controlled oscillator controls the output frequency through the voltage of the digital-to-analog converter; receiving a reference signal output by the local oscillator phase-locked loop according to the voltage-controlled crystal oscillator, performing phase-locked frequency multiplication processing and generating a local oscillator signal; and the transmitting local oscillator phase-locked loop performs phase-locked frequency multiplication processing on the reference signal. According to the invention, in an analog-digital combination mode, a digital frequency-locked phase-locked loop is used for controlling the output voltage of a DAC to control the frequency of a reference VCXO, so that carrier tracking of a radio frequency-intermediate frequency-digital large loop closed loop is completed; downlink coherent carriers can be directly obtained by PLL (Phase Locked Loop), and the requirement of downlink / uplink forwarding ratio 880 / 749 is strictly met.

The invention discloses a capacitor mismatch error shaping circuit and method suitable for a multi-bit quantization Sigma-Delta ADC, and belongs to the technical field of integrated circuits, and the capacitor mismatch error shaping circuit comprises a data weight averaging module which is used for adopting a data weight averaging technology for high-bit quantization code words, and correcting the high-bit quantization code words according to the data weight averaging technology; averaging the mismatch error of the capacitor corresponding to the high-order quantization code word to obtain an averaged high-order capacitor; and the mismatch error shaping module is used for taking the averaged high-order capacitance as a reference, adopting a mismatch error shaping technology, keeping low-order feedback of the current low-order quantization code word of the lower polar plate of the capacitive digital-to-analog converter during Sigma-Delta ADC sampling, and realizing subtraction operation between two adjacent low-order quantization code words. According to the invention, the error caused by the mismatch of the CDAC capacitor fed back by the multi-bit quantization Sigma-Delta ADC can be effectively suppressed, the linearity of the system is improved, and the circuit overhead is remarkably reduced.

A system for scalable two-dimensional surface code comprises four sub-lattices of qubits, each selectively controlled by a set of analog lines. Eight sets of analog lines selectively control eight sets of inter-qubit couplers. The qubits and couplers have response homogenization devices comprising control structures to apply analog signals and DACs to apply static bias to qubits and couplers. A second surface code layer compensates for defective qubits. A quantum processor and a method of moving data within a quantum processor are described. The quantum processor has quantum logic units with a plurality of physical qubits and couplers. The logic unit has a plurality of logical qubit blocks making up 2-local interaction registers. A shift register block with one or more logical qubit blocks and merge blocks connecting adjacent logical qubit blocks are provided. The shift register block is selectively communicatively coupled to 2-local interaction registers by a merge block.

A processing device is built into an output device, which uses a DA converter to output a predetermined voltage value serving as a reference. The processing device includes an input voltage acquisition unit, which acquires a positive reference voltage value and a negative reference voltage value output as internal reference voltage values from an internal voltage supply in the output device. An output voltage acquisition unit acquires a positive output voltage value and a negative output voltage value output from the DA converter. An adjustment unit adjusts a set value of the DA converter and adjusts the acquired positive output voltage value and negative output voltage value toward the acquired positive reference voltage value and negative reference voltage value.

A dual tank LC-tuned Voltage Controller Oscillator (LC VCO) comprising a differential pair of cross-coupled transistors (M1, M2, M3, M4) produces a negative impedance by keeping a lower drain swing and a sufficient gate swing. The gate terminals of first and second transistors M1, M2 and third and fourth transistors M3, M4 are separated through a series of two inductors L1, L2 and two cross-coupled capacitors are connected between the drain and gate terminals of cross-coupled transistors to attenuate the output swing. The VCO tank further comprises two R2R Digital to Analog Converters (DAC) to bias both NMOS and PMOS cross-coupled pairs of transistors, to produce a common mode noise.

This disclosure generally relates to processor systems comprising printed circuit boards, I / O chips and processor chips with mated contacts. Contacts are formed on an upper surface of a printed circuit board having a through-hole and on a processor chip inside the through-hole. The processor chip may be a superconducting quantum processor chip comprising qubits, couplers, Digital to Analog converters, QFP shift registers and analog lines. Contacts are formed on an upper surface on an I / O chip and mated with the contacts on the printed circuit board and the processor chip. Contacts may be Indium bump bonds or superconducting solder bonds. The processor chip and the I / O chip may include a shield layer, a substrate layer and a thermally conductive layer.

Display device (10) with a substrate (12) and a display area (30) arranged on the substrate (12), wherein the display area (30) comprises a plurality of pixels (32) arranged in a two-dimensional array, wherein the display device (10) comprises the following: a first control loop (40) arranged on the substrate (12), wherein the first control loop (40) comprises a plurality of first input signal lines (XSR control signal, 42, 44, 45), (Idata, 46), (Yck, 48), a plurality of first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) and a plurality of data lines (DR1, DG1, ..., 64), wherein the data lines (DR1, DG1, ..., 64) are arranged to provide image data for the pixels (32), wherein the first electronic components (XSR(1), XSR(2), ..., 52), (Latch(R1), Latch(G1), ..., 62), (S1, S2) are configured to receive data signals from the first input signal lines specifying the image data; a second control loop arranged on the substrate (12), wherein the second control loop (70) comprises a plurality of second input signal lines (YSR control signal), a plurality of second electronic components (YSR(1), YSR(2), ..., 82) and a plurality of sampling lines (P1, P2, ...), wherein the sampling lines (P1, P2, ...) are arranged to provide timing control signals for the pixels (32), and wherein the second electronic components (YSR(1), YSR(2), ..., 82) are configured to receive timing pulses from the second input signal lines specifying the timing control signals; and a connecting cable (20) comprising a plurality of first connecting lines (24) and a plurality of second connecting lines (24), wherein the first input signal lines (42, 44, 45), (Idata, 46), (Yck, 48) are electrically connected to the first connecting lines (24) to receive the data signals, and the second input signal lines (YSR control signal) are electrically connected to the second connecting lines (24) to receive the time pulses, and wherein the data signals are digital signals, wherein the digital signals have an amplitude range, wherein the connecting cable (20) is further configured to provide reference signals for controlling the image data in the first control circuit (40) and for controlling the timing control signals in the second control circuit (70), wherein the reference signals have a signal voltage range, wherein the amplitude range of the digital signals is greater than the signal voltage range of the reference signals.

The utility model provides a light compensating circuit and a pulse blood oxygen simulation system, which relates to the technical field of blood oxygen detection and comprises an ambient light detection circuit, an ambient light simulation generation circuit and a compensation superposition circuit. The ambient light detection circuit comprises a light sensor, a first operational amplifier, a first resistor and a microprocessor; the optical sensor is connected with the inverted input end of the first operational amplifier, the inverted input end of the first operational amplifier is connected with the output end of the first operational amplifier through the first resistor, and the output end of the first operational amplifier is connected with the input end of a digital analog converter port of the microprocessor. The output end of the digital analog converter port of the microprocessor is connected with the first input end of the compensation superposed circuit, and the output end of the ambient light analog generation circuit is connected with the second input end of the compensation superposed circuit. Therefore, the resistance of the system to ambient light interference is effectively improved.

The utility model discloses a cooking device which comprises a shell, a plurality of groups of containing grooves are formed in the surface of the top of the shell, weighing sensors are embedded in the centers of the bottoms of the containing grooves, and the detection ends of the weighing sensors are connected with heating plates; the pot bodies are placed in inner cavities of the containing grooves respectively, the bottoms of the pot bodies make contact with the top of the heating disc, a pot cover is connected to an opening of each pot body in a clamped mode, the top of each pot cover is communicated with an exhaust pipe, and the gas outlet end of each exhaust pipe is fixedly connected with a gas sensor. The weight of rice and water before and after cooking is metered through the weighing sensor, substances in gas are detected through the gas sensor, and data collected by the weighing sensor and the gas sensor can be visually presented to a user through the operation screen through the digital-to-analog converter and the single-chip microcomputer. And the cooking taste of the rice is digitalized.

A potentiostat architecture includes one or more feedback loops configured to regulate and maintain electrode potentials while measuring a sensing current. At least one of the feedback loops include a comparator configured to sense a voltage difference and output a signal based on the voltage difference, a digital loop filter configured to receive the signal from the comparator and output feedback digital bits related to a control, and a digital to analog convertor configured to receive the signal from the comparator and output feedback digital bits related to a control.

An analog in-memory computing (AIMC) system includes a plurality of tiles. A plurality of vertically stacked tiers are present on each tile. Each tier comprises a crossbar of resistive memory devices, configured to encode a matrix of weights. A digital to analog convert (DAC) is shared by the plurality of tiles. The DAC is configured to encode an input vector to voltage pulses applied on the crossbar. An analog to digital converter (ADC) is shared by the plurality of tiles, and includes a register of counters. The ADC is configured to measure an induced current on each column of the crossbar and digitize the induced current into a digital value. A programmable logic controller is configured to: control the ADC to retain integration values between integrations performed for each tier. An accumulation of partial integration results is performed in-situ of the tile.

The crossbar array includes a plurality of memory elements. An analog-to-digital converter (ADC) is electrically coupled to the vector output register. A digital-to-analog converter (DAC) is electrically coupled to the vector input register. A processor is electrically coupled to the ADC and the DAC. The processor may be configured to determine whether a quotient of input vector data and output vector data from the crossbar array is within a threshold, and if not within the threshold, determine a change data value between the output vector data and the input vector data, and write the change data value to the memory element of the crossbar array.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.

The invention discloses a transposition bias system for closed-loop control, and relates to the technical field of rotary table control, the transposition bias system comprises a transposition bias unit and a stable closed-loop system, the transposition bias unit is used for processing electric lock large impact caused by an interference source, machine shake and bias angle change caused by abnormal out-of-tolerance; the offset angle of the transposition offset unit is subjected to real-time and prediction processing according to actual angle measurement calculation and different states such as large impact, machine shake and abnormal out-of-tolerance of the electric lock, external and self interference source signals are received through sensing current closed-loop adjustment and the transposition offset unit, stabilization processing is carried out through offset angle changes, and offset closed-loop stability is achieved. The stable closed-loop system collects a high-precision digital-to-analog converter signal, a frictional resistance signal and a wiring harness torque signal, stable bias algorithm resolving is carried out through the circuit system, and finally state processing of the bias system is carried out; according to the invention, the control precision of the rotary table can be improved.

The utility model discloses a signal generator circuit with multiple residual current waveform generation capabilities, a microcontroller and an external crystal oscillator circuit comprise a microcontroller U7, the microcontroller U7 generates a B-type residual current waveform through a residual current waveform generation program specified by a running command, and the B-type residual current waveform is converted into a B-type residual current waveform. And the waveform meeting the detection requirement of the new national standard GB / T18487.1-2023 on the residual current sensor can be generated. Secondly, a high-performance digital-to-analog converter (DAC) is built in the microcontroller U7, and high-sampling-rate conversion is supported; in the circuit, the 20KHz high-sampling-rate DAC can ensure high smoothness of output waveforms, and the DAC can output sine waves or other waveforms close to an ideal state by accurately controlling conversion of digital signals into analog voltage signals, so that various application requirements are met.

The application discloses an R-2R digital-analog converter with an auxiliary calibration structure and relates to the technical field of high-precision digital-analog conversion. The converter comprises a main DAC, a calibration quantity calculation module, a compensation code generation module, an auxiliary DAC and an operational amplifier circuit. The main DAC converts a digital input into an analog current. The calibration quantity calculation module generates a 15-bit compensation code containing a 1-bit sign bit and a 14-bit data bit through a 24-bit ADC, a comparator and successive approximation logic, and only calibrates the high 12 bits of the main DAC bit by bit, and the low 4 bits do not need to be calibrated. The compensation code generation module generates a total compensation code through gating by a multiplexer and superposition by an adder. The auxiliary DAC is a 14-bit binary current type structure, and realizes bidirectional compensation in cooperation with a positive and negative reference voltage source. The application has the advantages of short calibration period, small storage consumption, no need for additional bias calibration, excellent linearity, and suitability for application in the fields of wireless communication, biological medicine and the like, and meets the application requirements of high resolution and high precision.

The present invention proposes a highly flexible storage computing array, belonging to the technical field of semiconductor non-volatile memories and in-memory computing. In the 1T1R array of the present invention, the word line direction is perpendicular to the input direction. The word line driver is used to control the word line input power supply voltage or ground voltage of the 1T1R array to turn on or off a column of word lines. The input unit is provided with an input register, a voltage multiplexer, and a row multiplexer. The voltage multiplexer selects one of the multiple voltages generated by the linear regulator as the input according to the value of the input register. The row multiplexer is connected to the source line of the 1T1R array. The bit lines of the 1T1R array are connected to the clamping circuit and the analog-to-digital converter through the column multiplexer in the output unit. By using the highly flexible storage computing array provided by the present invention, unnecessary power consumption can be saved, multi-value input can be achieved without an analog-to-digital converter, the computing speed is improved, and the number of times the array is turned on and the resulting power consumption are reduced.

The application discloses a direct digital frequency synthesizer based on RBF neural network of phased optimization, which comprises a phase accumulator responsible for generating a phase signal, an RBF neural network module responsible for converting the phase signal into a digital amplitude signal, a digital-analog converter responsible for converting the digital amplitude signal into a low-frequency sawtooth signal and a low-pass filter responsible for converting the sawtooth signal into a smooth analog signal. The RBF neural network module comprises a hidden layer and an output layer, each node in the hidden layer has a corresponding radial basis function, so as to map a corresponding characteristic value for each input phase information, multiply the corresponding characteristic value of each node with the corresponding weight in the output layer, and then sum up to obtain an amplitude value corresponding to the phase information. Compared with the prior art, the application introduces the RBF neural network, so that the direct digital frequency synthesizer has stronger scalability and adaptability when processing complex and nonlinear frequency synthesis tasks.

Vehicle battery control system, including: a battery unit (208), comprising: a first and a second pole (210, 212, 214, 220); a third and a fourth pole (216); a large number of individually stored batteries (224); and a plurality of switches (232) configured to connect one of the batteries (224) to and from one of the first, second, third and fourth poles (210, 212, 214, 220, 216); a mode module (604) configured to set an operating mode based on at least one of a plurality of available operating parameters; and a switch control module (240) configured to control the plurality of switches (232) based on the operating mode, a pre-charge circuit (404) comprising a comparator (412), an output (420), a digital-to-analog converter DAC (424), a pre-charge switch (428) and a pre-charge capacitor (448), wherein the pre-charge capacitor (448) is connected in parallel to the first and second poles (210, 212, 214, 220), wherein the pre-charge circuit (404) is configured to connect a first battery (224-1) to the pre-charge capacitor (448), wherein the pre-charge circuit (404) is further configured to connect a second battery (224-2) to the pre-charge capacitor (448) in response to a determination that the pre-charge capacitor (448) has been charged to a predetermined voltage, wherein the DAC (424) is configured to adjust the output (420) so that the comparator (412) opens the pre-charge switch (428), wherein the switch control module (240) is configured to open a first switch (232-1) and to close a second switch (232-2) and a third switch (232-3), wherein the first battery (224-1) and the second battery (224-2) are configured to charge the pre-charge capacitor (448) when the pre-charge switch (428) is closed.

The invention relates to the technical field of air pre-heaters, and discloses an air pre-heater heat transfer element blockage intelligent detection system which comprises a middle rotating shaft, a hot end middle beam, a cold end middle beam, a rotor and a control box, a heat transfer element is arranged on the rotor, and a light source generator facing the rotor is arranged on the cold end middle beam. A visible light camera device facing the rotor and corresponding to the light source generator is arranged on the hot end middle beam, power sources of the light source generator and the visible light camera device are both connected with the control box, and the visible light camera device is further connected with the control box through a digital-to-analog converter. According to the intelligent blockage detection system for the heat transfer element of the air pre-heater, the blockage condition of the element in a certain area of the air pre-heater is detected by adopting the penetration brightness of the light source, and the intelligent blockage detection system has the advantages of visual operation, simplicity in system control operation, rapidness and accuracy in positioning and high feasibility.

The present invention provides a DA conversion device and the like that use the range of low voltage dependency of a MOS capacitor to make it possible to reduce nonlinearity of an output voltage. A charge scaling type DA conversion device comprising a high-order bit side capacitor array and a low-order bit side capacitor array that are connected via an attenuation capacitor comprises a control circuit that applies a voltage, to a plurality of capacitors of the high-order bit side capacitor array and a plurality of capacitors of the low-order bit side capacitor array, so that all of the capacitors have a positive bias voltage or a negative bias voltage at the times of reset and conversion of the DA conversion device, wherein at least one of a reference voltage of the low-order bit side capacitor array and a reset voltage is set to a value different from a reference voltage of the high-order bit side capacitor array.

A data driving circuit of a display device includes a digital-analog converter which includes a gamma reference voltage generator to output gamma reference voltages in response to a first-group signal of a digital signal, and a voltage selector to output, as a gamma selection voltage, one of the gamma reference voltages in response to a second-group signal of the digital signal. The data driving circuit also includes a first amplifier to receive the gamma selection voltage and to output a first conversion voltage, a boosting circuit to convert the first conversion voltage into a second conversion voltage in response to the first-group signal of the digital signal, and a second amplifier to receive the second conversion voltage and to output an analog signal.

The present disclosure provides for crossbar circuits with minimized write disturbance. A crossbar circuit may include a plurality of bit lines intersecting with a plurality of word lines, a plurality of select lines, a plurality of cross-point devices, and a ramp-rate adjustable DAC that comprises a control circuit and an operational amplifier. An input of the operational amplifier is connected to a capacitor. The control circuit may generate, based on a digital input, a control signal. To program a cross-point device of the crossbar circuit, the capacitor may be charged using a reference current. As the charging rate of the capacitor is limited by the reference current, and the charging duration is controlled by the control signal, thus the output of the operational amplifier corresponds to the digital input and may be applied to the cross-point device as a programming signal with limited slew-rate adjustable by the reference current.