2056 results about "Synchronizing" patented technology

In a display system capable of displaying images fed from a plurality of sensing devices on an indicator, horizontal and vertical synchronizing signals of the individual measuring devices are synchronized with one another and desired image signals are selected for on-screen presentation during each successive horizontal scanning period, whereby operator-selected multiple images are displayed.

An apparatus and method for improving the communication capabilities of computer systems is disclosed. The most preferred embodiments of the present invention use a series of data buffers and data registers to process an incoming high speed data signal. By using the buffers and registers, the incoming signal can be reformatted and manipulated at a much lower frequency than the original transmission frequency. The deserializer of the present invention also samples a greater portion of the incoming data signal than usual to further increase reliability. These various features of the invention provide for a more stable and reliable communication link and will also provide a less expensive solution for serialization/deserialization. The present invention includes a serializer that receives parallel data input from a computer and serializes the data for transmission over a high-speed serial communication link. On the receiving end, the present invention provides a deserializer that can quickly and efficiently transform the serial data back into parallel form for use within the computer system on the receiving end. By utilizing two related clock signals, one clock signal being an integer multiple of the other, a self-synchronizing serializer/deserializer can be created. In addition, by increasing the size of the data sample on the receiving end, the comparisons necessary to retrieve a parallel signal from a serial transmission can occur at a much lower frequency than the frequency of the serial transmission. In the most preferred embodiment, the invention is provided as a integrated solution manufactured on a Peripheral Component Interconnect (PCI) card, thereby allowing the present invention to be easy installed into existing computer systems.

A format converter includes: a microcomputer for receiving horizontal and vertical synchronizing signals from a host, determining a video mode, and generating data that indicates the number of dots per a period of a horizontal output signal; a W-PLL and time generator for receiving the data from the microcomputer, and generating a write clock signal; an R-PLL and time generator for receiving the data and the horizontal synchronizing signal respectively generated by the microcomputer and the host, and generating a read clock signal; an AD converting section for sampling an analog picture signal received from the host according to the write clock signal of the W-PLL and time generator, and converting it to a digital picture signal; and a format converting section for storing the picture signal received from the AD converter according to the period of the write clock signal of the W-PLL and time generator, and converting the format of the stored picture signal according to the read clock signal received from the R-PLL and time generator.

A method is provided for operating a dual-use wireless device. The method includes: receiving an external timing signal (460) at a first wireless circuit (480) in the device (605); synchronizing a first clock in the first wireless circuit with the external timing signal (610); sending a first internal timing signal (570) from the first wireless circuit to a second wireless circuit in the device, after the synchronizing (615); and listening for a remote periodic control signal at the second wireless circuit for a set monitoring time, a start of the monitoring time being based on the first internal timing signal (865). The second wireless circuit sends an association request if the second wireless circuit hears the remote periodic control signal within the monitoring time (875), and sends a local periodic control signal if the second wireless circuit does not hear the remote periodic control signal within the monitoring time (625).

A method and apparatus are generally disclosed for maintaining data integrity across distributed computer systems. In one embodiment, the method of the invention includes the step of transmitting an object from a server application to a client application. The method also includes the step of transmitting an object state from the server application to the client application. The method further includes the steps of synchronizing the object and object state between the server application and the client application, and updating the object by invoking a server application method after the step of synchronizing. An apparatus and article of manufacture for carrying out the steps of the method are also disclosed.

The invention provides a method and a device of transmitting and acquiring synchronous information blocks. The method comprises steps that according to a synchronous information block set SS burst Set mode, target mode index information is determined; the target mode index information is stored in every synchronous information block SS block, and the to-be-transmitted synchronous information block is acquired; by adopting a high frequency wave beam, user equipment in a target cell is periodically transmitted to the target synchronous information block; every SS burst Set comprises periodically transmitted synchronously burst SS burst of a first preset number; every SS burst comprises target synchronous information blocks of a second preset number are transmitted according to a space sequence. By adopting the method provided by the invention, the cell signal synchronizing of the user equipment in a 5G network is realized accurately and quickly.

A wireless data communication system is operable in a power saving mode wherein stations are synchronized to be in an awake state to receive synchronizing messages (TIM, PSYNC) and traffic indicator information and are changed to a doze state if they are not to receive data messages. In one embodiment all stations (20) communicate via a base station access point (16), which broadcasts synchronizing messages (TIM) at regular intervals identifying stations (20) that are to receive data messages. In another embodiment all stations (220) communicate directly with one another, one station assumes the role of a master station and broadcasts synchronizing messages (PSYNC), and stations (220) desiring to transmit data messages transmit traffic indicator messages (PTIM) to the appropriate destination stations (220), in a synchronized awake period just before the next synchronizing message (PSYNC) is expected to arrive.

In base station side equipment, a control channel for transmitting control information and a communication channel for transmitting information to each mobile station are spread with different synchronizing codes before being superposed by operating a switch to switch the output of an adder over to the output of a synchronizing code generator. Further, a synchronizing code is periodically inserted in a signal by one symbol length and the signal is transmitted over the superposed channel. In a plurality of base station side equipment, moreover, the synchronizing code and its transmission period are equal and the transmission timing is asynchronous and independent. A synchronizing correlator in mobile station side equipment obtains the correlation value of the whole chip phase in a synchronizing code transmission period using the synchronizing code and decides a base station which is transmitting the synchronizing code at the greatest correlating peak position to the closest one and further extracts symbol timing from the peak position.

The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit and a second frame synchronizing unit. The first and second synchronizing units synchronize with a first pattern, a second pattern at a first position and a second position, respectively. Thereafter, when the first position used for the synchronization by the first frame synchronizing unit is found to be in error, the first frame synchronizing unit synchronizes with the second pattern at the second position used by the second frame synchronization unit.

A method and system for maintaining synchronization between a local data cache and a data store is disclosed. The method includes comparing first validation information and second validation information, and synchronizing first data stored in a local data cache with second data stored in a data store, if the comparison indicates that the synchronizing is needed.

A method for start-up of a network, including a number of nodes, which are connected via channels. The nodes exchange information in the form of messages via the channels. The transition phase of a synchronizing node from its initial phase to a synchronized phase is separated in a first integration phase and a second subsequent cold-start phase. A synchronizing node in the integration phase listens to messages being sent from nodes in the synchronized phase and only reacts to an integration message (i-frame) if the integration message is a valid message. Furthermore, a synchronizing node, wherein integration of the synchronizing node to a set of already synchronized nodes was not successful after a specifiable period, changes into the cold-start phase, in which a cold-start procedure of the node is extracted, wherein in the cold-start phase the node does not react to integration messages of a node in the synchronized phase.

A video processor for endoscopic camera or for videoendoscopic probe associated with a color video sensor, the video processor comprising: a signal preprocessing circuit designed to be remotely connected to the video sensor through an electrical link without any intermediate connection device, the preprocessing circuit comprising a first signal processor for generating from image signals output by the video sensor raw video signals comprising a brightness signal and a color signal, these signals being not usable directly because they are phase shifted and are noisy due to synchronization residues, and a synchronizing circuit for synchronizing the video sensor and the first signal processor; and a remote auxiliary circuit comprising a second signal processor connected to the first signal processor through a low impedance electrical link providing good immunity to interference, the second signal processor generating from said raw video brightness and color signals at least one useful video signal according to an international video standard.

A first candidate selection portion 130 selects format candidates based on the horizontal synchronizing cycle and the vertical synchronizing cycle of an input video signal. A second candidate selection portion 140 selects formats having the tolerance ranges for the horizontal synchronizing cycles within which the horizontal synchronizing cycle of the input video signal falls as format candidates. A format decision portion 160 determines the format of the input video signal from format candidates from the first candidate selection portion 130 when format candidate(s) is obtained by the first candidate selection portion 130, and determines the format of the input video signal from format candidates selected by the second candidate selection portion 140 when no format candidate is obtained by the first candidate selection portion 130.

A wireless gaming method and wireless gaming-enabled mobile terminal are provided for enabling a number of players to participate simultaneously in a game using their mobile terminals. A wireless gaming method of the present invention includes inviting, if a multi-player gaming mode for a game is activated, at least one counterpart terminal on a short range wireless communication network by transmitting a multi-player gaming mode request message; synchronizing, if an acknowledge message is received in response to the multi-player gaming mode request message, game data with the counterpart terminal transmitted the acknowledge message; and generating a game screen with an image taken by the camera as a background image after the game is synchronized; and starting the game with the game screen.

A synchronization system in accordance with the principles of the invention includes a central synchronizing management unit, at least one synchronization distribution unit, and at least one network element. Each synchronization distribution unit receives synchronization and management information from the central synchronization management unit. This information may be transmitted directly from the central synchronization management unit, or it may be transmitted though another synchronization distribution unit in a group of a daisy-chained synchronization distribution units. The daisy-chained arrangement employs both active and passive optical paths. The central synchronizing management unit may query any synchronization distribution unit within the system to obtain performance statistics. Additionally, the central synchronizing management unit may detect faults within the system by setting performance monitoring thresholds and interrogating a synchronization distribution unit to determine whether a threshold has been exceeded. The synchronization distribution units are physically located in close proximity to the network elements they serve. Additionally, the management and synchronization information exchanged between the central synchronization unit and a synchronization distribution unit is carried over a bidirectional optical link.

The invention discloses a data processing and transmitting system of high-speed multichannel CCD (charge-coupled device), which comprises a CCD analog front end, a data processing unit, a high-speed serial transmission unit and a high-speed image data collection system which are sequentially connected. The CCD analog front end is used for converting an analog signal output by a CCD detector and subjected to sampling and pulse control into n channels of digital image data via n A/D (analog/digital) converters, transmitting the digital image data to the data processing unit, and acquiring data of each channel at the same time. The data processing unit is used for transmitting single-channel high-speed data streams, a data transmitter clock and a horizontal synchronizing signal acquired from integration of the digital image data to the high-speed serial transmission unit. The high-speed serial transmission unit is used for converting single-channel high-speed data streams via LVDS (low-voltage differential signaling) serial chips into high-speed LVDS data streams for transmitting. The high-speed image data collection system is used for collecting the high-speed serial LVDS data streams and realizing real-time storing and displaying of the image data.

A method for determining an instantaneous phase difference between time bases of at least two location anchors for a desired point in time (t), each of the location anchors having transmitting and receiving access to a joint broadcast transmission medium and a respective time base for measuring time, wherein a first of the location anchors broadcasts a first broadcast message at least twice; the first location anchor and at least a second of the location anchors receive the first broadcast messages; the second location anchor broadcasting a second broadcast message at least twice; and the second location anchor and at least the first location anchor receive the second broadcast messages. The location server calculates the instantaneous phase difference from a determined first and second clock model functions and from a time elapsed between a reference point in time and the desired point in time t.

This invention provides a multi-channel clock synchronizing method and a system, in which, a phase calibration theory is used and a phase calibration module takes received sampling clocks of a main device and a path of sampling clocks output by a drive module of a slave device as the phase calibration automatic control input signal to regulate the phase of a reference clock of the main device so as to realize accurate synchronizatin of main and slave devices, and the system includes a main device and at least one slave device and provides a DSP+FPGA module used in generating active synchronous signals and a control mode selecting module used in realizing selection of active and automatic modes, which can realize accurate synchronization of multi-channel clocks, and an operator can regulate phase difference of main and slave device actively when the clock system is lost at automatic synchronization to realize synchronization again.

An image pickup device includes an image sensing device and a driving unit. The image sensing device includes a first pixel group and a second pixel group. The first pixel group includes a plurality of pixels arranged as a two-dimensional array in a semiconductor substrate surface portion that receives incidence light from a subject. The second pixel group includes a plurality of pixels arranged as a two-dimensional array in the semiconductor substrate surface portion in an area overlapping the first pixel group while the pixels in the first pixel group do not disposed in the same positions as the pixels in the second pixel group. The driving unit outputs a picked-up image signal of one frame from the first pixel group exposed over one vertical synchronizing time period for each vertical synchronizing signal.

A number of laser beam stations emit vertically separated parallel planes and/or ray-planes of laser light that can be discriminated by their respective plane elevations, modulation of the laser light, time synchronizing, etc. Identifying the laser plane would also imply an identification of the source laser beam station, and thus a precise indication of the elevation at the point of optical intercept. Alternatively, a single laser beam station is used that can emit several different monochromatic color planes and/or ray-planes of laser light. Monochromatic laser diodes, for example, are used for point-light sources and rotating or on-end conical mirrors are used to convert the diode laser light to the required monochromatic color planes and/or ray-planes of laser light. Receivers, generally held on masts attached to motor grader, bulldozer, loader, and excavator machines are used to sense the vertical reference position of the monochromatic color planes and/or ray-planes of laser light, relative to the earth cutting blade of the machine. Fixed-color filters, color filter wheels, and/or linear array photodetectors are used to discriminate amongst the colors and to exactly sense the plane of intersection with the machine. The results of the sensing are either displayed to an equipment operator for manual adjustment of the blade to an automatic servo control system connected to hydraulically control the blade.

An interface circuit includes: a first synchronizing circuit for synchronizing a signal having a delay equal to or more than a predetermined period with respect to a reference clock, with the reference clock; a second synchronizing circuit for synchronizing a signal having a delay less than the predetermined period with respect to the reference clock, with the reference clock; a delay determining circuit for outputting a determination signal based on a delay of the signal relative to the reference clock; a delay determination setting circuit for outputting a path setting signal that designates an output value of one of the first synchronizing circuit and the second synchronizing circuit based on a preset value; and a delay selecting circuit for selecting and outputting an output value of one of the first synchronizing circuit and the second synchronizing circuit based on one of the determination signal and the path setting signal.