142results about "Parallel/series conversion" patented technology

The invention relates to the technical field of conversion circuits, and provides a converter drift suppression front-end circuit and a drift suppression method, and the circuit comprises a first signal processing circuit and a second signal processing circuit which are symmetrically distributed, and a high-frequency path and a low-frequency path which are arranged between the first signal processing circuit and the second signal processing circuit; wherein a normal-phase input signal forms a first node signal after passing through the first signal processing circuit, and a reverse-phase input signal corresponding to the normal-phase input signal forms a second node signal after passing through the second signal processing circuit; the first node signal and the second node signal are respectively input into a normal-phase input end and an inverted-phase input end of a converter CTLE through the high-frequency path or the low-frequency path; and the low-frequency path comprises a fully differential amplifier with resistance proportion negative feedback. According to the invention, baseline drift can be effectively suppressed, so that the stability of converter receiving end signals is improved.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

Transvascular diaphragm pacing systems (TDPS) and methods are disclosed for providing respiratory therapy to a patient. The TDPS can provide rapid insertion and deployment of endovascular pacing electrodes in critically ill patients who require intubation and invasive PPMV in order to support the physiological requirements of the human ventilatory system. The systems and methods make best use of the contractile properties of the diaphragm muscle and prevent muscle disuse and muscle atrophy. This can be carried out by engaging the phrenic nerves using patterned functional electrical stimulation applied to endovascular electrodes that are temporarily and reversibly inserted in central veins of the patient, such as the left subclavian vein and the superior vena cava. The TDPS can be designed to seamlessly interface with any commercially available positive-pressure ventilatory assistance / support equipment such as is commonly in use in hospital intensive care units (ICU) for treating critically ill patients with breathing insufficiencies, pain, trauma, sepsis or neurological diseases or deficits.

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.

A system includes a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs. The system also includes an edge swallower or a pulse swallower coupled to the clock input of the deserializer.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

It is provided an improved integrated circuit (10) is provided for driving fast links in radiation-hard applications comprising a PISO device (1) including a transmitting block (2) defining a first basic logic and configured to transmit first data in parallel (1p) correlated to a first low frequency clock signal (1l), a PLL (3) configured to receive a first reference clock signal (1r) and to generate at least a first high frequency clock signal (1a) and in including at least a first FD (30) configured to generate at least a first control clock signal (1c), a Serializer (4) operatively connected to the PLL (3) and the transmitting block (2) and configured to receive at least the first data in parallel (1p) and the first high frequency clock signal (1a) and reorganize the first data in parallel (1p) on the basis of a first load signal (4c) in first serial data (1s) related in frequency to the first high clock signal frequency (1a), in which the first PD (30) is operatively connected to the transmitting block (2), the first low frequency clock signal (1l) coincides with the first control clock signal (1c) and the transmitting block (2) transmits the first low frequency clock signal (1l) to the Serializer (4) so as to determine the first load signal (4c) in proportion to the first low frequency clock signal (1l); and a SIPO device (5) including a receiving block (6) defining a second basic logic and configured to receive second data (5p) correlated to a second low frequency clock signal (5l), CDR apparatus (7) configured to receive second serial data (5s), to generate at least a second high frequency clock signal (5a) and in including at least a second FD (70) configured to generate at least a second control clock signal (5c), a Deserializer (8) operatively connected to the CDR apparatus (7) and to the receiving block (6) and configured to receive at least the second serial data (5s) and the second high frequency clock signal (5a) and reorganize the second data (5s) on the basis of a second load signal (8c) in the second parallel data (5p) correlated in frequency to the second high frequency clock signal (5a), wherein the second PD (70) is operationally connected to the receiving block (6), the second low frequency clock signal frequency (5l) coincides with the second control clock signal (5c) and the receiving block (6) transmits the second low frequency clock signal (5l) to the Deserializer (8) in order to determine the second load signal (8c) proportionally to the second low frequency clock signal (5l); and wherein the Serializer (4) is operatively connected to the Deserializer (8) and to the CDR apparatus (7), the first serial data (1s) coincide with the second serial data (5s), the first parallel data (1p) they are equivalent to the second parallel data (5p), the first high frequency signals (1a) are equivalent to the second high frequency signals (5a) and the first low frequency signals (1l) are equivalent to the second low frequency signals (5l).

The application discloses a data sorting system and method. In the application, the data sorting system comprises an ADC chip, a sorting multiplexing module and a sorting control module. When the current state is a test mode, the ADC chip is used to transmit data clock and LVDS data to the sorting multiplexing module, then the sorting multiplexing module is used to generate parallel output data according to the data clock and the LVDS data, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. When the current state is the test mode, the ADC chip is used to transmit the data clock and the LVDS data to the sorting multiplexing module, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. The delay condition of the parallel output data can be processed by the sorting control module, so that the calibration between the data and the clock can be realized, and the LVDS data can be accurately sorted.

An apparatus (100) for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit (130) receiving an input signal from a signal path mixed with interference from a clock path. The apparatus (100) includes a phase interpolator circuit (120) implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit (140) to sample the input signal and the interference in every cycle. The apparatus (100) also includes an analog-to-digital converter (150) configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

The application relates to the field of integrated circuit technology and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, a parity data exchange unit, a shift unit and a selection output unit. The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end. The parity data exchange unit is connected between the parallel data storage unit and the shift unit and is used for directly outputting parallel data or outputting the parallel data after parity data bit exchange according to a first selection control signal. The shift unit is connected with the parity data exchange unit, the selection output unit and a serial clock signal end. The selection output unit is connected with the shift unit, a serial clock signal input end and a serial data output end and is used for sequentially and serially outputting each bit data in the shift data according to the high and low levels of the serial clock signal. The technical scheme can dynamically configure a specific parallel-serial conversion mode and improves the flexibility of I / O interface use of the FPGA.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

The invention discloses a self-adaptive AD interface device. Comprising an FPGA chip and an ADC chip. The FPGA chip is a PS + PL system architecture and comprises a PS end and a PL end; the PL end is configured to be used for configuring the ADC chip to enter a test code mode to start test code training, configuring the ADC chip to exit the test code mode after the test code training is completed, and performing serial-parallel conversion on data output by the ADC chip according to a training result; the PS end is configured to perform initialization operation on the ADC chip and send a training result of the test code training to the upper computer; the training result is displayed by the upper computer; the ADC chip is configured to perform analog-to-digital conversion on an input signal, perform parallel-serial conversion on a converted code value, and output the converted code value through the data lines D0 + / -and D1 + / -; or is configured in a test code mode in which a specific test code is output via the data lines D0 + / -, D1 + / -. According to the scheme, the time delay between ADC channels can be automatically compensated, and the adaptability of an interface to hardware difference is improved.

The application discloses a delay calibration method and device for multiple FPGAs. The method comprises the following steps: in response to a first delay calibration instruction sent by a host computer, a synchronization signal sent by a second FPGA is received; the second FPGA and the first FPGA are located on different circuit boards; a delay calibration process is performed on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and a first delay value is determined according to the calibrated signal and the synchronization signal; a first delay calibration success signal is sent to the host computer; the host computer forwards the first delay calibration success signal to the second FPGA; a first trigger signal sent by the second FPGA based on the first delay calibration success signal is received; and a delay calibration process is performed on the first trigger signal according to the first delay value to obtain a first calibrated trigger signal. The application realizes the synchronous detection of trigger signals of multiple FPGAs.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

A comparator circuit with a speed control element is disclosed herein. The speed control element may include a variable voltage source and one or more transistors. Using a voltage supplied by the variable voltage source, the one or more transistors may control a swing of a clock signal to provide a swing controlled clock signal to an amplification portion of the comparator circuit. The swing controlled clock therefor may be used to control the speed of the comparator circuit (e.g., an amplification phase) based on a level of noise in the circuit. The swing controlled clock may further be used to align an output common voltage of the comparator circuit with switching voltages of downstream logic cells (e.g., inverters) connected to the comparator circuit.

The invention belongs to the technical field of integrated circuits, and particularly relates to an 8: 1 high-speed parallel-to-serial circuit which comprises a pulse generation circuit unit, a buffer circuit unit, a data sampling circuit unit and a summing circuit unit. According to the circuit, an eight-phase clock is converted into eight paths of pulse signals with the duty ratio of 1 / 8 through a pulse generation circuit unit, sequential sampling of eight paths of parallel data in one clock period is achieved in cooperation with a pre-charging-sampling-resetting stage working mode, and the serial output rate is increased to be eight times of the input clock frequency; meanwhile, the summing circuit adopts gradual merging logic of selecting one from two and one from four, so that the problem of sharp increase of load capacitance of an output node caused by direct one from eight is avoided, the charging and discharging time of the circuit is greatly shortened, and the working speed of the circuit and the data transmission accuracy in a high-speed scene are improved. The problems that the performance of an existing circuit is limited due to load imbalance, and the maximum data rate of a parallel-to-serial circuit is limited by an input clock are solved.

This application relates to a decoder, a chip, a high-speed serial transmission interface, and an electronic device, belonging to the field of electronic technology. The decoder is used to decode N parallel input channels of first target data and N parallel input channels of second target data into parallel N-bit PRBS data output. The N channels of first target data are data obtained after serial-to-parallel conversion of first sampled data, and the N channels of second target data are data obtained after serial-to-parallel conversion of second sampled data. The first sampled data is data obtained by sampling encoded data using a first sampling threshold, and the second sampled data is data obtained by sampling encoded data using a second sampling threshold. N is an even number greater than or equal to 4. Because this decoder can be located after the serial-to-parallel conversion circuit, the high-frequency clock requirement of the decoder can be significantly reduced, thereby reducing the power consumption on the clock and increasing the upper limit of the decoder's operating speed.

This application relates to a parallel-to-serial conversion circuit and a control method for the parallel-to-serial conversion circuit. The circuit includes: a sampling sub-circuit, which receives 2 N The system consists of a set of parallel data and multiple first target clocks. The parallel data corresponds to a first target clock, and the multiple first target clocks have different phases. Based on the first target clock, the corresponding parallel data is sampled to obtain 2... N A set of sampled data; a parallel-to-serial conversion sub-circuit, which receives the sampled data and N second clock groups, performs N parallel-to-serial conversions based on the sampled data and the second clock groups to obtain a set of serial data. The m-th second clock group is the working clock group for the m-th parallel-to-serial conversion. The m-th second clock group includes 2 N‑m This circuit uses two second target clocks with different phases but the same frequency. The phase and frequency of the second target clocks in different second clock groups are all different. The circuit uses a clock with phase-shifting characteristics as the operating clock, eliminating the need for delay circuits and enabling the control of two... N Parallel-to-serial conversion of grouped parallel data.

The present disclosure provides a data sending circuit, a data receiving circuit, and an electronic device. The data sending circuit comprises a parallel-to-serial conversion circuit, a multi-level modulation circuit and a first transmission path; the parallel-to-serial conversion circuit is configured to convert a plurality of parallel initial data signals into serial data combinations, wherein each data combination comprises an n-bit data signal; the multi-level modulation circuit is configured to generate and output a target data signal on the basis of each data combination; and the first transmission path is coupled with the multi-level modulation circuit and is configured to transmit the target data signal to a second chip. According to the present disclosure, by means of multi-value transmission technology, a one-bit target data signal is used for the transmission of the n-bit data signal, so that the number of transmission paths can be reduced, and the transmission efficiency is improved.

The controller determines the period during which the media access control (MAC) layer circuit outputs data corresponding to an idle symbol, which is output by the MAC layer circuit for transmission over the communication link. In response to the stage of determining the period, at least a portion of the PHY circuitry transitions to a low-power mode during that period, and the PHY circuitry outputs a signal corresponding to an idle symbol, which is for transmission over the communication link.

The application discloses an eye diagram data synchronization circuit and method and a serial-parallel converter receiving end, and belongs to the technical field of high-speed serial data communication; the circuit comprises: a calibration signal generation module for generating a phase calibration signal according to a phase difference between a data sampling signal and an offset sampling signal; two registers for respectively outputting the offset sampling signal and pre / post offset sampling signals; wherein the pre / post offset sampling signals are obtained by outputting the offset sampling signal in advance / delaying half a bit period; and a selection output module for selecting the offset sampling signal or the pre / post offset sampling signals as a synchronized offset sampling signal output according to the phase calibration signal, so that the synchronized offset sampling signal and the data sampling signal are in the same bit period. The application has wide application range, high synchronization precision and good dynamic performance.

The invention discloses a wide-range high-speed data acquisition system. The system comprises a signal acquisition front end, a pre-amplifier, a filter network, an A / D conversion module, an FPGA, an ARM processor and a dual-port RAM. The ARM processor is used for writing sampling rate parameters and channel selection parameters, and the FPGA completes channel selection and sampling time sequence control based on the parameters and generates an A / D sampling clock through the clock module; the FPGA performs serial-parallel conversion on the serial conversion data output by the A / D and then writes the serial conversion data into the dual-port RAM, a ping-pong cache mechanism with at least two cache regions is adopted, an interruption notification is sent to the ARM processor when the dual-port RAM is full of the data, and the ARM processor reads the cache data to perform local storage or network transmission.

Systems and methods are provided for timing synchronization of serial data stream outputs of a plurality of serializers. The method involves providing a first serial data stream output of a first serializer of the plurality of serializers to an "AND" gate; selecting each serializer of the plurality of serializers other than the first serializer, to determine a timing offset for the serial data stream output of each selected serializer by providing the serial data stream output of the selected serializer to the "AND" gate, and then adjusting the timing offset for the serial data stream output of the selected serializer until an oversampling of a gate data stream output from the "AND" gate indicates a maximum timing alignment between the serial data stream output of the selected serializer and the first serial data stream output; and controlling the timing synchronization based on the determined timing offsets.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

Various techniques are provided to configure serializer / deserializer (SerDes) lanes in one or more SerDes quads into configurable groups using a bonded link. The configuration registers may configure the SerDes lanes into the configurable groups. A lane bonding control module in each SerDes quad may link the signals, including control signals, that travel within each configurable group. To synchronize the control signals, the lane bonding control module may include one or more flops that introduce a fixed time delay for control signals that travel between SerDes quads, and pipe stage match modules that introduce a variable time delay to match the fixed time delay caused by the flops. Once synchronized, the control signals arrive at different SerDes lanes in the configurable group at the same clock cycle.

Methods, apparatus, and systems are described to facilitate phase detection for data clock synchronization. An example phase detection circuit includes a first switch including a control terminal, the control terminal of the first switch coupled to a clock generator; a second switch including a control terminal, the control terminal of the second switch coupled to the clock generator; a first capacitor including a first terminal, the first terminal of the first capacitor coupled to a second terminal of the first switch; a second capacitor including a first terminal, the first terminal of the second capacitor coupled to a second terminal of the second switch; and a comparator including a first input terminal and a second input terminal, the first input terminal of the comparator coupled to the second terminal of the first switch, the second input terminal of the comparator coupled to the second terminal of the second switch.

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.