312results about "Parallel/series conversion" patented technology

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

A high-speed transmitter system is disclosed that uses a supply-controlled serialization stage embedded in a PMOS output stage. In some embodiments, the transmitter includes a serialization circuit configured to convert parallel data to serial data by one or more serialization stages, a logic circuit configured to connect each input of the last stage of the one or more serialization stages of the serialization circuit to a respective dedicated output stage of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal using PMOS transistors based on the received input. Also, the logic circuit is connected to a low-voltage power supply, whereby its output can be adjusted to be close to the switching point of a PMOS-based gm stage so as to accelerate the operation of the transmitter.

An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

Disclosed is a high-speed transmitter system that uses a serialization stage embedded in an output stage and controlled in a common mode. In some of the plurality of embodiments, the transmitter includes a serialization circuit configured to convert parallel data into serial data using one or more serialization stages, a logic circuit configured to connect each of the inputs of the final stage of one or more serialization stages of the serialization circuit to respective dedicated output stages of an output circuit via respective logic functions, and an output circuit configured to implement an output stage to generate a signal based on a received input using NMOS transistors. Additionally, the logic circuit is configured to achieve a desired voltage value (such as the common mode of the output circuit), thereby making it possible to reduce the switching point of the gm stage of the NMOS and activate the gm stage within the reduced time.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

A circuit and method for data recovery comprises clock generation, data reception, data oversampling, and data selection circuits; wherein, clock generation circuits are used to output data reception clock signals and data processing clock signals; data reception circuits are used to receive original transmission data from the data transmitter in accordance with the data reception clock signals, and transmit data based on its output; data oversampling circuits are used for multiple oversampling of at least one bit of transmission data corresponding to at least one data processing cycle according to the data processing clock signal and outputting corresponding parallel sample data; data selection circuits are used for transition detection on the corresponding parallel sample data for each data processing cycle and selecting sample data from the corresponding parallel sample data to output based on the transition detection results. The embodiments of the present application use a simple structure to implement data recovery, reducing layout area and circuit power consumption.

A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.

A data conversion apparatus includes a conversion module, a frequency divider module electrically connected to the conversion module, and a clock selection module electrically connected to both the conversion module and the frequency divider module. The frequency divider module is configured to divide an input clock signal to obtain an output clock signal according to a bit-width m of input data and a bit-width n of output data. The clock selection module is configured to transmit the input clock signal and the output clock signal to the conversion module as a write clock signal and a read clock signal, respectively. The conversion module is configured to: receive the input data of m-bit-width according to the wire clock signal; convert the input data into the output data of n-bit-width; and output the output data according to the read clock signal.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

The invention provides a data transmitting circuit, a data receiving circuit and electronic equipment, and the data transmitting circuit comprises a parallel-serial conversion module which is configured to convert a plurality of parallel initial data signals into a serial data combination; the data combination comprises n bits of data signals; a multi-level modulation circuit configured to generate and output a target data signal based on each data combination; and the first transmission path is coupled with the multi-level modulation circuit and is configured to transmit the target data signal to the second chip.

The invention discloses a high-frequency digital phase-locked amplifier based on a parallel digital algorithm and a control method. The amplifier comprises an analog-to-digital converter module, a serial-to-parallel module, an N parallel frequency measurement module, an N parallel phase-locked loop module and an N parallel input coherent demodulation module. The method comprises the following steps: acquiring an analog input signal and a reference signal, and sampling; performing serial-parallel conversion processing on the sampled digital input signal and the digital reference signal; performing frequency measurement on the N parallel digital reference signals to obtain reference signal frequency measurement information; performing phase locking adjustment on the N parallel digital reference signals to obtain frequency information and phase information; and performing demodulation processing on the N parallel digital input signals to obtain amplitude information, phase information and XY component information of the digital input signals. The embodiment of the invention can reduce the rate of the data flow and improve the throughput of the data information, thereby improving the bandwidth of the phase-locked amplification system. The invention can be widely applied to the technical field of phase-locked amplification.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

The invention relates to the technical field of conversion circuits, and provides a converter drift suppression front-end circuit and a drift suppression method, and the circuit comprises a first signal processing circuit and a second signal processing circuit which are symmetrically distributed, and a high-frequency path and a low-frequency path which are arranged between the first signal processing circuit and the second signal processing circuit; wherein a normal-phase input signal forms a first node signal after passing through the first signal processing circuit, and a reverse-phase input signal corresponding to the normal-phase input signal forms a second node signal after passing through the second signal processing circuit; the first node signal and the second node signal are respectively input into a normal-phase input end and an inverted-phase input end of a converter CTLE through the high-frequency path or the low-frequency path; and the low-frequency path comprises a fully differential amplifier with resistance proportion negative feedback. According to the invention, baseline drift can be effectively suppressed, so that the stability of converter receiving end signals is improved.

An integrated circuit memory device includes a serializer configured to convert a plurality of bits of parallel read data, which are synchronized with a corresponding plurality of clock signals that are out-of-phase relative to each other, into a serial stream of the read data. This conversion is performed using a Boolean logic circuit, which is configured to receive each of the plurality of bits of parallel read data and each of the plurality of out-of-phase clock signals at corresponding inputs thereof.

The invention provides a linear frequency modulation signal generation method and device based on multi-path parallel real-time calculation, and relates to the technical field of synthetic aperture radars. Comprising the following steps: determining an initial frequency control word and a frequency modulation slope control word according to a preset linear frequency modulation signal parameter; generating k parallel frequency control words based on the constructed virtual serial frequency control word, the initial frequency control word and the frequency modulation slope control word, wherein k is an integer greater than 1; respectively inputting the k paths of parallel frequency control words into k phase accumulators, and synchronously generating k paths of linear frequency modulation signals with continuous phases; and the k paths of signals are combined and output as broadband linear frequency modulation signals through a digital-to-analog converter. On the basis of arithmetic progression characteristics of virtual serial frequency control words, phase compensation terms of all parallel branches are eliminated, and phase continuity among multiple signals is guaranteed through synchronous recursion of multiple phase accumulators.

The invention provides a signal fast scanning and reading circuit system suitable for a touch sensor. The system comprises a 16 * 16 sensing capacitor array used for simulating pressure information; the 16 column parallel capacitance digital conversion channels are used for realizing conversion from capacitance signals to digital signals; the multiplexer module is used for controlling a capacitor to be connected to the capacitance digital conversion channel; the 4-16 decoders control switches of the multiplexers, so that the capacitors are gated column by column; and the time sequence control module is used for generating a working time sequence of the circuit. Meanwhile, each capacitance digital conversion channel comprises a capacitance voltage conversion circuit, so that conversion from a capacitance signal to a voltage signal is realized; the circulating analog-to-digital converter is used for converting the voltage into a digital signal; and the parallel-serial conversion interface circuit converts the parallel digital output of the analog-to-digital converter into serial digital output, so that the number of chip pins is reduced, and the integration level is improved. The invention has the advantages of high integration level and fast conversion speed.

The invention relates to a serial-to-parallel conversion circuit and MIPI C-PHY equipment, the serial-to-parallel conversion circuit comprises a first frequency division module, a second frequency division module and a serial-to-parallel conversion module, the first frequency division module is used for accessing a first clock signal, performing m-1 frequency division processing and m frequency division processing on the first clock signal and then outputting a second clock signal and a switching signal; the second frequency division module is used for accessing a first clock signal and performing n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; wherein n + 1 is equal to 2m, and n is a positive odd number; the serial-to-parallel conversion module is connected with the first frequency division module and the second frequency division module and is used for outputting the data signal as n paths of data under the control action of the access data signal, the first clock signal, the second clock signal, the switching signal and the synchronous clock signal; the transmission rate of the data signal is twice the frequency of the first clock signal.

A high-speed SerDes transmitter module, a programmable logic chip and a test method. The module comprises a parallel-serial conversion circuit, an output drive circuit, a three-state gate circuit and a swing measurement circuit; the parallel-serial conversion circuit is used for receiving parallel data, and carrying out parallel-serial conversion on the parallel data, so as to output a serial signal; the output drive circuit is used for receiving and outputting the serial signal; on the basis of an external control signal, the three-state gate circuit is used for controlling the state of an input end of the output drive circuit; the swing measurement circuit is controlled by the external control signal to measure an output swing of the output drive circuit. Using the solution of the present invention can rapidly measure the swings of high-speed SerDes transmitters, and effectively reduce the usage of ATE.

The invention discloses a high-frequency data transmission method and device and semiconductor testing equipment, and relates to the technical field of semiconductor testing, and the high-frequency data transmission method comprises the steps: obtaining a to-be-switched target transmission rate; therefore, on the basis of the target transmission rate, a frequency division number used for indicating the number of repetitions of each bit in the initial parallel data to be sent is determined; according to the embodiment of the invention, the frequency division number is determined according to the target transmission rate to be switched, the frequency division number is determined according to the target transmission rate to be switched, and then the initial parallel data is processed based on the frequency division number to obtain frequency division parallel data, and the frequency division parallel data is new parallel data obtained after each bit in the initial parallel data is repeated according to the frequency division number. And the initial parallel data is recoded through the frequency division number, so that the data transmission rate is influenced, the purpose of switching the transmission rate is achieved, and the non-delay switching of the target transmission rate is realized.

The invention discloses a calculation method and device for realizing Fourier transform by a parallel circuit. The method comprises the following steps: acquiring an input signal sequence of an input signal; based on a preset degree of parallelism, performing serial-parallel conversion on the input signal sequence by using a parallel circuit to obtain a signal transformation matrix; obtaining an original Fourier transform matrix according to the input signal sequence, and transforming the original Fourier transform matrix into a parallel Fourier transform matrix based on the degree of parallelism; and performing vector inner product operation on the row vectors of the parallel Fourier transformation matrix and the signal transformation matrix in sequence to obtain a Fourier transformation result of the input signal sequence. During calculation, it is not required that the length of an input signal sequence must be N power of 2 or 4, and it is not required that the input signal sequence must be uniformly sampled, but a Fourier transform result can be obtained by sequentially carrying out vector inner product operation on row vectors of the parallel Fourier transform matrix and the signal transform matrix, so that the calculation efficiency is improved, and the calculation cost is reduced. And the waste of computing resources is avoided.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

Transvascular diaphragm pacing systems (TDPS) and methods are disclosed for providing respiratory therapy to a patient. The TDPS can provide rapid insertion and deployment of endovascular pacing electrodes in critically ill patients who require intubation and invasive PPMV in order to support the physiological requirements of the human ventilatory system. The systems and methods make best use of the contractile properties of the diaphragm muscle and prevent muscle disuse and muscle atrophy. This can be carried out by engaging the phrenic nerves using patterned functional electrical stimulation applied to endovascular electrodes that are temporarily and reversibly inserted in central veins of the patient, such as the left subclavian vein and the superior vena cava. The TDPS can be designed to seamlessly interface with any commercially available positive-pressure ventilatory assistance / support equipment such as is commonly in use in hospital intensive care units (ICU) for treating critically ill patients with breathing insufficiencies, pain, trauma, sepsis or neurological diseases or deficits.

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

The embodiment of the invention discloses a data acquisition card and a data acquisition method. The data acquisition card comprises a plurality of analog-to-digital conversion modules; the clock module is in communication connection with each analog-to-digital conversion module; the field programmable gate array is in communication connection with each analog-to-digital conversion module and the clock module, and the field programmable gate array is used for generating a synchronizing signal and outputting the synchronizing signal; the synchronization module is in communication connection with each analog-to-digital conversion module, the clock module and the field programmable gate array, and the synchronization module is used for receiving a synchronization signal and transmitting the synchronization signal to each analog-to-digital conversion module and the field programmable gate array; wherein the analog-to-digital conversion modules are further used for determining the phase relation between the synchronizing signals and the clock signals according to the synchronizing signals and the clock signals, and the field programmable gate array is further used for determining the time when the synchronizing signals reach the analog-to-digital conversion modules according to the phase relation. According to the data acquisition card and the data acquisition method provided by the embodiment of the invention, data acquisition synchronization can be realized.

The invention discloses a low-power-consumption column parallel monoclinic ADC (Analog to Digital Converter) circuit adopting a floating comparator circuit, a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) image sensor reading circuit and a CMOS image sensor. The low-power-consumption column parallel monoclinic ADC circuit adopting the floating comparator circuit comprises a floating comparator, an M-bit calculator, an M-bit latch and a parallel-serial conversion circuit which are connected in sequence, and the floating comparator is provided with a pixel signal input end and a ramp signal input end and is connected with a ramp generator through the ramp signal input end. According to the low-power-consumption column parallel monoclinic ADC circuit of the floating comparator circuit, the topological structure of a traditional floating comparator is improved, and an input overturning point of the comparator is kept on a set level; in the comparison stage of the monoclinic ADC, the voltage reduction amplitude of the floating capacitor is reduced, and it is ensured that the comparator is in a normal working state in the whole comparison stage.

A semiconductor device (10, 20) includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.