230results about "Parallel/series conversion" patented technology

A transmitter in an interface circuit includes a first retimer circuit configured to serialize data by interleaving even bits of the data and odd bits of the data into a first bitstream, a second retimer circuit configured to serialize the data by interleaving even bits of the data and inverted versions of the odd bits of the data into a second bitstream, and line driver circuits configured to transmit the first bitstream over a communication link.

A high-speed transmitter system using a common mode controlled serialization stage embedded in an output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using NMOS transistors. In addition, the logic circuit is configured to be a desired voltage value (e.g., the output circuit's common mode) such that a switching point of the NMOS gm stage can be decreased and the gm stage can be activated within a reduced time.

An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.

A high-speed transmitter system using a supply controlled serialization stage embedded in a PMOS output stage is disclosed. In some embodiments, the transmitter includes a serialization circuit that is configured to convert parallel data into serial data with one or more serialization stages; a logic circuit that is configured to connect each input of a last stage of the one or more serialization stages of the serialization circuit, via a respective logic function, to a respective dedicated output stage of an output circuit; and the output circuit that is configured to implement output stages to generate a signal based on the received input using PMOS transistors. In addition, the logic circuit is connected to a low voltage supply such that its output can be adjusted to be close to a switching point of the PMOS based gm stage to speed up transmitter operations.

A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.

The invention relates to a SERDES channel control binding system and method. Various techniques are provided to configure serializer / deserializer (SerDes) channels in one or more SerDes tetrads into a configurable group using a bound link. A configuration register may configure the SerDes channels into a configurable group. A channel binding control module in each SerDes tetrad may link signals, including control signals, that travel within each configurable group. In order to synchronize the control signals, the channel binding control module may include: one or more flip-flops that introduce a fixed time delay for the control signals traveling between SerDes tetrads; and the tube level matching module introduces variable time delay to match the fixed time delay caused by the trigger. Once synchronized, the control signal reaches different SerDes channels in the configurable group at the same clock cycle.

A method for generating soft information for a digital signal decoder. The method includes receiving a first plurality of signals, each corresponding to a time index, each time index being associated with two states including state 1 and state 0. The method also includes processing the first plurality of signals to calculate path metric values of state 0 and 1 for generating each of a second plurality of most-likely symbols by hard decisions and intermediate information for a most-likely path and a second-likely path at each time index. The method includes computing a difference between the most-likely path and a second-likely path for a given one of the two states at each time index. The method also includes determining a soft information corresponding to either one of the two states at the time index per one of the second plurality of most-likely symbols.

The invention relates to the technical field of conversion circuits, and provides a converter drift suppression front-end circuit and a drift suppression method, and the circuit comprises a first signal processing circuit and a second signal processing circuit which are symmetrically distributed, and a high-frequency path and a low-frequency path which are arranged between the first signal processing circuit and the second signal processing circuit; wherein a normal-phase input signal forms a first node signal after passing through the first signal processing circuit, and a reverse-phase input signal corresponding to the normal-phase input signal forms a second node signal after passing through the second signal processing circuit; the first node signal and the second node signal are respectively input into a normal-phase input end and an inverted-phase input end of a converter CTLE through the high-frequency path or the low-frequency path; and the low-frequency path comprises a fully differential amplifier with resistance proportion negative feedback. According to the invention, baseline drift can be effectively suppressed, so that the stability of converter receiving end signals is improved.

The invention provides a signal fast scanning and reading circuit system suitable for a touch sensor. The system comprises a 16 * 16 sensing capacitor array used for simulating pressure information; the 16 column parallel capacitance digital conversion channels are used for realizing conversion from capacitance signals to digital signals; the multiplexer module is used for controlling a capacitor to be connected to the capacitance digital conversion channel; the 4-16 decoders control switches of the multiplexers, so that the capacitors are gated column by column; and the time sequence control module is used for generating a working time sequence of the circuit. Meanwhile, each capacitance digital conversion channel comprises a capacitance voltage conversion circuit, so that conversion from a capacitance signal to a voltage signal is realized; the circulating analog-to-digital converter is used for converting the voltage into a digital signal; and the parallel-serial conversion interface circuit converts the parallel digital output of the analog-to-digital converter into serial digital output, so that the number of chip pins is reduced, and the integration level is improved. The invention has the advantages of high integration level and fast conversion speed.

The invention relates to the technical field of integrated circuits, and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, an odd-even data exchange unit, a shifting unit and a selection output unit, the parallel data storage unit is connected with a parallel data input end and a parallel clock signal end, and the odd-even data exchange unit is connected between the parallel data storage unit and the shifting unit. The data output module is used for directly outputting parallel data or performing odd-even data bit exchange on the parallel data according to a first selection control signal and then outputting the parallel data; the shifting unit is connected with the odd-even data exchange unit, the selection output unit and a serial clock signal end; and the selection output unit is connected with the shift unit, the serial clock signal input end and the serial data output end, and is used for sequentially and serially outputting each bit of data in the shift data along with the high and low levels of the serial clock signal. According to the technical scheme, the specific parallel-serial conversion mode can be dynamically configured, and the use flexibility of the I / O interface of the FPGA is improved.

Transvascular diaphragm pacing systems (TDPS) and methods are disclosed for providing respiratory therapy to a patient. The TDPS can provide rapid insertion and deployment of endovascular pacing electrodes in critically ill patients who require intubation and invasive PPMV in order to support the physiological requirements of the human ventilatory system. The systems and methods make best use of the contractile properties of the diaphragm muscle and prevent muscle disuse and muscle atrophy. This can be carried out by engaging the phrenic nerves using patterned functional electrical stimulation applied to endovascular electrodes that are temporarily and reversibly inserted in central veins of the patient, such as the left subclavian vein and the superior vena cava. The TDPS can be designed to seamlessly interface with any commercially available positive-pressure ventilatory assistance / support equipment such as is commonly in use in hospital intensive care units (ICU) for treating critically ill patients with breathing insufficiencies, pain, trauma, sepsis or neurological diseases or deficits.

The application discloses a kind of synchronization methods of multi-channel high-speed digital-analog conversion module, comprising: reference clock source generates reference clock;Trigger controller generates trigger signal, trigger signal is used to inform each DAC board to start the digital quantity transmission of new waveform;Master chip PLL is multiplied to preset operating frequency by reference clock, and the feedback path of master chip PLL is removed to DAC board, and the delay of voltage-controlled oscillator output master chip IO's wiring is consistent and position is close;DAC PLL is multiplied to the sampling clock frequency of DAC by reference clock, and the output phase of DAC PLL can be adjusted, to ensure the timing margin when DAC reads digital quantity;Master chip is triggered under trigger signal, and at preset time, the digital quantity of several waveforms to be converted is sent to DAC by isochronous transmission path, and DAC converts digital quantity into analog waveform, realizes that all DAC completes digital quantity to analog quantity conversion at the same time, and realizes the high-precision synchronous conversion of DAC.

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

A serializer circuit includes flipflops and a multiplexing circuit. A first flipflop may be configured to capture a bit of data from a first data signal during each cycle of a clock signal. A second flipflop may be configured to capture a bit of data from a second data signal during each cycle of the clock signal. The multiplexing circuit may be configured to provide an output of the first flipflop as an output of the multiplexing circuit when a delayed version of the clock signal is in a first signaling state, and to provide an output of the second flipflop as the output of the multiplexing circuit when the delayed version of the clock signal is in a second signaling state. The delayed version of the clock signal may be configured to suppress data-dependent glitches in an output signal used in subsequent stages of a receiving device.

The embodiment of the invention discloses a data acquisition card and a data acquisition method. The data acquisition card comprises a plurality of analog-to-digital conversion modules; the clock module is in communication connection with each analog-to-digital conversion module; the field programmable gate array is in communication connection with each analog-to-digital conversion module and the clock module, and the field programmable gate array is used for generating a synchronizing signal and outputting the synchronizing signal; the synchronization module is in communication connection with each analog-to-digital conversion module, the clock module and the field programmable gate array, and the synchronization module is used for receiving a synchronization signal and transmitting the synchronization signal to each analog-to-digital conversion module and the field programmable gate array; wherein the analog-to-digital conversion modules are further used for determining the phase relation between the synchronizing signals and the clock signals according to the synchronizing signals and the clock signals, and the field programmable gate array is further used for determining the time when the synchronizing signals reach the analog-to-digital conversion modules according to the phase relation. According to the data acquisition card and the data acquisition method provided by the embodiment of the invention, data acquisition synchronization can be realized.

The invention discloses a trigger signal acquisition circuit, an ADC sampling device and a sampling method. The trigger signal acquisition circuit comprises a comparison module, a buffer module, a data acquisition module and a clock module, the clock module outputs N paths of clock signals, and the phases and the frequencies of the N paths of clock signals are the same; the comparison module accesses a first trigger signal and a trigger threshold, and outputs a second trigger signal according to the first trigger signal and the trigger threshold; the buffer module copies according to the second trigger signals and outputs N paths of second trigger signals, the data acquisition module acquires third trigger signals according to the clock signal and converts and outputs fourth trigger signals, the number of the third trigger signals is N, and when N is larger than 2, the fourth trigger signals are output. The time differences of two paths of third trigger signals at adjacent moments in the N paths of third trigger signals are equal. The trigger signal acquisition circuit provided by the invention can realize high-precision extraction of the trigger signal.

A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a control logic configured to generate a control signal based at least in part on the second clock signal; and two or more analog-to-digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, where the multiplexer is configured to select a set of the second number of inputs to be output, where the selected set of the second number of inputs is based at least in part on the control signal. The apparatus includes one or more unit ADCs, wherein respective outputs of the one or more unit ADCs are coupled as inputs to the multiplexer.

A transmitter circuit (1) that receives parallel signals (D(1:4)) and outputs a serial signal (D_Tx) in response to the parallel signals may include; a clock generator (20) generating first clock signals (CK(1:4)) having different respective phases, a multiplexer (10) including selection circuits (11, 12, 13, 14) respectively configured to selectively provide at least two of the parallel signals (D1, D2 or D2, d3 or D3, D4 or D4, D1) to an output node in response to at least two of the first clock signals (Ck1, Ck2 or Ck2, Ck3 or Ck3, Ck4 or Ck4, Ck1), and an output driver (15) generating the serial signal (D_Tx) by amplifying a signal at the output node.

A system includes a deserializer having a data input, a clock input, and parallel outputs, wherein the deserializer is configured to receive a serial data stream at the data input, convert the serial data stream into parallel data, and output the parallel data at the parallel outputs. The system also includes an edge swallower or a pulse swallower coupled to the clock input of the deserializer.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.

Embodiments of the disclosure relate to the technical field of semiconductors, and disclose an interface circuit, a data transmission circuit and a memory. The interface circuit includes a clock pad (102), data pads (101) and input buffer circuits (103), where the clock pad (102) and the data pads (101) are arranged in the first row, and the M data pads (101) are arranged on two sides of the clock pad (102), half of the M data pads (101) being arranged on each side, where the M input buffer circuits (103) are arranged in the second row and form an axis (AA1) perpendicular to the first row with the data pads (102) as reference, and the M input buffer circuits (103) are arranged on two sides of the axis (AA1), half of the M input buffer circuits (103) being arranged on each side, and where the distance between each input buffer circuit (103) and the axis (AA1) is smaller than the distance between the data pad (101) corresponding to the input buffer circuit (103) and the axis AA1.

It is provided an improved integrated circuit (10) is provided for driving fast links in radiation-hard applications comprising a PISO device (1) including a transmitting block (2) defining a first basic logic and configured to transmit first data in parallel (1p) correlated to a first low frequency clock signal (1l), a PLL (3) configured to receive a first reference clock signal (1r) and to generate at least a first high frequency clock signal (1a) and in including at least a first FD (30) configured to generate at least a first control clock signal (1c), a Serializer (4) operatively connected to the PLL (3) and the transmitting block (2) and configured to receive at least the first data in parallel (1p) and the first high frequency clock signal (1a) and reorganize the first data in parallel (1p) on the basis of a first load signal (4c) in first serial data (1s) related in frequency to the first high clock signal frequency (1a), in which the first PD (30) is operatively connected to the transmitting block (2), the first low frequency clock signal (1l) coincides with the first control clock signal (1c) and the transmitting block (2) transmits the first low frequency clock signal (1l) to the Serializer (4) so as to determine the first load signal (4c) in proportion to the first low frequency clock signal (1l); and a SIPO device (5) including a receiving block (6) defining a second basic logic and configured to receive second data (5p) correlated to a second low frequency clock signal (5l), CDR apparatus (7) configured to receive second serial data (5s), to generate at least a second high frequency clock signal (5a) and in including at least a second FD (70) configured to generate at least a second control clock signal (5c), a Deserializer (8) operatively connected to the CDR apparatus (7) and to the receiving block (6) and configured to receive at least the second serial data (5s) and the second high frequency clock signal (5a) and reorganize the second data (5s) on the basis of a second load signal (8c) in the second parallel data (5p) correlated in frequency to the second high frequency clock signal (5a), wherein the second PD (70) is operationally connected to the receiving block (6), the second low frequency clock signal frequency (5l) coincides with the second control clock signal (5c) and the receiving block (6) transmits the second low frequency clock signal (5l) to the Deserializer (8) in order to determine the second load signal (8c) proportionally to the second low frequency clock signal (5l); and wherein the Serializer (4) is operatively connected to the Deserializer (8) and to the CDR apparatus (7), the first serial data (1s) coincide with the second serial data (5s), the first parallel data (1p) they are equivalent to the second parallel data (5p), the first high frequency signals (1a) are equivalent to the second high frequency signals (5a) and the first low frequency signals (1l) are equivalent to the second low frequency signals (5l).

The application discloses a data sorting system and method. In the application, the data sorting system comprises an ADC chip, a sorting multiplexing module and a sorting control module. When the current state is a test mode, the ADC chip is used to transmit data clock and LVDS data to the sorting multiplexing module, then the sorting multiplexing module is used to generate parallel output data according to the data clock and the LVDS data, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. When the current state is the test mode, the ADC chip is used to transmit the data clock and the LVDS data to the sorting multiplexing module, and then the sorting control module is used to respectively perform data sorting processing on each channel data in the parallel output data. The delay condition of the parallel output data can be processed by the sorting control module, so that the calibration between the data and the clock can be realized, and the LVDS data can be accurately sorted.

An apparatus (100) for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit (130) receiving an input signal from a signal path mixed with interference from a clock path. The apparatus (100) includes a phase interpolator circuit (120) implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit (140) to sample the input signal and the interference in every cycle. The apparatus (100) also includes an analog-to-digital converter (150) configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

A multi-channel synchronous acquisition and transmission system based on the JESD204B protocol includes a multi-channel AD synchronous acquisition module, a signal source module, a power module and an upper computer module, wherein the signal source module sends a reference clock and multiple analog signals to the multi-channel AD synchronous acquisition module; the multi-channel AD synchronous acquisition module includes an FPGA, a multi-channel ADC, an independent clock source and multiple devices; the independent clock source receives the reference clock and transmits a sysref signal; a time window is configured in the multi-channel ADC; the FPGA generates a sync signal and synthesizes an LMFC, and an edge of the sysref signal is taken as an edge of the LMFC; in the multi-channel ADC, a corresponding ILAS is set for each digital signal; and the FPGA receives all the ILASs and digital signals, and multiple digital signals are processed synchronously.

The application relates to the field of integrated circuit technology and discloses a parallel-serial conversion circuit. The parallel-serial conversion circuit comprises a parallel data storage unit, a parity data exchange unit, a shift unit and a selection output unit. The parallel data storage unit is connected with a parallel data input end and a parallel clock signal end. The parity data exchange unit is connected between the parallel data storage unit and the shift unit and is used for directly outputting parallel data or outputting the parallel data after parity data bit exchange according to a first selection control signal. The shift unit is connected with the parity data exchange unit, the selection output unit and a serial clock signal end. The selection output unit is connected with the shift unit, a serial clock signal input end and a serial data output end and is used for sequentially and serially outputting each bit data in the shift data according to the high and low levels of the serial clock signal. The technical scheme can dynamically configure a specific parallel-serial conversion mode and improves the flexibility of I / O interface use of the FPGA.

Clock recovery from a serial data signal involves using a serializer / deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

The invention discloses a self-adaptive AD interface device. Comprising an FPGA chip and an ADC chip. The FPGA chip is a PS + PL system architecture and comprises a PS end and a PL end; the PL end is configured to be used for configuring the ADC chip to enter a test code mode to start test code training, configuring the ADC chip to exit the test code mode after the test code training is completed, and performing serial-parallel conversion on data output by the ADC chip according to a training result; the PS end is configured to perform initialization operation on the ADC chip and send a training result of the test code training to the upper computer; the training result is displayed by the upper computer; the ADC chip is configured to perform analog-to-digital conversion on an input signal, perform parallel-serial conversion on a converted code value, and output the converted code value through the data lines D0 + / -and D1 + / -; or is configured in a test code mode in which a specific test code is output via the data lines D0 + / -, D1 + / -. According to the scheme, the time delay between ADC channels can be automatically compensated, and the adaptability of an interface to hardware difference is improved.

The application discloses a delay calibration method and device for multiple FPGAs. The method comprises the following steps: in response to a first delay calibration instruction sent by a host computer, a synchronization signal sent by a second FPGA is received; the second FPGA and the first FPGA are located on different circuit boards; a delay calibration process is performed on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and a first delay value is determined according to the calibrated signal and the synchronization signal; a first delay calibration success signal is sent to the host computer; the host computer forwards the first delay calibration success signal to the second FPGA; a first trigger signal sent by the second FPGA based on the first delay calibration success signal is received; and a delay calibration process is performed on the first trigger signal according to the first delay value to obtain a first calibrated trigger signal. The application realizes the synchronous detection of trigger signals of multiple FPGAs.