2results about "Computations using pulse rate multipliers/dividers" patented technology

The invention relates to a floating-point number in-memory calculation method and system based on time domain index processing, and a medium. The floating-point number in-memory calculation method based on time domain index processing comprises the steps that the weight part of the data type of an FP8 is converted into the type of an FP9 to be processed, input indexes and weight indexes are converted into pulse widths to be combined to solve the index sum, and then the number of pulse edges contained under the indexes and the pulse widths is calculated according to the number of the pulse edges contained under the pulse widths to obtain the floating-point number in-memory calculation. And synchronously completing mantissa shift control as a control signal, and synchronously starting subsequent operation by utilizing a maximum delay signal so as to adaptively control a calculation period. The bit widths of the weight index and the input index which need to be operated can be reduced by one bit, the bit width of the weight mantissa is increased by one bit, meanwhile, an index processing module in a digital domain in the prior art is omitted, mantissa shifting is synchronously controlled by utilizing a time domain processing index part, and the operation efficiency is improved. Therefore, the bottleneck problems of multiple cycles and high hardware cost caused by the fact that calculation in the floating-point number memory depends on a digital device are obviously reduced.

An electric vehicle motor rotational speed value generating device comprises: a first counter counting an input frequency according to a system frequency and outputs a first bit numerical value; a second counter receiving the first bit numerical value, the second counter counts the first bit numerical value with an exponent n in a 2n exponential function that approximates a maximum rotational speed command value and outputs a second bit numerical value; a frequency divider receiving the second bit numerical value, and the frequency divider divides the second bit numerical value from the system frequency and outputs a counting frequency; and a third counter receiving the counting frequency, and the third counter is electrically connected to a maximum frequency generator and receives a maximum frequency generated by the maximum frequency generator, and the third counter counts the maximum frequency from the counting frequency and outputs a feedback rotational speed value.