2170 results about "Frequency synthesizer" patented technology

A novel mechanism for simultaneous multiple signal reception and transmission using frequency multiplexing and shared processing. Multiple RF signals, which may be of various wireless standards, are received using one or more shared processing blocks thereby significantly reducing chip space and power requirements. Shared components include local oscillators, analog to digital converters, digital RX processing and digital baseband processing. In operation, multiple RX front end circuits, one for each desired wireless signal, generate a plurality of IF signals that are frequency multiplexed and combined to create a single combined IF signal. The combined IF signal is processed by a shared processing block. Digital baseband processing is performed on each receive signal to generate respective data outputs. Further, simultaneous full-duplex transmission and reception is performed using a single local oscillator. The phase / frequency modulation of the frequency synthesizer used in the TX is removed from the local oscillator signal for use in the receiver.

Circuits of a TAF-DPS clock generator implemented on programmable logic chip comprise: 1) a base time unit generator created from configurable blocks, or on-chip PLL, or on-chip DLL, said base time unit generator produces a plurality of phase-evenly-spaced-signals; 2) a TAF-DPS frequency synthesizer created by configuring configurable blocks of said programmable logic chip, said TAF-DPS frequency synthesizer takes said plurality of phase-evenly-spaced-signals as its input. Methods of creating flexible clock signal to drive application comprise: 1) selecting one or more strategic areas in said programmable logic chip; 2) creating one or more TAF-DPS clock generator for each said area by using the configurable resource in said area; 3) creating control function to control the frequency and duty-cycle of the TAF-DPS clock generator output, said control function can be circuit created from configuring configurable blocks, said control function can also be achieved by software; 4) driving the circuits in application by the flexible clock generated from said TAF-DPS clock generator.

Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a compensated microelectromechanical oscillator, having a microelectromechanical resonator that generates an output signal and frequency adjustment circuitry, coupled to the microelectromechanical resonator to receive the output signal of the microelectromechanical resonator and, in response to a set of values, to generate an output signal having second frequency. In one embodiment, the values may be determined using the frequency of the output signal of the microelectromechanical resonator, which depends on the operating temperature of the microelectromechanical resonator and / or manufacturing variations of the microelectromechanical resonator. In one embodiment, the frequency adjustment circuitry may include frequency multiplier circuitry, for example, PLLs, DLLs, digital / frequency synthesizers and / or FLLs, as well as any combinations and permutations thereof. The frequency adjustment circuitry, in addition or in lieu thereof, may include frequency divider circuitry, for example, DLLS, digital / frequency synthesizers (for example, DDS) and / or FLLs, as well as any combinations and permutations thereof.

In an implantable medical device, a frequency synthesizer employed in the RF transceiver of the IMD operating system functions in a PLL LOCK mode wherein the VCO frequency is governed by the PLL and an energy saving HOLD mode wherein the PLL is not operational and the VCO generated carrier frequency can drift over time. The PLL circuit is powered up and coupled with a control voltage input and the output of the VCO to develop a frequency control voltage stored by a capacitive loop filter during initial LOCK portions of both uplink and downlink telemetry transmission time periods. A frequency modulation (FM) input of the VCO receives data bit modulation voltages that modulates the carrier frequency during uplink transmission of patient data. During the HOLD portion of a downlink telemetry transmission, an AFC algorithm is enabled and derives a frequency correction value from the difference in frequency of the constant received carrier frequency and the drifting VCO generated carrier frequency, and the frequency correction value is applied to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. The AFC algorithm derived frequency correction value is stored in memory and is also applied during the HOLD portion of an uplink telemetry transmission to the VCO FM input to compensate for loop filter capacitor discharge of the control voltage causing the drift. In addition, a recharge current is applied to the capacitive loop filter.

A frequency synthesizer is disclosed. The frequency synthesizer comprises a fixed frequency generator configured to generate a fixed frequency signal, a variable frequency generator configured to generate a variable frequency signal, wherein the fixed frequency signal and the variable frequency signal are combined to provide a fast-hopping output signal.

A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up / down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

An image processing device includes: a frequency divider for performing a frequency division processing of dividing an input image into a plurality of frequency components each having a frequency band; a noise remover for performing a noise component removal processing of removing a noise component from a high frequency component in the frequency components each having the frequency band obtained by the frequency division processing by the frequency divider; an edge preservation information calculator for detecting an edge intensity based on a low frequency component in the frequency components each having the frequency band obtained by the frequency division processing by the frequency divider, and calculating edge preservation information relating to a degree of preserving an edge component based on the detected edge intensity; an edge preserving section for preserving the edge component in the high frequency component, based on the edge preservation information calculated by the edge preservation information calculator; and a frequency synthesizer for synthesizing the high frequency component whose noise component is removed by the noise remover and whose edge component is preserved by the edge preserving section, and the low frequency component, in each of the frequency bands.

The invention discloses a vehicle-mounted millimeter-wave radar moving target recognizer. The vehicle-mounted millimeter-wave radar moving target recognizer is characterized in that the recognizer is a frequency synthesizer; a frequency agility continuous signal is modulated into a pulse signal and then is processed into a millimeter-wave signal by up-conversion; after being amplified by a power amplifier, the millimeter-wave signal is transmitted out; an antenna receives a radar echo signal back to a circulator and then the signal is transmitted into a frequency mixer; a high-frequency echo pulse and constant-amplitude high-frequency voltage generated by a high-stability local oscillator are mixed and the signal is reduced to a middle frequency and then is processed by a middle-frequency amplifier; the middle-frequency signal is directly sampled by an A / D (Analogue / Digital) conversion module; after being sampled, echo signals of a whole pulse string are stored into a storage unit; and information of targets, such as quantity, speed and direction, is measured by a signal processing unit and then is transmitted to an alarm executing unit. With the adoption of the structure, the vehicle-mounted millimeter-wave radar moving target recognizer has the advantages that 1 the distance measuring precision and the angle measuring precision of a moving target are improved; and 2 excessive hardware does not need to be added and the production cost is lower.

A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.

A phase-locked loop frequency synthesizer has a charge pump, phase-locked loop filter, voltage-controlled oscillator, and a bandwidth calibration circuit. The bandwidth calibration circuit measures the gain of the voltage-controlled oscillator and uses the measured voltage-controlled oscillator gain to adjust the charge pump level. The charge pump level is adjusted so that a product of the voltage-controlled oscillator gain and the measured charge pump level results in a constant phase-locked loop bandwidth.

A low noise multi-loop radio frequency synthesizer is disclosed for the read channel in a hard disk drive, and for RF wireless communications local oscillator applications. The frequency synthesizer receives an input reference signal having a frequency fR, into a fine tune phase locked loop and into a coarse tune phase locked loop. Driven by the input reference signal, the fine tune PLL outputs a fine tune signal with a frequency fR.P, where P is an integer, while the coarse tune PLL, also driven by the same input reference signal, outputs a coarse tune signal with a frequency fR.A, where A is an integer. A translation phase locked loop has a unity multiplication factor and is driven by the fine tune signal output. The frequency synthesizer finally has a Gilbert cell double balanced mixer coupled between the coarse tune and the translation phase locked loops, wherein the Gilbert cell mixer combines the coarse tune signal and the output signal of the translation phase locked loop and couples the mixed signal into the translation phase locked loop. The translation loop outputs a signal with a frequency which is proportional to the linear sum of the coarse tune signal and the fine tune signal.

A system for synchronizing a second receive chain relative to a first receive chain in a multi-mode communication system. The system includes a first circuit that measures a first frequency associated with the first receive chain. A second circuit adjusts a second frequency associated with the second receive chain based on the first frequency and provides a desired second frequency to the second receive chain in response thereto. In a specific embodiment, the first circuit includes a first counter that receives a signal associated with an output of a first oscillator and provides a measurement of the first frequency in response thereto. The second circuit includes a frequency synthesizer for providing the desired second frequency in response to a frequency control or reference signal. Another circuit generates the control or reference signal based on a difference between the second frequency and the first frequency. A second counter receives a signal characterized by the second frequency and provides the second frequency in response thereto.

Apparatus for Doppler correction in a wireless communications system, including a first frequency synthesizer for generating a carrier signal oscillating at a rate responsive to a first input, a counter coupled to the first input for generating a Doppler compensation signal, the counter having a clock input, and a second frequency synthesizer coupled to the clock input for generating a clock signal oscillating at a rate responsive to a rate input. The rate input is adjusted over time according to a predetermined sequence so that the Doppler compensation signal compensates for the Doppler effect experienced by, for example, ground-to-satellite communications in a satellite communications system.

A lightweight millimeter wave outdoor unit includes a lightweight housing with a heat sink and mounting member configured for mounting on the antenna to form a wireless link. A millimeter wave transceiver board is formed of ceramic material and mounted within the housing. It includes a millimeter wave transceiver circuit that has microwave monolithic integrated circuit (MMIC) chips and operable with the transmit and receive boards. An intermediate frequency (IF) board has components forming an intermediate frequency circuit operable with the millimeter wave transceiver circuit. A frequency synthesizer board has a signal generating circuit for generating local oscillator signals to the transceiver circuit. A controller board has surface mounted DC and low frequency discrete devices thereon forming power and control circuits that supply respective power and control signals to other circuits on other boards. A quick connect / disconnect assembly is operative with the housing for allowing the housing to be rapidly connected and disconnected to the antenna circuit contact members interconnect circuits between boards.

A television tuner (920) is adapted for use in a television receiver (900) that receives a radio frequency (RF) signal from an input device (910) and outputs audio and video information from a selected channel in response thereto. The television tuner (920) includes a direct digital frequency synthesizer (206) and a mixer (220). The direct digital frequency synthesizer (206) has an output for providing a digital representation of a mixing signal. The mixer (220) has a signal input for receiving a television signal, a mixing input coupled to the output of said direct digital frequency synthesizer (206), and an output for providing an intermediate frequency (IF) television signal.

A frequency synthesizer and an automatic calibration device are disclosed. An automatic calibration device for a phase-locked loop based frequency synthesizer includes: a frequency-to-digital converter for converting a frequency of a signal outputted from a voltage controlled oscillator into a first digital value; a frequency difference detector for calculating a difference between the first digital value outputted from the frequency-to-digital converter and a second digital value corresponding to a target frequency; an automatic frequency calibration logic for selecting an optimal control code for a capacitor bank such that an output frequency of the voltage controlled oscillator is closer to the target frequency; and a loop bandwidth calibration logic for tuning a charge pump gain such that a loop bandwidth is kept constant in the optimal control code using the frequency-to-digital converter. Thus, the calibration speed can be increased, and the loop bandwidth can be kept constant within the output frequency range.

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

Techniques for direct modulation of a voltage-controlled oscillator (VCO) with adaptive digital gain control for wideband wireless applications are disclosed. A digital adaptive gain control loop is used to directly modulate the VCO, and a phase-locked loop (PLL) to track the frequency drift and other nonlinear effects of the VCO. As the PLL is applied to track the carrier frequency without passing the modulation signal into the PLL loop filter, the PLL can be implemented with a narrow loop bandwidth. The wideband frequency modulated signal is directly up-converted to the radio frequency (RF) signal by directly modulating the VCO through a digital-to-analog converter which is digitally controlled by an adaptive gain control loop. Thus, both wide bandwidth and low output noise for a frequency synthesizer and modulator can be achieved.

An x-ray diagnostic apparatus and methods performs Real-Time Digital Radiography with particular application in dental x-ray imaging modalities, such as Orthopantomography, Scannography, Linear Tomography and Cephalography, by using a versatile and modular electronic unit, featuring ultra fast computation capability to serve diversified image sensor typology and scanning modality.In Digital Orthopantomography and Scannography, a plurality of tomographic images at different depths of the jaw can be generated, based on the pre-selection made by the user interface.The image processing unit utilizes for the tomo-synthesis of the diagnostic image an accurate and economic digital simulator of the radiographic film speed, including a digital frequency synthesizer fed with film cassette speed digital input and high resolution clock signal, ensuring accurate and reproducible phase continuity of the output frequency signal.It also introduces an automatic adaptation of the frame acquisition rate in frame transfer mode, based on the actual speed of the cassette unit. By this method the dynamic of the exposure signal is reduced, and a better optimization of the signal response of the x-ray detector is achieved.

The invention discloses a frequency adjustment method of oscillator and a decimal frequency dividing phase-locked loop frequency synthesizer which comprises a digital frequency range rough adjusting mechanism and a simulate frequency fine adjusting mechanism. A binary search method is used in the process of digital frequency range rough adjusting, which gradually enhances the frequency comparative accuracy when reducing the adjusting step length, thus accelerating the self-alignment.

Systems and methods are described for hybrid spread spectrum radio systems. A method includes modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control an amplification circuit that provides a gain to the signal. Another method includes: modulating a signal by utilizing a subset of bits from a pseudo-random code generator to control a fast hopping frequency synthesizer; and fast frequency hopping the signal with the fast hopping frequency synthesizer, wherein multiple frequency hops occur within a single data-bit time.

The invention relates to a digital signal processing method and a device for a micro-mechanical gyroscope. The device mainly comprises a digital signal processor, a direct digital frequency synthesizer, a digital phase-locked loop and an analog-to-digital converter. The frequency synthesizer is used for outputting a sine drive signal with controllable frequency and amplitude. A drive feedback signal and an angular velocity readout signal are synchronously converted by the analog-to-digital converter; the converted frequency is an integral multiple of the frequency of the drive signal, and thesampling time length is an integral multiple of the period of the drive signal. With the adoption of the digital signal processor, the sampling data is multiplied by the fixed sine and cosine coefficients, and the input angular velocity and the orthotropic error as well as the phase and the amplitude of the drive feedback signal are resolved in an accumulative manner, and the phase parameters areutilized for adjusting the frequency of the drive signal, so that the frequency of the drive signal follows up the resonance frequency of the gyroscope. The amplitude parameters are utilized for adjusting the amplitude of the drive signal, so that the vibration amplitude is constant. The device realizes the drive of the micro-mechanical gyroscope and the digitization of the angular velocity demodulation, has simple structure and high computation precision, and is easy to produce and transplant in batch.

A noise attenuator loop filter for PLL applications that allows a full on-chip integration of the loop filter capacitors, while ensuring a low output clock phase noise (jitter) is disclosed. A voltage attenuator (A) is inserted between the loop filter (passive or active) and the controlled oscillator. The attenuator attenuates the noise coming from the loop filter. In case of a passive RC filter, the series resistor noise power is attenuated by A2 times, allowing the usage of a resistor that is A2 times larger and therefore the loop filter capacitors result A2 times smaller (easy to integrate on-chip). The relatively low value capacitor allows the usage of thick-oxide accumulation-mode MOSFET capacitors that take a reasonable low area, have a good linearity, are isolated from the substrate by the grounded N-well, and have negligible gate leakage current. Several embodiments of the noise attenuator are proposed for different practical applications: clock generation for digital circuits, frequency translation, low or high supply voltage, narrow or wide frequency range, processes with or without isolated well devices, processes with or without polysilicon resistors, and medium or high reference spurs rejection.

A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using any harmonic frequency that overlaps the spectrum for any of the plurality of center frequencies.

The invention discloses a multifrequency phased array ultrasonic Doppler flow detection system and a multifrequency phased array ultrasonic Doppler flow detection method. The system comprises a central control processor, a frequency synthesizer, a transmitting part, a receiving part and a display, wherein the transmitting part comprises a transmitter, a power distribution network, a beam control network, a first beam subarray and a second beam subarray; the receiving part comprises a first beam receiver, a second beam receiver, a multi-beam forming network and a signal processor. The system is characterized in that the central control processor is respectively connected with the frequency synthesizer, the transmitter, the power distribution network, the beam control network, the first beam receiver, the second beam receiver, the multi-beam forming network and the signal processor. In the detection method of the system, beam deflection and dynamic focusing are realized through the phased array technology, multi-directional and multi-depth positions can be measured on the cross section of an integral pipeline, and by a mode of adjusting beam scanning dynamically, the processing timeof the beam scanning is reduced, and the measuring accuracy is improved.

There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

A digital cordless telecommunication system capable of maintaining the enhanced frequency stability of radio transmission signals from stationary base stations by use of a specific clock signal including either a high-precision clock or a reference clock as generated by main equipment. In this system the main equipment is provided with a high-precision oscillator that generates and issues a clock signal with increased pulse-phase accuracy, whist a respective one of the base stations is with a line interface for extraction of such high-precision clock signal from the high-precision oscillator, a reference oscillator which supplies a reference clock to a frequency synthesizer that generates a local oscillation signal, a frequency error detector operable to detect a difference or "error" in frequency between the reference clock of the reference oscillator and the high-precision clock of the line interface, and a reference oscillator controller which is responsive to receipt of the error signal from the frequency error detector for adjusting any possible frequency deviation of the reference oscillator causing the reference clock frequency of the reference oscillator to keep track of the frequency of the high-precision clock signal.

Transmitter architectures designed to accommodate both constant and non-constant of envelope modulation schemes and capable of providing local oscillator carrier frequencies within any one of numerous desired frequency bands, thus allowing compliance with many different communication standards. One example of a programmable frequency synthesizer includes a plurality of transmitter components and a microcontroller coupled to the frequency synthesizer and to the plurality of transmitter components. The microcontroller is adapted to provide a frequency control signal to the frequency synthesizer to control a frequency of the local oscillator carrier frequency. In addition, the microcontroller is also adapted to provide digital control signals to at least some of the plurality of transmitter components to turn on and off different ones of the plurality of transmitter components based on an operating mode of the transmitter, such that the transmitter can accommodate both constant envelope modulation and non-constant envelope modulation schemes.