39 results about "Glitch" patented technology

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention provides a glitch power consumption optimization system and method based on logic efficacy, and relates to the technical field of electrical digital data processing.The glitch power consumption optimization system based on the logic efficacy comprises a path efficacy calculation module used for determining the path logic efficacy, the path branch efficacy and the path electrical efficacy of each path, determining the path efficacy of each path; the burr source identification module is used for determining an actual delay difference value between the paths converged to the same path convergence point, and judging the path convergence point as a burr source when the actual delay difference value meets a preset burr source judgment condition; and the burr optimization module is used for generating burr optimization suggestions of the burr source. According to the scheme, potential glitch risks of different circuit topological structures can be rapidly evaluated without depending on a series of processes such as integration, physical implementation, parasitic parameter extraction, post-simulation and glitch power consumption evaluation, traditional experience-driven optimization is converted into data-driven scientific optimization, and the glitch power consumption optimization effect is improved.

The invention relates to the technical field of big data, and provides a transaction data processing method and device based on idle time, equipment and a medium, which can start a business thread to scan a market queue and a return queue in real time in a current transaction period so as to respond in time. In the continuous scanning process of preset times, when no new market information slice is scanned in the market information queue and no new return information is scanned in the return queue, calculating the current idle time according to an idle time determination strategy after the market information and the return are ensured to be processed; the operator type with high real-time performance is divided into the pre-calculation operator and the decision operator, the pre-calculation operator is processed in the current idle time, the decision operator is processed in the current transaction time, the idle time can be fully utilized, glitch time delay in the transaction process is reduced, and the performance and time delay penetration stability of a transaction system are improved.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The application provides a fractional-N multi-mode synchronous frequency divider and a PLL. The fractional-N multi-mode synchronous frequency divider comprises N frequency dividers connected in series, N-2 first logic modules connected in series and N+1 first flip-flops, and N is an integer greater than 2. The first logic module is configured to output a high level when a first input end of the first logic module and a second input end of the first logic module are both at a high level. The first flip-flop is configured to output a frequency division ratio switching signal corresponding to the first flip-flop when a signal received by a first input end of the first flip-flop is converted from a low level to a high level. The embodiment of the application realizes glitch-free switching inside the MMSD, and can effectively improve the accuracy of the fractional frequency output by the PLL.

A computing system for glitch power estimation receives a circuit design describing an electronic device and waveform data. One or more waveforms corresponding to one or more critical points in the circuit design are extracted from the waveform data. For each connected component, a zero-delay simulation is performed to generate a zero-delay output waveform associated with at least one internal node of the connected component, and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component. One or more glitch toggles in the delayed output waveform are identified based on a comparison between the zero-delay output waveform and the delayed output waveform. A glitch power associated with the connected component based on toggles identified as glitch in the delayed output waveform is computed, and a glitch power report file is generated based on the glitch power.

This disclosure relates to glitch suppression for FSK demodulation. According to an embodiment, a glitch suppression circuit includes a first-stage averaging circuit with programmable length, a second-stage averaging circuit, and a hysteresis comparator. The first stage uses a FIFO buffer to implement recursive shifting and averaging to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses a programmable threshold set based on the peak signal value to generate a clean output signal. This circuit removes glitches from the input signal of the frequency shift keying (FSK) demodulator while maintaining signal integrity at high bit rates. The programmable parameters allow for optimization based on desired glitch characteristics and system requirements.

The application discloses a kind of spin latches based on ultrafast magneto-optical dynamics, construction method and system, belong to spin dynamics technical field, the basic function of RS latch is realized by the angle of Co4&gamma-Graphyne system spin state control, successfully designed with RS latch as the foundation spin latch latch, the logic unit consumed is less, compared with the traditional latch, avoid the influence of glitch, and the entire completion time reaches ultra-high speed sub-picosecond, guarantee degree is more than 95%.This provides a train of thought for the design and application of new generation spin latch.

An electronic system and a method of using the electronic system are disclosed. The system includes a differential signal generator configured to generate a first single-ended signal and a second single-ended signal having opposite polarities. The input signal and the first and second single-ended signals transition between a first power supply voltage and a first ground voltage. The system also includes a glitch management circuit configured to generate an output signal based on the first and second single-ended signals. The output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to generate an output signal based on the first and second intermediate signals.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

An electronic system with a current-steering digital-to-analog converter using conversion cells capable of glitch elimination and skew alignment is shown. In a conversion cell, a differential switch pair is controlled by an input signal and an inverted input signal, to couple a current source to a positive output terminal and a negative output terminal of a differential analog output port. A cascode pair is coupled between the differential switch pair and the differential analog output port. A glitch elimination pair is controlled by the input signal and the inverted input signal to eliminate glitches at the differential analog output port. The glitch elimination pair is coupled to the differential analog output port without passing through the cascode pair. At the differential analog output port, the parasitic capacitance due to the glitch elimination pair is relatively small. The glitch elimination performance is thereby improved.

The invention relates to low power glitch detection circuitry for exposed power supplies in a system on chip. Embodiments of a glitch detector disposed in a digital circuit are disclosed. The glitch detector detects glitches in a digital power supply voltage on a digital power supply rail. The glitch detector includes glitch detection circuitry and an asymmetric memory element. The glitch detection circuitry is coupled to the digital supply rail and is configured to detect glitches on a digital supply voltage on the digital supply rail. The asymmetric memory element is operably associated with the glitch detection circuitry to generate a glitch detection signal, where the glitch detection signal is generated in a detection state in response to the glitch detection circuitry detecting the glitch on the digital supply voltage on the digital supply rail. The asymmetric memory element is asymmetrically configured such that leakage of charge from the asymmetric memory element drives the asymmetric memory element to generate the glitch detection signal in the detection state.

The invention relates to voltage glitch detection in an integrated circuit for detecting fault injection attacks. Example embodiments include an integrated circuit (411), the integrated circuit (411) including: a hardware accelerator (412) including a computing module (4131, 4132) configured to perform a computing function; and a glitch detector (4161, 4162) comprising a delay function (4131, 4132) and a comparator (4191, 4192), the comparator (4191, 4192) being arranged to compare an output from the delay function (4131, 4132) to an expected result to provide an output for detecting glitch, wherein the delay function (4131, 4132) of the glitch detector (4161, 4162) is provided at least in part by the computing function of the computing module (4131, 4132) in the hardware accelerator (412).

This invention relates to the field of industrial automation, specifically to a configurable digital input / output method and system with short-circuit protection and interference-free diagnostics. It includes an interconnected microcontroller and configurable channels. Each channel includes an output driver unit and an input acquisition unit, with the output terminal of the output driver unit and the input terminal of the input acquisition unit connected to the same physical port within a circuit board. The microcontroller is configured to perform the following: determine diagnostic excitation based on the channel's operating mode; acquire the actual voltage state of the corresponding physical port under the diagnostic excitation through the input acquisition unit to obtain a port readback value; and compare the port readback value with the expected logic value corresponding to the diagnostic excitation to generate a channel fault determination result. No modifications are made to the existing hardware structure of configurable digital input / output channels; the diagnostic and protection functions are implemented solely through the microcontroller's internal software logic.

According to an embodiment, a protection circuit for an asynchronous finite state machine (AFSM) circuit is proposed. The protection circuit includes a state decoder configured to generate a first state error signal in response to detecting a state fault condition associated with the AFSM circuit; a fault de-glitch subcircuit configured to receive the first state error signal and generate a second state error signal in response to the first state error signal being asserted for a duration greater than a predetermined threshold; and a set / reset register configured to generate a pulsed reset signal in response to the second state error signal being generated by the fault de-glitch subcircuit, the pulsed reset signal being asserted for a predetermined duration, and wherein the pulsed reset signal causes the AFSM circuit to be reset to a reset or idle condition.

The present specification discloses a test device, a test system, a test method, and a test apparatus. The test device provided in the present specification includes an FPGA chip capable of controlling a target power supply that supplies power to an MCU under test. In practice, different test logic programs can be configured in the FPGA chip based on actual needs, to satisfy a need of flexibly testing different types of MCUs under test. In addition, the FPGA chip in the test device can be used to generate a high-frequency clock signal, to ensure time accuracy when voltage glitch faults are injected into the MCU under test, so as to further ensure a test effect for the MCU under test.

A computing system includes a communication system comprising a glitch filter circuitry disposed in an integrated circuit (IC) device configured to receive an input signal and provide a glitch filter output signal based on the input signal. The glitch filter circuitry includes a control path circuitry configured to receive the input signal and generate a control signal based on detecting a glitch within the input signal, the control path circuitry including a configurable resistor capacitor (RC) filter circuitry configured to deliver a configurable RC filter circuitry output signal based on one or more selection signals. The control signal is based on the configurable RC filter circuitry output signal, and a data path circuitry configured to receive the control signal and mitigate glitches within the input signal based on the control signal.

The invention discloses a power system sampling data burr detection and repair method, which comprises the following steps of: acquiring a real-time digital sampling signal sequence, and defining a current sampling point Data, a front first sampling point bData, a front second sampling point bbData, a rear first sampling point aData and a rear second sampling point aaData; calculating the difference product between the current sampling point Data and the second sampling point bbData before the current sampling point Data and the difference product between the current sampling point Data and the second sampling point aaData after the current sampling point Data, and if the difference product result is smaller than zero, determining that the current sampling point Data is a burr point; calculating a replacement value xData, wherein the xData is an average value of the extrapolation prediction value and the interpolation estimation value; and covering the value of the burr point Data with the replacement value xData. Through a signal reconstruction algorithm of linear extrapolation and linear interpolation, high-precision repair of burr points can be realized under extremely low calculation overhead, and the fidelity of signals and the accuracy of subsequent calculation are ensured.

Dynamically updating a delay line code. A circuit for updating a delay line code is provided having a delay line having a first chain of interleaved logic gates and a second chain of interleaved logic gates. The circuit further include a first clock path generated based upon the first chain of interleaved logic gates and a second clock path generated based upon the second chain of interleaved logic gates, wherein an output of at least one logic gate is forced to zero prior to performing a code update.

Embodiments of a glitch detector provided in a digital circuit are disclosed. The glitch detector detects glitches in a digital power voltage on a digital power rail. The glitch detector includes glitch detection circuitry and an asymmetric memory element. The glitch detection circuitry is coupled to the digital power rail and is configured to detect a glitch on a digital power voltage on the digital power rail. The asymmetric memory element is operably associated with the glitch detection circuitry so as to generate a glitch detection signal where the glitch detection signal is generated in a detection state in response to the glitch detection circuitry detecting the glitch on the digital power voltage on the digital power rail. The asymmetric memory element is configured asymmetrically such that leaking charge from the asymmetric memory element drives the asymmetric memory element to generate the glitch detection signal in the detection state.

The invention discloses an exception detection method and device, a storage medium and a product, and relates to the technical field of exception detection.The method comprises the steps that when a front-end driver of a system is loaded, negotiation configuration information of the front-end driver and back-end hardware is obtained and cached to a virtual function state maintenance module of the back-end hardware; the negotiation configuration information comprises a port state of a virtual function port; operation interaction information of the front-end drive and the rear-end hardware during operation of the VirtIO hardware unloading system is obtained; and performing exception detection according to the port state of the virtual function port cached in the virtual function state maintenance module and the operation interaction information to obtain an exception detection result, in this way, the exception data can be captured and identified when the software driver just starts to generate exception or exit, exception handling and self-healing are performed in time, and the reliability of the software driver is improved. The fault influence range is reduced, and the stability and reliability of the whole system are improved.

This disclosure provides an I / O sampling method, apparatus, and electronic device. The I / O sampling method includes: receiving an I / O input signal; sampling the I / O input signal on the rising edge and falling edge according to a clock cycle signal to obtain a rising edge sampled signal and a falling edge sampled signal; comparing the rising edge sampled signal and the falling edge sampled signal to obtain a comparison result; selecting a signal to be output from a previously output sampled signal and a current sampled signal based on the comparison result, wherein the current sampled signal is either the rising edge sampled signal or the falling edge sampled signal; and outputting the signal to be output as a sampled signal corresponding to the I / O input signal. This technical solution can improve the I / O sampling accuracy in scenarios with numerous glitches and jitter.

Systems and techniques are described for providing a power supply glitch detector. For example, a computing device can generate (e.g., using a first supply scale-down engine connected to a power supply) based on a lower voltage threshold, a first voltage close to a reference voltage, compare (e.g., using a first comparator) the first voltage with the reference voltage, and generate, based on determining the first voltage is less than the reference voltage, a low flag indicating detection of a fault in the power supply. The computing device can generate (e.g., using a second supply scale-down engine connected to the power supply), based on an upper voltage threshold, a second voltage close to the reference voltage, compare (e.g., using a second comparator) the second voltage with the reference voltage, and generate, based on determining the second voltage is greater than the reference voltage, a high flag indicating detection of the fault.

The application discloses a timing adjustment device, method, high-bandwidth memory and chip, the device comprises a delay determination circuit and a delay adjustment circuit; the delay determination circuit is used for outputting a preset delay value and receiving a phase feedback signal of DRAM; after determining a metastable signal from the phase feedback signal, a flip point is determined based on the metastable signal; the target delay value is determined and output according to the flip point; the delay adjustment circuit is used for adjusting the phase of the write data gate signal multiple times according to the received preset delay value, and sending the write data gate signal after each adjustment to the DRAM; after receiving the target delay value, the phase of the write data gate signal after the last adjustment is adjusted according to the target delay value, and the target write data gate signal is output. Therefore, the flip point is more accurately judged based on the delay determination circuit and the delay adjustment circuit, the misjudgment caused by jitter or glitch is avoided, and then the accurate writing of data of the DRAM based on the target write data gate signal is ensured.

The invention relates to the technical field of integrated circuit design, in particular to a circuit glitch optimization method and device based on static time sequence analysis, electronic equipment and a storage medium. According to the circuit glitch optimization method based on static time sequence analysis, data path time delay is directly analyzed and balanced based on static time sequence analysis; on the premise that time sequence convergence is maintained, multi-channel time delay of an input node of the same device is accurately balanced, competition conditions can be effectively restrained, the occurrence probability and amplitude of burrs are reduced from the source, and therefore dynamic power consumption caused by the occurrence probability and amplitude of the burrs is reduced; furthermore, by embedding a physical design and sign-off tool chain, data conversion and transmission among multiple tools are avoided, the process is remarkably simplified, the error risk is reduced, the optimization period is shortened, optimization can be dynamically implemented according to the design stage, and the efficiency and reliability of chip design are integrally improved.

The application belongs to the technical field of analog integrated circuits, and discloses a zero drift architecture of an improved chopping plus self-stable zero structure. The zero drift architecture comprises two loops, and the two loops are in a ping-pong mode. The loop comprises an operational amplifier AMP1, an operational amplifier AMP2, a clock switch group and a dummy switch, and the operational amplifier AMP1 and the operational amplifier AMP2 are electrically connected. The clock switch groups of the two loops are strictly non-overlapping with each other. The clock switch group comprises a switch d1 and a switch d2, the on-off states of the switch d1 and the switch d2 are opposite, the clocks of the switch d1 and the switch d2 are in a complementary relationship, and the dummy switch corresponds to the switch d2. In the prior art, the LPF compresses the signal bandwidth and cannot completely eliminate the high-frequency glitches. At the same time, the residual offset (tens of nV to hundreds of nV) is caused, and the absolute zero offset cannot be realized. Compared with the prior art, the application realizes the direct current precision close to zero offset and the low-ripple output signal, does not sacrifice the signal bandwidth, and reduces the design difficulty of the subsequent circuit.

A method can include performing at least one glitch resistance operation and detecting, by a circuit included in a glitch detector coupled via a connection matrix to a first processing unit, an indication of a glitch on a memory system. The method can include notifying, via the connection matrix, at least a second processing unit of the detected indication of the glitch. The method can include subsequent to notifying at least the second processing unit, transmitting via the at least the second processing unit a glitch confirmation signal.