83 results about "Glitch" patented technology

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

The invention discloses a fault determination method and device, equipment and a computer storage medium. The method comprises the steps of obtaining operation data of multiple devices in a preset time period, constructing a first time-delay matrix and multiple second time-delay matrixes of the operation data by using a sliding window, calculating a first Cauchy-Schwarz divergence of the first time-delay matrix and a target second time-delay matrix, the target second time-delay matrix being any one of the multiple second time-delay matrixes, and calculating a second Cauchy-Schwarz divergence of the target second time-delay matrix; and if the first Cauchy-Schwarz divergence is greater than a first threshold value, determining that the operation data corresponding to the target second time-delay matrix is abnormal, and determining that a plurality of devices fail. In this way, the Cauchy-Schwarz divergence of the first time-delay matrix and the second time-delay matrix is calculated, that is, the fault problem is detected according to the difference degree of probability distribution between the data in the normal state and the test data, the fault is recognized earlier and more accurately, and the detection rate of the tiny fault is increased.

Techniques are described for offloading an audio pump from a central processing unit (CPU) of a computing device to an audio co-processor. A device graph for an audio endpoint can be modified to include a processing pipeline for an audio stream from an application. Audio data from the audio stream can be retrieved by the audio co-processor from a shared buffer accessible to the application and the audio co-processor. The processing pipeline for the audio stream can include a series of audio processing objects (APOs) linked by connection buffers. Audio data from the audio stream can be processed by executing an audio pump thread with the audio co-processor. Multiple audio streams can be executed in parallel by the audio pump thread, including render, capture, and loopback streams, with better glitch resilience, relatively low latency, and a better power profile.

The invention provides a synchronous optimization control method and system for suppressing burrs in a clock switching circuit, and relates to the technical field of application-specific integrated circuits, and the method comprises the steps: carrying out the synchronous processing of a clock switching control signal, and generating a synchronous gating signal for clock gating after the metastable state is eliminated through multi-beat sampling; performing logic AND operation on the basis of the synchronous gating signal and at least two clock sources to realize clock switching, and setting a time sequence constraint containing establishment time and retention time for a logic AND operation unit; a transmission path of a synchronous gating signal is optimized through rear-end layout wiring, signal gradual change time is compressed, it is ensured that time sequence constraint is met, and burr-free clock output is achieved. The clock switching circuit solves the technical problems of burr generation, time sequence mismatch and system instability caused by a metastable state in a clock switching circuit in the prior art.

The invention provides a glitch power consumption optimization system and method based on logic efficacy, and relates to the technical field of electrical digital data processing.The glitch power consumption optimization system based on the logic efficacy comprises a path efficacy calculation module used for determining the path logic efficacy, the path branch efficacy and the path electrical efficacy of each path, determining the path efficacy of each path; the burr source identification module is used for determining an actual delay difference value between the paths converged to the same path convergence point, and judging the path convergence point as a burr source when the actual delay difference value meets a preset burr source judgment condition; and the burr optimization module is used for generating burr optimization suggestions of the burr source. According to the scheme, potential glitch risks of different circuit topological structures can be rapidly evaluated without depending on a series of processes such as integration, physical implementation, parasitic parameter extraction, post-simulation and glitch power consumption evaluation, traditional experience-driven optimization is converted into data-driven scientific optimization, and the glitch power consumption optimization effect is improved.

The invention discloses a multi-interface software and hardware dual-definition precise fault injection device based on electrical layer signals. The device comprises an MCU / CPU system, a hardware coprocessor module, a high-speed ASIC FIFO sending module, a high-speed DAC module, a burr injection module, an external interrupt high-speed ASIC hardware trigger module, a power-down burr driving module and a peripheral communication module. The MCU / CPU module is electrically connected with the hardware coprocessor module, the high-speed ASIC FIFO sending module, the external interrupt ASIC hardware triggering module, the burr injection module, the power-down burr driving module and the peripheral communication module. The hardware coprocessor module is electrically connected with the high-speed ASIC FIFO sending module and the high-speed DAC module, the high-speed DAC module is electrically connected with the burr injection module, and the high-speed ASIC FIFO sending module is electrically connected with the external interrupt high-speed ASIC hardware trigger module. The technical problems that an existing fault injection hardware device is complex in structure and cannot adapt to diversified application scenes are solved.

The invention relates to the technical field of big data, and provides a transaction data processing method and device based on idle time, equipment and a medium, which can start a business thread to scan a market queue and a return queue in real time in a current transaction period so as to respond in time. In the continuous scanning process of preset times, when no new market information slice is scanned in the market information queue and no new return information is scanned in the return queue, calculating the current idle time according to an idle time determination strategy after the market information and the return are ensured to be processed; the operator type with high real-time performance is divided into the pre-calculation operator and the decision operator, the pre-calculation operator is processed in the current idle time, the decision operator is processed in the current transaction time, the idle time can be fully utilized, glitch time delay in the transaction process is reduced, and the performance and time delay penetration stability of a transaction system are improved.

Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector. The self-testing glitch signal is further fed back to the glitch controller for verification, and the glitch controller presents an error of the self-testing glitch signal by an error flag.

The present application relates to the technical field of integrated circuits, and discloses a false trigger prevention circuit, method, system, power amplifier circuit and device, which comprises an input circuit, a glitch trigger circuit and a logic circuit, the output end of the input circuit is connected with the input end of the glitch trigger circuit, and the output end of the glitch trigger circuit and the input end of the input circuit are both connected with the input end of the logic circuit, so that the false trigger problem of the existing N-type power tube caused by glitches is solved.

The disclosure provides a circuit (700) and method for correcting single event upsets, SEUs, or glitches in electronic circuits. The circuit includes rising and falling edge detection sub-circuits (710, 712) connected to a sequential circuit element output (706) which generate signals if the sequential circuit element output changes logic levels, and comparison sub-circuits (716, 724) which compare the signal from the edge detection sub-circuits with a signal generated on an active edge of a clock signal of the sequential circuit element. The comparison sub-circuits detect an SEU or glitch if their two signals do not coincide. First and second gating sub-circuits (720, 728) permit the outputs of the comparison sub-circuits to asynchronously set or reset the sequential circuit element (702).

The invention discloses a burr filtering circuit, method and device, a medium and a program product, and the burr filtering circuit comprises a first time delay circuit which is used for delaying an input signal by a time delay width; the first logic gate circuit is used for filtering high-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second logic gate circuit is used for filtering low-level burrs of which the width is smaller than or equal to the delay width in the input signal; the second delay circuit is used for delaying the input signal by two delay widths; the third logic gate circuit is used for ensuring that the signal with the length greater than two delay widths is not filtered; and the fourth logic gate circuit is used for outputting a target serial signal, and the target serial signal is a signal obtained by filtering high-level burrs and low-level burrs of which the widths are less than or equal to the delay width of the input signal and delaying for one delay width. The burr filtering circuit provided by the embodiment of the invention is simple in circuit structure, small in size, easy to change in filtering width and low in output delay.

The application provides a fractional-N multi-mode synchronous frequency divider and a PLL. The fractional-N multi-mode synchronous frequency divider comprises N frequency dividers connected in series, N-2 first logic modules connected in series and N+1 first flip-flops, and N is an integer greater than 2. The first logic module is configured to output a high level when a first input end of the first logic module and a second input end of the first logic module are both at a high level. The first flip-flop is configured to output a frequency division ratio switching signal corresponding to the first flip-flop when a signal received by a first input end of the first flip-flop is converted from a low level to a high level. The embodiment of the application realizes glitch-free switching inside the MMSD, and can effectively improve the accuracy of the fractional frequency output by the PLL.

The embodiment of the invention provides a burr optimization system and method applied to a DAC (Digital-to-Analog Converter), and the system comprises an I / O clock module, an input data register, a DAC register, a DAC digital-to-analog converter and a sampling and holding circuit which are connected in sequence, and also comprises a logic control module, a sampling and holding control module and an analog delay module, a DAC register is arranged to transfer input data, digital-to-analog conversion is directly carried out through a DAC to obtain converted voltage, the influence of the input data register on the output voltage of the DAC during data updating is avoided, and by arranging an internal clock and an analog delay module, a sampling and holding control signal is delayed by a set phase difference and then sent to a sampling and holding circuit; the time sequence control is optimized, so that the sampling holding signal and the data updating signal are performed in sequence, the interference of the data updating signal on the sampling voltage is eliminated, the analog delay module enables the control signal of the sampling holding circuit and various clock signals in the chip to generate phase difference, and the sampling voltage is prevented from being interfered by the clock in the chip.

A computing system for glitch power estimation receives a circuit design describing an electronic device and waveform data. One or more waveforms corresponding to one or more critical points in the circuit design are extracted from the waveform data. For each connected component, a zero-delay simulation is performed to generate a zero-delay output waveform associated with at least one internal node of the connected component, and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component. One or more glitch toggles in the delayed output waveform are identified based on a comparison between the zero-delay output waveform and the delayed output waveform. A glitch power associated with the connected component based on toggles identified as glitch in the delayed output waveform is computed, and a glitch power report file is generated based on the glitch power.

This disclosure relates to glitch suppression for FSK demodulation. According to an embodiment, a glitch suppression circuit includes a first-stage averaging circuit with programmable length, a second-stage averaging circuit, and a hysteresis comparator. The first stage uses a FIFO buffer to implement recursive shifting and averaging to process a binary input signal. The second stage provides moving average filtering. The hysteresis comparator uses a programmable threshold set based on the peak signal value to generate a clean output signal. This circuit removes glitches from the input signal of the frequency shift keying (FSK) demodulator while maintaining signal integrity at high bit rates. The programmable parameters allow for optimization based on desired glitch characteristics and system requirements.

The application discloses a kind of spin latches based on ultrafast magneto-optical dynamics, construction method and system, belong to spin dynamics technical field, the basic function of RS latch is realized by the angle of Co4&gamma-Graphyne system spin state control, successfully designed with RS latch as the foundation spin latch latch, the logic unit consumed is less, compared with the traditional latch, avoid the influence of glitch, and the entire completion time reaches ultra-high speed sub-picosecond, guarantee degree is more than 95%.This provides a train of thought for the design and application of new generation spin latch.

The application discloses a digital processing circuit, comprising a logic unit, at least one combinational logic device, the combinational logic device comprising at least one input terminal; a filter unit is used to divide the waveform of the received initial input signal into at least two segments of waveforms within a cycle of the clock signal of the combinational logic device, and to prevent the back propagation of glitches contained in at least one segment of waveforms, so as to provide a filtered input signal to the input terminal of the combinational logic device. By preventing the back propagation of the glitches contained in at least one segment of waveforms in the initial input signal through the filter unit, the application can eliminate the influence of the glitches in the signal on the power consumption of the entire circuit in time, so as to effectively reduce the additional power consumption caused by the glitches.

Disclosed is an information processing apparatus (104). The information processing apparatus (104) includes processing circuitry (122) configured to receive, from a user 5 of a set of users, a glitch report associated with at least one digital asset of one or more digital assets, initiate a glitch bounty payment when the glitch report is validated and verified by way of a smart contract associated with the at least one digital asset, assign the glitch report to at least one user of the set of users for mitigation of one or more glitches, generate one or more recommendations based on the type of severity assigned 10 to the one or more glitches by way of one of, one or more AI techniques, one or more ML techniques, or a combination thereof, and update a status of the glitch report.

An electronic system and a method of using the electronic system are disclosed. The system includes a differential signal generator configured to generate a first single-ended signal and a second single-ended signal having opposite polarities. The input signal and the first and second single-ended signals transition between a first power supply voltage and a first ground voltage. The system also includes a glitch management circuit configured to generate an output signal based on the first and second single-ended signals. The output signal transitions between a second power supply voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single-ended signals and generate first and second intermediate signals. The first and second intermediate signals each transition between the second power supply voltage and the second ground voltage. The system also includes a second latch configured to generate an output signal based on the first and second intermediate signals.

An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.

The present invention provides a SOC multi-clock glitch-free switching circuit, which relates to the field of SOC integrated circuits. The present invention simplifies the steps required for multi-clock switching by setting a hardware circuit. When the system switches the clock, it only needs to set the corresponding clock code in the system register. The clock code is compiled into a one-hot encoded clock code by a first encoder and is respectively handed over to each clock branch; each clock branch determines whether it matches the clock connected to itself based on the clock code. If it matches, the corresponding clock is output to complete the clock switching; the present invention only needs to set the corresponding system register. For the software layer, it is not necessary to pay attention to the clock switching steps to obtain the desired clock, thereby solving the problem that the switching method of the prior art needs to be carried out in several steps. In addition, the present invention also provides a clock indication unit. The system can know the current real clock by reading the output signal of the clock indication unit.

An electronic system with a current-steering digital-to-analog converter using conversion cells capable of glitch elimination and skew alignment is shown. In a conversion cell, a differential switch pair is controlled by an input signal and an inverted input signal, to couple a current source to a positive output terminal and a negative output terminal of a differential analog output port. A cascode pair is coupled between the differential switch pair and the differential analog output port. A glitch elimination pair is controlled by the input signal and the inverted input signal to eliminate glitches at the differential analog output port. The glitch elimination pair is coupled to the differential analog output port without passing through the cascode pair. At the differential analog output port, the parasitic capacitance due to the glitch elimination pair is relatively small. The glitch elimination performance is thereby improved.

The invention discloses a remote rocket ammunition-oriented clock synchronization signal processing method, which is applied to a missile-borne component for receiving a reference clock synchronization pulse signal and can improve the clock synchronization reliability of the missile-borne component so as to improve the flight control reliability of a remote rocket. The processing method mainly comprises the following steps: 1) filtering an input synchronizing signal to filter burrs; 2) waiting for a module starting instruction of the system; 3) detecting a rising edge of the synchronization signal; 4) when the rising edge interval of the synchronization signal is less than or equal to the preset period, indicating that the synchronization signal state is normal, and forwarding the satellite synchronization signal; and 5) when the rising edge interval of the synchronizing signal is greater than a preset period, indicating that the state of the synchronizing signal is abnormal, and generating an analog synchronizing signal to be output. According to the invention, the missile-borne part can stably and reliably obtain the clock synchronization signal, and the stable operation of the missile-borne part is ensured.

A glitch-free multi-clock switching circuit supporting testability design relates to integrated circuit technology. The invention comprises a clock selection decoding circuit and N parallel clock signal branches, where N is an integer greater than 2; the clock signal branches comprise: a selector, a reset processor, a multi-input AND gate, a synchronizer, a branch D flip-flop, and a gated clock module; the bypass control terminal of each clock signal branch is connected to a bypass input terminal of the multi-input AND gate in all other branches, and each bypass input terminal is only connected to one bypass control terminal. The invention supports glitch-free clock switching, and the invention switches at the falling edge of the clock. Due to the existence of negative feedback, it is ensured that only one clock is turned on at the same time.

The invention discloses a method and a device for eliminating electrification burrs on a GPIO (General Purpose Input / Output) circuit, and the method comprises the steps: S11, generating a VTHEN detection signal through a power supply electrification threshold detection circuit, and detecting whether the power supply voltage of a CORE voltage domain reaches the minimum voltage value required by the normal work of the circuit or not; step S12, controlling the Level Shift to output a fixed state in the stage through a VTHEN signal; step S13, controlling one or more of the output buffer, the pull-up resistor and the pull-down resistor under the control of the VTHEN; and S14, in the power-on stage, GPIO output is fixed to be low, and output burrs are eliminated. The device is used for implementing the method. The method has the advantages of being simple in principle, easy to implement, capable of thoroughly eliminating burrs caused by power-on delay and the like.

A semiconductor device is protected against glitch attacks (FIA). A reset data transfer controller (RDTC) performs N data transfers, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparator circuit (CMP1) determines the match / mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs and outputs a determination result signal RS representing the determination result. A system controller (SYSC) activates a processor (PRC) when the determination result signal RS indicates a match and causes the reset data transfer controller (RDTC) to re-execute the N data transfers when it indicates a mismatch.

A de-jitter circuit and method for masking or filtering glitches from an input signal are provided. The de-jitter circuit includes a reset synchronizer circuit and a logic circuit. The reset synchronizer circuit receives an input signal, detects glitches in the input signal, and outputs one or more reset synchronizer output signals, the one or more reset synchronizer output signals having a first reset synchronizer state indicating that a glitch has been detected. The logic circuit receives the one or more reset synchronizer output signals, determines that the one or more reset synchronizer output signals are in the first reset synchronizer state indicating that a glitch has been detected, and in response to determining that the one or more reset synchronizer output signals are in the first reset synchronizer state, maintains the output signal of the de-jitter circuit in the current state of the output signal of the de-jitter circuit.

The invention relates to low power glitch detection circuitry for exposed power supplies in a system on chip. Embodiments of a glitch detector disposed in a digital circuit are disclosed. The glitch detector detects glitches in a digital power supply voltage on a digital power supply rail. The glitch detector includes glitch detection circuitry and an asymmetric memory element. The glitch detection circuitry is coupled to the digital supply rail and is configured to detect glitches on a digital supply voltage on the digital supply rail. The asymmetric memory element is operably associated with the glitch detection circuitry to generate a glitch detection signal, where the glitch detection signal is generated in a detection state in response to the glitch detection circuitry detecting the glitch on the digital supply voltage on the digital supply rail. The asymmetric memory element is asymmetrically configured such that leakage of charge from the asymmetric memory element drives the asymmetric memory element to generate the glitch detection signal in the detection state.

The invention relates to voltage glitch detection in an integrated circuit for detecting fault injection attacks. Example embodiments include an integrated circuit (411), the integrated circuit (411) including: a hardware accelerator (412) including a computing module (4131, 4132) configured to perform a computing function; and a glitch detector (4161, 4162) comprising a delay function (4131, 4132) and a comparator (4191, 4192), the comparator (4191, 4192) being arranged to compare an output from the delay function (4131, 4132) to an expected result to provide an output for detecting glitch, wherein the delay function (4131, 4132) of the glitch detector (4161, 4162) is provided at least in part by the computing function of the computing module (4131, 4132) in the hardware accelerator (412).