125results about "Instant pulse delivery arrangements" patented technology

The invention discloses a memristor-based signal detection circuit and method, a receiver and equipment, and relates to the field of wireless communication, a voltage source module of the circuit is connected with a voltage input end of a memristor array module, and a current source module is connected with a current input end of the memristor array module; the current output end of the memristor array module is connected with the reverse input end of the operational amplifier module and one end of the feedback resistor module, the other end of the feedback resistor module and the output end of the operational amplifier module are connected with the input end of the multiplier module, and the output end of the multiplier module is connected with one end of the resistor module. The voltage of the voltage source module is set according to the emission vector set; the current of the current source module is set according to the received radio frequency signal, and the conductance value of the memristor is set according to the channel matrix, so that a relatively low bit error rate of signal detection can be realized on the basis of greatly reducing calculation time and power consumption, and meanwhile, the requirement on programmable bit precision of the memristor is also reduced.

The invention discloses a SiC MOSFET hard switching loss measurement method and system without a current sensor, which cancel current measurement on the basis of a double-pulse measurement method and obtain a current waveform by analyzing voltage waveform change characteristics. Wherein the measurement of the drain-source voltage is very simple and convenient, the layout and the size of the converter are not influenced, and the measurement time is very short. The method can be popularized to any topology with an equivalent half-bridge commutation loop.

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

The invention provides a clock frequency monitoring circuit and method, and the circuit comprises a first multiplexer which selects and outputs a first clock signal; the second multiplexer is used for selectively outputting a second clock signal; the first counter is triggered based on the first enable signal and is used for counting the first clock signal progressively until the first clock signal progressively decreases to 0; the second counter is triggered based on the second enable signal, performs incremental counting on the second clock signal and outputs a count value; the count value comparison module is used for comparing the count value with a target set value and outputting a state indication signal according to a comparison result; the counter heavy load controller is used for generating a first enable signal and a second enable signal according to the first clock signal and the second clock signal, and triggering the count value comparison module to start working after the counting of the second counter is finished; and determining whether to restart the next round of monitoring according to the state indication signal. By using the scheme of the invention, monitoring of any clock frequency to be measured can be realized.

The invention relates to an improved ABSPD clock recovery method under single Baud rate sampling, clock synchronization of receiving and transmitting end signals is realized through a clock recovery loop based on a full number font, and when a provided timing error detector calculates a timing error e, symbol judgment and shift operation are used for replacing numerical multiplication; after a timing error e is calculated by the timing error detector, the timing error e is input into a loop filter for noise filtering, and a control word W is obtained; controlling the numerically controlled oscillator by using the control word W, and calculating a fractional interval mu k according to the output NCO of the numerically controlled oscillator and the control word W; and carrying out interpolation on the received signal in an interpolation filter by utilizing the integer mark mk of the symbol and the calculated fractional interval mu k so as to calculate and obtain data with correct timing. According to the invention, ABSPD clock recovery under single Baud rate sampling without multiplication operation is realized, and the complexity of the whole clock recovery loop is obviously reduced.

The invention discloses a nanosecond steep pulse excitation system and a nanosecond steep pulse excitation method. The nanosecond steep pulse excitation system comprises a high-voltage pulse generation module, a controller, an impedance detection module and a treatment electrode, the high-voltage pulse generation module is used for receiving a control signal monitored by the controller and outputting a high-voltage pulse to the treatment electrode; the impedance detection module comprises a measuring electrode, tissue impedance data are collected through the measuring electrode, and the impedance data are dynamically fed back to the controller; the controller dynamically adjusts parameters of the high-voltage pulse generation module according to impedance data to form closed-loop control, the Marx circuit is optimized, the high-voltage pulse generation efficiency is high, nanosecond-level accurate triggering is achieved through embedded control, effective deposition of high-frequency energy is ensured, transient voltage spikes are reduced, impedance changes are detected in real time through the impedance detection module, and the control precision is improved. The pulse width or amplitude is dynamically adjusted, pulse parameters are adjusted in real time based on impedance changes, and excessive ablation or insufficient treatment is avoided.

The invention relates to a cross-clock-domain data synchronization method, an FIFO control circuit and a synchronization circuit, and the method comprises the steps: obtaining a first clock cycle number passed by a source clock domain in target time if the write clock frequency of the source clock domain is different from the read clock frequency of a target clock domain, the first clock period number and the second clock period number passed by the target clock domain within the target time are both integers; under the condition that the first clock cycle number is larger than the second clock cycle number, multiple first effective clock signals are generated every time a target time passes, the multiple first effective clock signals are generated within the target time, the number of the first effective clock signals is the second clock cycle number, and data writing control is carried out based on the first effective clock signals, the cross-clock domain data synchronization is completed; according to the method, the cross-clock-domain data synchronous transmission between clocks with different frequencies is well realized, the implementation is relatively high, and the cost is relatively low.

To provide a wireline receiver with improved timing and associated margins. [Solution] A wireline receiver comprising a data sampler sa0, a first edge sampler sa1, a second edge sampler sa2, a base phase detection circuit 222, an additional phase detection circuit 224, a clock circuit 240, and a phase shift circuit 250, wherein the data sampler, the first edge sampler, and the second edge sampler, when triggered by the data clock, the first edge clock, and the second edge clock, respectively, sample and compare the receiver signal to determine whether the receiver signal exceeds the data threshold level, the first threshold level, and the second threshold level, thereby providing a basis for phase detection. In response to phase detection, the clock circuit provides the first edge clock and the data clock, and the phase shift circuit provides the second edge clock by phase shift.

The utility model provides a signal jitter elimination circuit, a control chip and an electronic device, and relates to the technical field of power electronics, and the circuit comprises a first jitter elimination circuit used for carrying out multi-stage delay on a received original reset signal to obtain a logic OR signal maintaining a first level state, so that when the control chip is in a de-reset state, the logic OR signal maintains the first level state; filtering out a first burr of which the duration is less than a first preset duration in the original reset signal; the second jitter elimination circuit is used for carrying out multi-stage delay on the logic OR signal to obtain a logic AND signal for maintaining a second level state so as to filter out a second burr of which the duration is less than the first preset duration in the original reset signal when the control chip is in a reset state; the counter is used for determining a count value of the logic AND signal in the second level state; the count value is used for filtering out the third burr of which the duration is longer than the first preset duration in the original reset signal. According to the utility model, comprehensive jitter elimination of the whole reset life cycle of the original reset signal can be realized.

The invention discloses a continuous current pulse generation circuit for power device testing and a control method thereof, and relates to the technical field of power electronics, the continuous current pulse generation circuit comprises a power supply, a control unit, a switch unit, an energy storage unit, an inductive load and a current absorption unit; the switch unit comprises a first relay, a second relay, a third relay, n first switches and one second switch; the energy storage unit comprises n capacitors; the control unit is used for respectively controlling the on-off of the first relay, the second relay, the third relay, the n first switches and the n second switches, carrying out different-stage control on each capacitor, and providing continuous current pulse for the test of the power device; the different stages comprise a capacitor charging stage, a capacitor discharging stage according to a time sequence and a capacitor residual charge releasing stage. According to the invention, more real continuous current pulse can be provided for the power device, and the reliability test requirement of the device under the impact of the continuous current pulse is met.

A radio frequency (RF) monitoring apparatus (102), comprising: an RF forward input port (116) and corresponding reverse input port (118); a tunable filter (218); an RF detector (220); an electronic processor (202) comprising a tuning signal output (208), wherein the processor (202) is configured to selectively generate a tuning signal at the tuning signal output corresponding with one or more specified frequency sub-bands, to record RF power signals generated by the RF detector (220) corresponding with RF signals received at the forward and reverse input ports (116, 118) within the specified frequency sub-bands, and to provide monitoring signals determined from the recorded RF power signals.

An active inductor modulator circuit is provided. The active inductor modulator circuit can include a circuit to receive an input signal and provide an output signal at an output terminal of the circuit based on a clock signal. A modulated active inductor is coupled to the circuit to improve the time delay between the input signal and the provided output signal. A modulation clock circuit can also be included to generate a delayed clock signal to activate the modulated active inductor before the output signal transitions from a first logic state to a second logic state.

The embodiment of the invention provides a wide dynamic range signal acquisition method and circuit, and the method comprises the steps: a quadrupole is connected with an ion receiving electrode, the ion receiving electrode is connected with a transimpedance amplifier circuit, the transimpedance amplifier circuit is connected with a threshold comparison circuit, the threshold comparison circuit is connected with a D trigger circuit, and the D trigger circuit is connected with a dead time correction circuit. The lower computer FPGA is connected with the D flip-flop circuit; the quadrupole is used for screening ion signal output; the ion receiving electrode is used for converting the ion signal into a current signal; the transimpedance amplifier is used for converting the current signal into a voltage signal; the threshold comparison circuit is used for turning the voltage signal into a logic level; the D flip-flop circuit is used for outputting a target signal level matched with the lower computer FPGA; and the lower computer FPGA is used for receiving the target signal level and counting the signals acquired by the plurality of pulses through the dead time correction circuit. In this way, the phenomenon of counting omission under high-frequency signals is reduced, and the counting accuracy is improved.

A circuit arrangement comprises a comparator circuit configured for comparing a voltage to a provided reference voltage and a time evaluation circuit configured for determining a time interval between a start signal and a stop signal. The circuit arrangement further comprises a voltage ramp generation circuit configured for generating a voltage ramp beginning with the start signal. In a normal operation mode, the circuit arrangement is configured for comparing an input voltage to the reference voltage by using the comparator circuit. In a self-test mode for performing a self-test of the comparator circuit, the circuit arrangement is configured for generating a voltage ramp by using the voltage ramp generation circuit, for continuously comparing the generated voltage ramp to the reference voltage by using the comparator circuit and for determining a time interval in which the generated voltage ramp reaches the reference voltage by using the time evaluation circuit.

The invention provides a multi-input pulse shaping circuit based on current addition and electronic equipment, and relates to the field of integrated circuits. The input end of each path of detection unit in the multiple paths of detection units is connected with one pixel, and the output end of each path of detection unit is connected with the input end of one path of trigger signal unit. According to the comparator circuit, the amplitude of the signal transmitted to the input end of the comparator through the summing circuit is far higher than that of the signal transmitted to the input end of the comparator through a traditional circuit structure, the threshold voltage range can be set to be high, and the comparator circuit meeting the requirement can be designed with a small area. A good measurement dynamic range can be achieved under the condition that the area of a chip is saved, and meanwhile the risk of false triggering is avoided. And tiny disturbance generated by a single pixel under the condition of no input signal cannot be detected, so that the working reliability of a chip is improved. The multi-input pulse shaping circuit structure based on current addition can enable a front-end circuit to reach an excellent dynamic range under the condition of saving the area of a comparator.

To provide a pulse width measuring circuit with which a measurement time is shortened.SOLUTION: A first programmable delay circuit 130 and a second programmable delay circuit 140 respectively delay a first pulse S1 and a second pulse S2 corresponding to an input pulse SIN and generate a first delay pulse Sd1 and a second delay pulse Sd2. A latch circuit 150 latches the first delay pulse Sd1 in response to an edge of the second delay pulse Sd2. A controller 160 continuously sweeps a delay amount τ2 of the second programmable delay circuit 140 in first processing, and detects a first delay mount τP when the output Q of the latch circuit 150 changes. In second processing, the delay amount τ2 of the second programmable delay circuit 140 is changed by a binary search and a second delay amount τn is detected when the output Q of the latch circuit 150 changes. The difference between the first delay amount τP and the second delay amount τn is made a pulse width Tp of the input pulse SIN.SELECTED DRAWING: Figure 1

The invention discloses a QCA fault detection circuit and detection method based on test clock control, and belongs to the technical field of quantum cellular automaton circuit detection. According to the invention, the arrangement of the programmable clock generation circuit layer, the metal sheet layer, the five clock signal lines, the five clock metal lines and the clock signal source is equivalent to the introduction of a test clock to the to-be-tested QCA circuit, and the test clock can send a test clock signal to a to-be-tested area in the to-be-tested QCA circuit when the to-be-tested QCA circuit is detected. According to the method and the device, fixed faults in the to-be-tested QCA circuit can be effectively detected, non-fixed faults in the to-be-tested QCA circuit can be effectively detected, and the detection success rate is relatively high from the aspect of the test effect.

The application discloses a signal detection circuit and method based on a memristor, a receiver and equipment, and relates to the field of wireless communication. A voltage source module of the circuit is connected with a voltage input end of a memristor array module, a current source module is connected with a current input end of the memristor array module, a current output end of the memristor array module is connected with an inverting input end of an operational amplifier module and one end of a feedback resistance module respectively, the other end of the feedback resistance module and an output end of the operational amplifier module are connected with an input end of a multiplier module, and an output end of the multiplier module is connected with one end of a resistance module. The voltage of the voltage source module is set according to a set of transmission vectors, the current of the current source module is set according to a received radio frequency signal, and the conductance value of the memristor is set according to a channel matrix. The application can realize a lower bit error rate of signal detection on the basis of greatly reducing the calculation time and power consumption, and also reduces the requirement for the programmable bit precision of the memristor.

The invention relates to comparator circuit self-testing. A circuit arrangement is presented, comprising: a comparator circuit configured to compare a voltage to a provided reference voltage; a time estimation circuit configured to determine a time interval between the start signal and the stop signal; and a voltage ramp generation circuit configured to generate a voltage ramp starting with the start signal. In a normal mode of operation, the circuit arrangement is configured to compare an input voltage to a reference voltage by using a comparator circuit. In a self-test mode in which a self-test of the comparator circuit is performed, the circuit arrangement is configured to generate a voltage ramp by using the voltage ramp generation circuit, continuously compare the generated voltage ramp to a reference voltage by using the comparator circuit, and determine a time interval at which the generated voltage ramp reaches the reference voltage by using the time estimation circuit. A method of performing a self-test of a comparator circuit is presented as well as a use of a circuit arrangement and a method of performing a self-test.

The invention provides a calibration method, a calibration device and a transceiver, and the device comprises a frequency doubling module which is used for receiving a reference clock signal and outputting a frequency doubling clock signal; the digital detection module is arranged in the digital baseband processing area and is used for detecting the duty ratio of the frequency doubling clock signal by adopting a digital-analog hybrid circuit structure and outputting duty ratio deviation information; and the delay adjusting module is respectively connected with the digital detection module and the frequency doubling module, and is used for adjusting a delay circuit in the frequency doubling module according to the duty ratio deviation information, so that the duty ratio of the frequency doubling clock signal is close to 50%. The digital detection module and the delay adjustment module form a closed loop to dynamically calibrate the duty ratio of the double-frequency clock to enable the duty ratio to be stable and close to 50%, in addition, through detection and adjustment of the digital module, the stability of a clock signal in a complex environment is enhanced, and the stability of the clock signal is improved. Therefore, the requirements of a transceiver, especially a narrowband transceiver, on high precision and high stability of the clock signal can be met.

The application provides a clock signal sinusoidal jitter calculation method, a computer device and a readable storage medium. The method comprises the following steps: obtaining frequency spectrum information of a to-be-tested clock signal injected with a sinusoidal jitter signal; identifying a plurality of target frequency points in the frequency spectrum information of the to-be-tested clock signal with a period of the sinusoidal jitter signal as a time interval, and determining amplitudes of the to-be-tested clock signal at the target frequency points; determining orders of the target frequency points according to the amplitudes of the to-be-tested clock signal at the target frequency points, and calculating an amplitude of the sinusoidal jitter signal by using the amplitudes corresponding to the target frequency points of each order based on a preset target function. The application also provides a computer device and a readable storage medium for implementing the above method. The application can reduce the amplitude calculation cost of the sinusoidal jitter signal and improve the accuracy of the amplitude calculation of the sinusoidal jitter signal.

The present invention provides a capacitance detection system and method, which relates to the field of electronic circuit technology, including: converting the capacitance value of the chip pin capacitance into a capacitance clock signal; periodically acquiring the capacitance clock signal as a real-time capacitance clock signal, calculating the capacitance value difference between the real-time capacitance clock signal and the latched historical capacitance clock signal each time the real-time capacitance clock signal is acquired, updating the latched historical capacitance clock signal to the real-time capacitance clock signal when the capacitance value difference is judged to be greater than a first resolution, and outputting an indication signal indicating a capacitance change when the capacitance value difference is judged to be greater than a second resolution. The beneficial effect is that the precise calculation method helps to accurately capture small changes in capacitance; the multi-resolution judgment mechanism improves the flexibility and accuracy of the system, and by setting a reasonable resolution threshold, the system can effectively reduce the false alarm rate caused by small fluctuations in capacitance, and improve the stability and reliability of the system.

The application relates to an improved ABSPD clock recovery method under single baud rate sampling, clock synchronization of transceiving end signals is realized through a full-digital type clock recovery loop, a timing error detector is used to replace numerical multiplication operation with symbol judgment and shift operation when calculating timing error e; after the timing error e is calculated by the timing error detector, the timing error e is input into a loop filter to remove noise and control words W are obtained; then the control words W are used to control a digital controlled oscillator, fractional interval mu k is calculated from the output NCO of the digital controlled oscillator and the control words W k The integer mark m k of the symbol and the calculated fractional interval mu k The received signal is interpolated in an interpolation filter, so that timing correct data are calculated. The application realizes ABSPD clock recovery under single baud rate sampling without multiplication operation, and significantly reduces the complexity of the whole clock recovery loop.

The application discloses a signal trigger output method and device, and the method comprises the following steps: acquiring a current edge phase value of a first trigger signal; judging whether the current edge phase value of the first trigger signal is stable; calculating a dynamic phase decision threshold which makes the stable edge phase value of the first trigger signal between phase decision thresholds according to the stable edge phase value of the first trigger signal; acquiring a real-time edge phase value of the first trigger signal, and judging whether the real-time edge phase value is between the dynamic phase decision thresholds; if the real-time edge phase value is between the dynamic phase decision thresholds, the real-time edge phase value is taken as a trigger phase value of waveform generation to control predetermined waveform generation. By adjusting the phase decision threshold to make the edge phase value of the first trigger signal between the phase decision thresholds according to the stable edge phase value of the first trigger signal in the synchronous trigger mode, the jitter of the signal trigger output is greatly reduced.

The invention provides an EMMC host controller clock processing system and method. The method comprises the following steps: generating a frequency division coefficient and configuration output of a high-frequency clock according to input configuration information from a host controller; performing frequency division processing on an input high-frequency clock according to the frequency division coefficient to generate a sampling clock; an input clock from a host controller or an EMMC particle is received, sampling offset is carried out on the input clock according to an enable control signal and a sampling clock, and delay offset is carried out on an output clock generating sampling offset. According to the invention, the reliability of particle data sampling of the host controller and the EMMC is remarkably improved, and support is provided for application of embedded storage equipment.

The invention discloses a low-frequency kiloampere pulse current generator which is characterized by comprising a first working power supply, a second working power supply, a pulse generator and N isolation driver amplification units, wherein the first working power supply is respectively connected with one end of the pulse generator and a first power input end of each isolation driver amplification unit; the other end of the pulse generator is connected with the signal input end of each isolation driver amplification unit; the second working power supply is connected with the second power input end of each isolation driver amplification unit; n is a positive integer. Good test adaptability can be provided for pulse loads such as a TR assembly, and the defect that standard load equipment in the market cannot simulate the instantaneous pulse current is overcome.

The application discloses a method for generating an IRIG-B direct current code synchronous second pulse front edge based on a single-chip microcomputer. max The application can realize the same second pulse 1PPS precision by using a domestic single-chip microcomputer, does not need to use a separate FPGA, and greatly reduces the cost. When the first N max code symbols are received, a timer TIMER2 is enabled to start counting. When the counting value of the timer TIMER2 reaches a maximum value, an overflow interrupt is entered, and the timer TIMER3 is configured as a single pulse mode and enabled after the timer TIMER2 enters the overflow interrupt. After the timer TIMER3 is triggered, a signal second pulse 1PPS output by the timer TIMER3 is synchronized with the rising edge of the frame start code symbol of the next frame after a fixed delay Δ and a programmable delay Delay.

The utility model discloses a kind of determination circuits of output power of flyback topology structure, comprising: the detection end of synchronous rectification mos pipe SR end is connected to resistance R1 low end, parallel resistance R2 between detection end and resistance R1, detection end includes diode D1 and bias voltage source V B Diode clamping circuit composed of diode D1 and diode D2, triode Q1 and triode Q2 compose low-connection current mirror, triode Q2 connects dynamic voltage;Low-connection current mirror delivers detection current mirror image to resistance R3;Voltage comparator T1 is based on detection current and resistance R3 output detection signal, rising edge counter J1 determines the rising edge frequency of detection signal, output determination result. Thus, only need to add a resistance on existing drive circuit, can be compared by voltage comparator output detection signal containing rising edge and falling edge, according to this determination switching frequency, realize load determination, device demand is greatly reduced, and detection accuracy is greatly improved.

The invention discloses a high-reliability pulse trigger circuit for radiation field measurement, and solves the problems that an existing pulse trigger circuit is easy to generate false trigger operation, cannot dynamically adjust and lock time parameters on the premise of not changing hardware configuration, and is weak in reliability and poor in flexibility. The circuit specifically comprises a comparison circuit, a self-locking circuit, a narrow pulse generation circuit and a switching circuit. The in-phase input end of the comparison circuit is used for being connected with external analog signal output equipment, the inverted input end of the comparison circuit is used for being connected with an external threshold voltage power supply Vth, and the output end of the comparison circuit is connected with the B input end of the self-locking circuit; the Q1 output end of the self-locking circuit is connected with the A input end of the self-locking circuit and is used for signal closed-loop feedback; the Y output end of the self-locking circuit is connected with the input end of the narrow pulse generation circuit; the narrow pulse generation circuit is used for generating a narrow pulse trigger signal according to the trigger pulse, and the output end is connected with the input end of the switching circuit; the switching circuit is used for outputting a fast pulse trigger signal.

The application relates to the technical field of signal measurement circuits, and discloses a high-speed signal measurement system which comprises a signal trigger module, a capacitor charging module, a threshold comparison and trigger module and a counting module; the signal trigger module provides a stable substrate drain current source IDB for the capacitor charging module; the capacitor charging module outputs a capacitor voltage Vout; the capacitor voltage Vout provides a real-time conduction signal for the threshold comparison and trigger module; the threshold comparison and trigger module converts voltage variation of the capacitor voltage Vout into an effective trigger signal, and sends a trigger instruction to the counting module; the field effect transistor Q1 of the signal trigger module utilizes the high-speed conduction characteristic of FET, combines the substrate drain current source IDB, and provides a stable high-speed current for the capacitor C charging module, so that signal delay is greatly reduced, high-speed signal response speed and measurement precision are improved, errors caused by delay and parameter instability are reduced, the circuit structure is simplified, the cost and power consumption of the circuit are reduced, and high-precision measurement is maintained.