327results about How to "Shorten test time" patented technology

Disclosed is a semiconductor-memory device comprising a selector for performing switching control such that in the standby state the refresh operation is performed responsive to an external-refresh-execution command supplied from outside the semiconductor-memory device, while in the active state, the refresh operation is performed, not under the control from outside the semiconductor-memory device, but under the control from a built-in timer.

The present invention relates to a large scale integrated circuit test data compression method of multiple scanning chains. It is characterized by that it utilizes restricted input compaction to make width compression, and utilizes LFSR and folding counter codification to make two-dimensional compression.

The invention discloses a rapid detection method for the battery life. The rapid detection method for the battery life comprises the steps that firstly, the maximum available capacity of a battery is rapidly estimated on the basis of a partial discharge method; secondly, the capacity retention rate is acquired through the maximum available capacity; finally, the residual cycle life, represented in a cycle index mode, of the battery is estimated according to the current capacity retention rate and the known rated cycle life of the battery. It is clear that the maximum available capacity is selected as a key performance parameter, degradation track modeling is conducted on the maximum available capacity of the battery on the basis of a performance degradation method, and then prediction of the residual cycle life of the lead-acid battery is achieved. In addition, the maximum available capacity of the battery is estimated on the basis of the partial discharge method, so that rapid prediction of the residual cycle life of the battery is achieved. Due to the fact that whole-process discharge operation does not need to be conducted, the test time is greatly shortened, the accuracy can be satisfactory on the premise that the discharge rule of the battery is grasped, and the rapid detection method for the battery life has the high application value in the fields of military, energy sources and traffic.

The invention provides a crystal plate, a testing system, a testing method and a testing device thereof. The invention utilizes a first group probe to carry out high voltage stress test on a first chip and utilizes a second group probe to carry out function test on a second chip; wherein, the high voltage stress test and the function test are carried out simultaneously, thus greatly reducing the testing time of the crystal plate.

Using heater and control unit carries out constant heating for wall body to be tested by using plane heat source in ordinary power so as to form a local steady even heat flow in area to be measured. Thus, wall body is tested under manmade steady heat transfer state. Then, temperatures inside and outside wall, heat-flow density and ambient air temperature is itinerant connected. The said heat-flow density is heat-flow density passing through external surface of wall from inside wall to outside wall in area to be tested. Then, comparison and analysis are carried out between the collected data and sample database of heat transfer coefficient of wall body stored in computer and built in advance so as to obtain heat transfer coefficient of wall body finally. Advantages are: preventing influences from surrounding weather, and heat storage and emission of wall body self, good adaptability to climatic environment, short test time, high precision, low cost etc. The invention is suitable to southward with low difference in temperature between indoor and outdoor.

The application relates to wireless networks and more particularly to a method of reducing factory test time of receiver sensitivity in a Code Division Multiple Access (CDMA) wireless device. Under TIA/EIA/-98E, the radio frequency (RF) sensitivity of a CDMA wireless receiver is the minimum received power, measured at the mobile station antenna connector, at which the frame error rate (FER) does not exceed 0.5% with 95% confidence. In order to reduce the test time of FER test method, the relation between correlated energy (or Ec/Io) and FER is determined using simulated traffic and the correlated energy (or Ec/Io) measurement is then used as the test parameter on like models to achieve the same or superior test confidence with significantly reduced test time.

The invention discloses a method for evaluating the service life and safety of lithium secondary batteries, belongs to the field of secondary batteries and more particularly relates to a rapid evaluation method for lithium secondary batteries. In the method, a lithium secondary battery is first charged and discharged cyclically with the multiplying power more than 3C to test the cycle life; after the circulation, the battery goes through safety test and safety evaluation, thus the cycle life and the safety of the lithium secondary battery after cycle use can be acquired fast. The invention can fast and effectively judge the cycle life and the safety of the lithium secondary battery after cycle, has great effect on guaranteeing the life and safety of batteries and can decrease the time of warehousing waiting time cycle life test of batteries and safety performance test after the cycle.

The invention discloses a novel heating device of an apparent heat transfer coefficient field detection system for a wall body enclosure structure. The novel heating device mainly comprises a heat homogenizing plate, a flexible electric heating coil layer, an outer heat-isolation material layer, an inner heat-isolation material layer, an electric power adjuster and the like, wherein the heat homogenizing plate is tightly pressed against the surface of a wall body to be detected and can be used for uniformly heating the wall body. The periphery of the heat homogenizing plate is provided with the inner heat-isolation material layer which is located between a wall face and the heat homogenizing plate. The flexible electric heating coil layer is arranged on the back face of the heat homogenizing plate. The external heat-isolation material layer is arranged on the back face of the flexible electric heating coil layer so as to prevent the heat produced by the heating coil from being lost at the back of the coil in an isolation manner. The novel heating device is suitable for heating in the field detection of the apparent heat transfer coefficient of the wall body enclosure structure, is light in total weight, easy to regulate in electric heating power, rapid to assemble and disassemble and suitable for carrying, and the number of the heat homogenizing plates can be increased or decreased according to the actual dimension of the wall body in a detection field.

The invention relates to an erosion corrosion test device of a seawater piping system metal member, comprising a fluoroplastic centrifugal pump and a water storage tank, wherein the inner side wall of the water storage tank is provided with a cooling system; the inlet of the fluoroplastic centrifugal pump is connected with the water storage tank, and the outlet main line of the fluoroplastic centrifugal pump is connected with a plurality of parallel-connected working pipelines; each working pipeline is sequentially connected in series with a flow regulating valve, a vortex street flowmeter and a working pipe section; the outlet ends of the plurality of parallel-connected working pipelines are communicated with the water storage tank through loops; the outlet main line of the fluoroplastic centrifugal pump is also provided with a by-pass; the by-pass is communicated to the water storage tank; and the working pipe section is also electrically connected with an electrochemical test device. The erosion corrosion test device can realize the erosion corrosion resistant property tests of different pipe samples under approximately completely consistent test conditions of a same medium, same temperature, same flow velocity, and the like and can also be used for researching the erosion corrosion resistant property of a same material under the conditions of different mediums and flow velocities.

The invention discloses a test instrument sharing usage method and a test system in an automatic optical module test. The system comprises a plurality of testing machine platforms, optical modules to be tested, optical module testing instruments, servers, switchboards and optical switches, wherein the testing machine platforms are connected with the switchboards, the switchboards are connected with the servers, the servers are connected with all the optical module testing instruments, and the optical module testing instruments are with the optical modules to be tested which are arranged on the testing machine platforms through the optical switches. Control is achieved through servers, when a testing machine platform requires an optical module testing instrument, the testing machine platform applies for resources of the instrument for a server, when the instrument idles, the server distributes the resources of the instrument to the testing machine platform, at the same time, the instrument is remarked to be occupied until the testing machine platform releases the usage of the platform, and if one instrument is occupied by one of the testing machine platforms , the other testing machine platform can apply for the usage of other instruments. According to the method and the system, by the aid of the server, testing resources are coordinated, a plurality of optical modules can be detected, and the utilization rate of the instruments can be improved.

The invention discloses a rigid body mode testing method for a powertrain mounting system under the loading condition. In the method, a heavy object is hung on a powertrain mounting device under the loading condition; and a rope for hanging the heavy object is cut to suddenly release the force acted on the powertrain mounting device so as to excite the free vibration of the powertrain mounting device and immediately trigger a data acquisition unit to record and store the data on a vibration transducer at the moment. A rigid body mode of the mounting system is tested by the method and the obtained each-order natural frequency and decoupling rate are the actual and real natural frequency and decoupling rate of a tested vehicle, so that the method tests the performance of the vehicle most directly, really and reliably. The testing method can be performed on any entire vehicle, only a proper number of heavy objects is needed, and the design and processing of a test bench are avoided, so that the testing cost is basically avoided. Obviously, the testing time and the testing cost are greatly saved.

The invention discloses a classification method of chip bin maps in wafer circuit probing. The method includes the steps that specified chips needing to be marked as fail bins are obtained according to a wafer acceptance test, and the coordinates of the specified chips are recorded in a configuration file; step-by-step testing is carried out on a wafer, information of all the specified chips is judged before touch down of the current test step is carried out, and specified chips located in a touch down area are excluded out of test objects; the chip bin map of the current test step is printed, and the state of the corresponding specified chip is printed as the fail bin; a chip bin map of the whole wafer is generated on the basis of the chip bin maps obtained in all the test steps. By means of the method, test time can be effectively shortened, test hardware can be effectively protected, a process flow can be simplified, error probability can be effectively reduced, and work efficiency can be effectively improved.

The invention provides a wireless interference test method and system. The wireless interference test method achieves an adjustable interference test aiming at a LTE-V2X communication link in the anechoic chamber environment, comprising the following steps: establishing a wireless interference test system including a transmitting unit, an anechoic chamber, a receiving unit and an interference unitfirst; and establishing communication links between each device in the wireless interference test system to realize the semi-object simulation interference test in the anechoic chamber environment. When performing the wireless interference test, the simulation test of the true channels of different scenes in the frequency band is performed by setting different parameters of a first channel simulator in the transmission unit, therefore, the problem that more manpower and time cost are required in the general outfield test is solved, and the efficiency and effectiveness of the test are greatlyimproved. In addition, a second channel simulator is configured for the interference sources, therefore, the real interference signal characteristics in a non-used scene can be simulated, and the accurate and parameter adjustable interference source signal is realized.

The invention provides a board test method and device. The method includes allowing a Linux operating system kernel module to run on a board, allowing a core process module to run in the Linux operating system kernel module, allowing the core process module to read firmware information of the board, reading and running a test case according to configuration information in the firmware information, allowing the test case to return test results to the core process module, and allowing the core process module to output the test results. The device comprises the Linux operating system kernel module, the core process module, a test case database and an output module. The core process module runs in the Linux operating system kernel module and reads the firmware information of the board. The test case database includes a plurality of test cases and is used for selecting and running the test cases by the core process module. The output module is used for outputting the test results received by the core process module and returned by the test cases. The board test method and device has the advantages that test time of boards is shorter and test efficiency of boards is higher.

The invention relates to a method for testing the service life of NMOS hot carrier injection, which comprises the following steps that: 1, a test system applies a test voltage stress to a drain electrode of a tested apparatus, wherein the value of the test voltage accounts for 60 and 70 percent of value of a punch through voltage; 2, a grid voltage corresponding to a maximum substrate current when the voltage stress is applied to the drain electrode is a grid voltage stress, and the grid voltage stress is accessed to obtain a degradation picture of a drain electrode current of the tested apparatus; and 3, the test system fits data obtained by the step 2 to obtain a failure time of the tested apparatus, and when the apparatus is degraded to over 5 percent, the failure time of the apparatus is obtained through heterodyne calculation and then the service life of hot carrier injection is calculated by using a formula, namely TTF*Ids=C*(Isub/Ids)m. Through the technical scheme of the invention, the service life of the NMOS hot carrier injection can be quickly obtained so as to greatly shorten the test time and save the cost without packaging a chip.

The apparatus comprises: a RF instrument used for testing the terminal. Said terminal comprises two RF ports and a RF switch; one end of the RF switch is connected to the one of two RF ports; the other end of the RF switch is connected to the RF instrument. The invention used for realizing the automatic switchover between the calibration testing channels when making a calibration test of two systems.

The invention provides a Beidou equipment inter-module electromagnetic interference test method. When a Beidou module is taken as an interfering source, the intensity of electromagnetic interference to a tested module on each channel is tested; and when the Beidou module is taken as an interfered source, the intensity of electromagnetic interference of each channel of an interfering source to the Beidou module is tested. In interference test, the error probability or positioning failure probability is used to replace total omnidirectional sensitivity test to reduce the test time, and a total omnidirectional sensitivity result under the condition of the highest degree of being interfered is obtained through measurement to reflect the degree of electromagnetic interference to Beidou equipment in a multi-mode concurrent state. The problem that there is no standard for reference as to the methods for testing the interference between a wireless module and a Beidou module of terminal equipment with Beidou navigation and positioning functions is solved.

The invention discloses a testing device and method for a digital semiconductor device; the testing device comprises a time series generator module, an algorithm vector generator module, a programmable data selector module and a testing module, wherein the testing module comprises a logic testing module, a waveform format controller module, a base pin circuit module and a digital comparing module; the logic testing module receives a main clock signal and a first testing vector and simultaneously sends a second testing vector to the waveform format controller module; the first testing vector is transmitted to the logic testing module and is stored before testing begins; and when testing begins, the logic testing module selects the stored first testing vector, forms and transmits the second testing vector to the waveform format controller module. The testing device intensifies the functions of a tester of the traditional memory so that the tester not only has the powerful testing function of the traditional memory, but also has the testing capability of a complex logic device; and simultaneously the very strong simultaneous testing capability of the tester is beyond that of the traditional logic tester, thereby effectively reducing the testing cost and saving the testing time.

A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt.

A test table consists of control device, display device and operation devie. It is featured as integrating vacuum pumping device, oiling device, nitrogen filling device, running device and various performance detecting device together for automaticallyc arrying out performance tests for air-conditioning compressor of automobile under unified control of PLC; having on-line display of test state and making acousto-optic alarm for abnormals.

The invention provides a self-detection mending method for a built-in self-test system. The self-detection mending method comprises the following steps: inputting expected data into a memory storage array according to a gradually increased sequence of addresses; optimizing the built-in self-test system, wherein the built-in self-test system records a start address of the memory storage array and reads the data stored in the memory storage array according to an input mode; sequentially comparing each bit data of the stored data which is read according to the address with each bit data of the expected data in the built-in self-test system, which is pre-stored by taking the number of bytes corresponding to the addresses as a unit according to the input mode, and sequentially outputting a comparison result of each address; and when the comparison results indicate that the contents are inconsistent, determining that the stored data of the storage array, which corresponds to the comparison results, is an ineffective address, and mending the stored data of the ineffective address by a redundant array. According to the self-detection mending method, the ineffective address of a memory can be quickly judged, and the current ineffective address of the memory can be mended by the redundant array, so that the test time is shortened.

The invention discloses a loudspeaker T/S parameter testing method and testing device. Through arrangement of the testing device with a sealing function, the electro-acoustic parameter group of a loudspeaker before sealing and the impedance curve of the loudspeaker after sealing are tested separately, then the characteristic parameters of the electro-acoustic parameter group and the impedance curve of the loudspeaker after sealing are extracted separately, and the T/S parameter of the loudspeaker is calculated according to a standard formula of acoustic system equipment, so that a single loudspeaker or a loudspeaker module can be quickly tested online to obtain the T/S parameter without damaging the loudspeaker. The testing time is shortened, and the efficiency is improved.

The invention provides a wireless interference test method and system. The wireless interference test method that is used for carrying out semi-physical simulation interference testing in an anechoicchamber environment comprises: a wireless interference test system including a transmitting unit, an anechoic chamber, a receiving unit, and an interference device is established and communication links between all devices in the wireless interference test system are established; and when wireless interference testing is carried out, different parameters of a channel simulator in the transmittingunit are set to simulate real channels of different scenes in the test frequency band. Therefore, problems of lots of manpower and time costs for common outer field testing are solved, so that the testing efficiency and effectiveness are improved substantially. Moreover, because the outer field test interference source has attenuation and declining problems and an interference signal arriving at the under-interference device can not be quantified easily, interference sources with different frequency bands are added by a standard antenna in the anechoic chamber, so that the testing time is shortened effectively and the testing accuracy and reproducibility are improved.

Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

The invention discloses an audio test method for an earphone microphone and a speaker of a mobile terminal. The method comprises that an audio test device sends test audio signals to the mobile terminal by measuring earpieces; the mobile terminal receives the test audio signals through an earphone microphone interface and generates audio signals according to the test audio signals; the speaker of the mobile terminal plays the audio signals; and the audio test device receives the audio signals generated by the mobile terminal and tests an audio channel of the mobile terminal according to the audio signals and the test audio signals. The invention further discloses an audio test system for the earphone microphone and the speaker of the mobile terminal. By means of the audio test method and the system for the earphone microphone and the speaker of the mobile terminal, an input channel of the earphone microphone and an output channel of the speaker of the mobile terminal can be tested; and test time is short, and the test cost is low.

The invention discloses a method to take multi-chip parallel testing by using synchronous communication chip. It includes the following steps: connecting plural chips on silicon slice by shift register, outputting the testing signal to tested chips by the method of series to parallel, inputting the output data to I/O pins of tester from plural chips by the method of parallel to series, and reading the data and taking data process to gain the PASS/FAIL result of the chips. The invention could improve testing efficiency of testing chip and lower testing time and cost.

The invention discloses a method and device for testing software, and belongs to the field of Internet communications. The method comprises the steps that test cases corresponding to all interfaces respectively are generated according to a test case template and interface information, included in the software, of all the interfaces; the generated test cases run in parallel through a plurality of test virtual machines, and the running result of each test case is obtained; whether security holes exist in the software or not is determined according to the running result of each test case. The device comprises a generating module, a running module and a determining module. According to the method and device, the test time spent in testing the software can be shortened, and the testing efficiency of testing the software can be improved.

The invention relates to a test optimization method of an integrated circuit wafer, and is applied to a test process of the integrated circuit wafer. The method includes: designating a die coordinatein need of a test on the wafer in advance and storing the coordinate in a test system, then testing the pre-designated die according to a design pattern in a test process and adjusting the range of the pre-designated coordinate in real time according to a current die test result, and finally obtaining a required test coordinate pattern to cover the most invalid die quantity with a most optimized scheme so that the test time is reduced, the test efficiency is improved, the usage frequency of test hardware is reduced, and the service lifetime is prolonged. According to the method, through propercoverage quantity calculation, a small quantity of FAIL chips flowing to package are obtained, and the packaging cost is not increased; besides, the test frequency of a probe card is reduced, and theservice lifetime of the hardware is prolonged.

The invention relates to a tabu search and artificial potential field method combined online digital micro-fluidic chip test method, belongs to the field of digital micro-fluidic chip fault test, and aims at solving the problem that the practical application range is narrow as most of the existing online test methods aim at the customized digital micro-fluidic chips with special electrode layout. Aiming at digital micro-fluidic chips with regular rectangular electrode layout, the invention discloses the tabu search and artificial potential field method combined online digital micro-fluidic chip test method, and the method comprises the following steps of: establishing a mathematic model for online test of the digital micro-fluidic chips; constructing an abutment list; setting initial parameters; calculating the value of resultant force sugared from each node in a selectable neighborhood of the current node, and selecting the next node according to the value of resultant force and a tabu table; updating the tabu table; judging whether a path is integral or not; and judging whether the number of iterations achieves a preset value. The method provided by the invention is suitable for the online test path optimization problems of the digital micro-fluidic chips.

The invention provides an automatic detection system for a laser level meter. The automatic detection system for the laser level meter comprises a vertical detection station, wherein the vertical detection station is used for detecting a vertical laser line, and the station is provided with a pentaprism for deflecting the vertical laser line to a horizontal laser line; a horizontal detection station, wherein the horizontal detection station is used for detecting the horizontal laser line; an optical collimator, wherein the optical collimator is internally provided with an objective lens and areticle, the position of the objective lens is opposite to the position of the reticle, and the laser line is projected to the reticle after passing through the objective lens; a camera, wherein the camera is used for collecting a laser image on the reticle; and a computer, wherein the camera is connected with the computer, the computer is used for analyzing and calculating the image collected bythe camera. The technical scheme is capable of automatically and accurately measuring angles of the vertical and horizontal laser lines emitted by the laser level meter, greatly shortening the testingtime, improving the efficiency, realizing the measurement to the vertical laser line and the horizontal laser line by a set of the optical collimator and the camera, reducing the cost, and decreasingthe spatial arrangement of a detection device.