98 results about "Through-silicon via" patented technology

This application discloses a method and electronic device for detecting transmission parameters of through-silicon vias (TSVs), applied in the field of integrated circuit technology. The method includes: determining whether the total length of the TSV to be tested is greater than a preset first length; if so, dividing the TSV into multiple via segments such that the length of each segment is no greater than the first length; if not, treating the TSV as a TSV composed of single-segment vias; for each via segment, obtaining the pad capacitance, via pillar capacitance, anti-pad capacitance, via inductance, and via resistance of the via segment using preset parameter calculation rules, and constructing an equivalent circuit model of the via segment; cascading the equivalent circuit models of each via segment of the TSV to form an equivalent circuit model of the TSV, and performing transmission parameter detection on the TSV. Applying the scheme of this application can effectively determine the transmission parameters of the TSV, improving efficiency and ensuring the accuracy of the scheme.

The application discloses a kind of through superimposed photoresist layer the method for manufacturing wafer level packaging product, and the application belongs to wafer level packaging field, including step one: preparation glass wafer, release layer and sputtering layer are coated on the glass wafer top;Step two: the first heavy wiring layer is formed on the sputtering layer top;Step three: metal seed layer is set on the first heavy wiring layer top;Step four: photoresist is coated on the first heavy wiring layer top to form photoresist one;Step five: the photoresist one is carried out alignment exposure operation to photoresist one by mask one;Step six: photoresist one is developed to form opening structure one.The application utilizes the way of high tackiness wet film photoresist to manufacture silicon through hole bump, can solve the technical problem of silicon through hole bump preparation in advanced packaging field, effectively improve the product quality and production yield of chip, suitable for advanced packaging silicon through hole bump whole process preparation link.

A compute device comprising includes volatile memory (VM) dies stacked with a non-volatile memory (NVM) die and a logic die having control logic. A first plurality of through-silicon vias (TSVs) are formed through the one or more VM dies and the NVM die. In embodiments, the first plurality of TSVs are intercoupled through a plurality of microbumps. The control logic writes data to and reading data from the one or more VM dies through a first subset of the first plurality of TSVs. The control logic folds the data from the one or more VM dies to the NVM die through a second subset of the first plurality of TSVs that are fewer than the first subset and are dedicated to the folding of the data.

A semiconductor die includes manually designed full-custom logic circuits implemented at transistor level and performing digital computation without use of standard-cell libraries or automated synthesis. The die lacks bond pads, wire-bond terminals, or through-silicon vias and operates only when bonded to another die or carrier through dense hybrid-bonded or microbump conductive interconnects. In related embodiments, a system includes such a compute die and a peripheral die providing power, clock, and communication functions. The architecture enables pad-less full-custom compute dies operating solely through inter-die bonding for all external connectivity.

Stacked storage device (1000) comprising: a logic semiconductor die (1010); a plurality of storage semiconductors die (1070, 1080; 1100, 1200, 1300, 1400) stacked with the logic semiconductor die (1010), each of the storage semiconductors die (1070, 1080; 1100, 1200, 1300, 1400) comprising an integrated memory circuit (1071, 1081; 1401, 1402) and one or more of the storage semiconductors die (1070, 1080; 1100, 1200, 1300, 1400) comprising a computational semiconductor die (1080; 1400) comprising a computational unit (CU, CU1~CUn); and silicon vias (TSV) which electrically connect the logic semiconductor die (1010) and the majority of memory semiconductor dies (1070, 1080; 1100, 1200, 1300, 1400);wherein each of the computation units (CU, CU1~CUn) is configured to perform calculations based on transmitted data (DA) and internal data (DW1~DWn) and to generate computation result data (DR), wherein the transmitted data (DA) is provided jointly for the computation semiconductor dies (1080; 1400) through the silicon vias (TSV) and the internal data (DW1~DWn) is read from the integrated memory circuits (1071, 1081; 1401, 1402) of the computation semiconductor dies (1080; 1400).

The application provides a kind of core particle interconnection structure defect detection method based on physical level decomposition, comprising: obtaining the layout data and connection relationship data of through silicon via and micro-bump level;Form respective independent feature set according to physical space coordinates decomposition;Identify the vertical signal interruption feature of through silicon via and the poor contact feature of micro-bump;Establish physical connection topology graph, and the features existing spatial adjacent or electrical coupling relationship are connected after the above-mentioned features are labeled to generate correlation graph;Iterate the chain path, and mark the first defect feature node as defect source point;According to the level to which the source point belongs, select test signal injection and collect downstream response;Compare response with standard reference point by point, extract difference feature to determine the chain reaction extension range;Output the detection result containing defect level, position and influence range.The application can distinguish different physical level failure features and track chain reaction, realize the accurate identification of defect root and range.

A wafer-scale compute system integrates multiple semiconductor stacks on a monolithic passive silicon substrate patterned into mechanically isolated silicon islands interconnected through through-silicon vias and redistribution wiring layers. Etched silicon spring structures provide in-plane and out-of-plane compliance, enabling wafer-scale assembly without mechanical stress. The substrate includes redundant wiring and multiple regulated power domains supplied by vertical modules. All communication between stacks occurs through the silicon substrate, forming a contiguous all-silicon computational domain with no organic circuit boards or interposers. The architecture delivers zetta-scale performance with high yield and mechanical reliability.

This invention discloses a method and apparatus for measuring the depth of through-silicon vias (TSVs) based on a front-mounted objective reference module. The method includes: S1: Light emitted from a light source unit sequentially passes through a tube lens, objective lens, and beam splitter / combiner element before illuminating a non-hole region of a sample with a TSV. A spectral acquisition unit receives the returned light, obtains the interference spectrum signal, and processes it to obtain the system bias optical path characteristic corresponding to the round-trip optical path difference between the reference reflector and the non-hole region; S2: The sample is moved so that the light source unit is positioned on the TSV as described above, and the system bias optical path characteristic corresponding to the round-trip optical path difference between the reference reflector and the bottom of the TSV is obtained; S3: The physical depth of the TSV is calculated; S4: Anomalies occurring in steps S1 and S2 are handled. This method features high stability and a high signal-to-noise ratio, which helps promote the large-scale use of high-precision TSV measurement equipment in complex production line environments.

Techniques for mitigating capacitive coupling effects associated with electrical paths extending through a stack of multiple dies. The multiple dies include a memory structure having non-volatile memory cells (such as NAND). The multiple dies may also include control circuitry that performs die-level control of the non-volatile memory cells. The control circuitry may be formed on a semiconductor substrate (such as a crystalline silicon substrate). The electrical paths may extend through the stack of dies. The electrical paths may include through-silicon vias (TSVs) extending through the crystalline semiconductor substrate, and the control circuitry is formed in the crystalline semiconductor substrate.

The application provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first insulating medium layer on the substrate; forming a through-silicon via and a contact plug; wherein, before etching a via for forming the through-silicon via and / or a contact hole for forming the contact plug, an intermediate medium layer is formed on the first insulating medium layer; a sacrificial structure is formed in the via or the contact hole before the via or the contact hole is filled with a conductive material, and the intermediate medium layer and the sacrificial structure are sequentially removed; forming a metal layer; wherein, the through-silicon via and the contact plug are both in contact with the metal layer; the height difference between the top surface of the through-silicon via and the top surface of the contact plug in a first direction is less than the thickness of the metal layer in the first direction.

A compute device includes one or more volatile memory (VM) dies and a non-volatile memory (NVM) die, stacked with the VM dies. The NVM die includes a wide-bit input / output (I / O) interface. Through-silicon vias (TSVs) are formed through the VM dies and the NVM die and interconnected through microbumps. A logic die is stacked with the VM dies and the NVM die. The wide-bit I / O interface is configured to handle data transfers over the TSVs to and from the VM dies, through the logic die, at one of a data rate of the VM dies or at a reduced rate compared to the data rate of the VM dies.

1. The name of the design product: FemtoX LAB. 2. The use of the design product: It is a laser direct writing equipment, mainly used for processing brittle materials, such as the development and production of glass three-dimensional optical waveguide, glass via, silicon via, etc. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view 1.

This invention belongs to the technical field of chip design and fabrication, and discloses a horizontally driven MEMS micromirror structure, comprising a substrate layer, a driving layer, a support layer, and a mirror layer bonded together from bottom to top. The substrate layer has through-silicon vias (TSVs) for electrical isolation and partitioning. The driving layer uses a single photolithography / etching process to fabricate paired fixed and movable driving electrodes, forming a horizontal electrostatic driving structure unit that converts horizontal displacement into deflection power for the driving center area. The support layer has a gimbal-type deflection structure and a cavity, providing levers, fulcrums, and space for mirror deflection, while also protecting the driving structure. The mirror layer is linked to the support layer via a bonding structure to achieve precise mirror deflection. This invention improves electrode alignment accuracy, reduces driving voltage and power consumption, provides a large mirror deflection angle, and exhibits high structural reliability and integration, significantly reducing the assembly and debugging costs of optical communication modules. It can be widely applied in 3D optical imaging scanning, LiDAR, optical communication, and other fields.

Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. The multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.

An apparatus for the high-bandwidth memory is disclosed. The Apparatus comprises; a plurality of high-bandwidth memory dies; a plurality of TSVs (Through-Silicon Via) each corresponding one-to-one with the high-bandwidth memory dies; a memory control module connected to the plurality of TSVs; a test module configured to detect defects in the high-bandwidth memory dies and TSVs; and a non-volatile memory configured to store defect location information of at least one faulty high-bandwidth memory die and at least one faulty TSV detected by the test module. The memory control module is configured to set the TSVs based on the fault location information stored in the non-volatile memory, thereby minimizing the complexity of path configuration even in cases where faulty high-bandwidth memory dies and their corresponding TSVs exist, enabling efficient handling of clustered faults, and maintaining the performance of clock synchronization.

The application provides a semiconductor structure and a forming method thereof, wherein a first through silicon via structure is formed through two processes of front side processing and back side processing, and a second through silicon via structure is formed through one process of front side processing; since the first through silicon via structure is formed through two processes, the critical dimension and the depth adjustment range of the first through silicon via structure are large, so that the first through silicon via structure can be designed to have a small critical dimension, and the critical dimension is reduced; in addition, the first through silicon via structure and the second through silicon via structure are connected with back-end metal interconnections located on different planes, so that the process window of the back-end metal wiring is increased.

Embodiments disclosed herein include arrangements enabling extraction of bandwidth with multiple channels. In an example, a memory structure includes a package substrate. A base die is coupled to the package substrate and a memory die stack is coupled to the base die, or a memory die stack is coupled to the package substrate. A same number of through silicon vias span all memory dies in the die stack.

The present application relates to laser processing technology and precision cutting technology field, concretely is a kind of water jet assisted laser and mechanical compound drilling method and device, including the following steps: S1, the silicon carbide material to be processed is clamped and fixed above the infrared coaxial alignment sensor of device guide rail platform, after laser lens calibration focal length, water jet device is opened, and the controller receives the transmittance change of the infrared light beam emitted by the infrared coaxial alignment sensor in the processing process through signal receiving unit to determine the processing termination opportunity by bringing into penetration determination formula;S2, after pre-processing, switching position is carried out through device guide rail platform, and the coaxial calibration of pre-hole and PCD drill bit is completed by means of infrared coaxial alignment sensor;S3, after calibration, PCD drill bit is driven by drilling device according to pre-set parameter, and pre-hole is processed by pecking drill type sizing and reaming, and high-quality silicon carbide through-hole meeting the requirements of size and precision is obtained.

A compute device comprising includes volatile memory (VM) dies stacked with a non-volatile memory (NVM) die and a logic die having control logic. A first plurality of through-silicon vias (TSVs) are formed through the one or more VM dies and the NVM die. In embodiments, the first plurality of TSVs are intercoupled through a plurality of microbumps. The control logic writes data to and reading data from the one or more VM dies through a first subset of the first plurality of TSVs. The control logic folds the data from the one or more VM dies to the NVM die through a second subset of the first plurality of TSVs that are fewer than the first subset and are dedicated to the folding of the data.

The present application relates to the technical field of three-dimensional integrated circuit protection in aerospace radiation environment, and particularly relates to a method and system for simulating and modeling a microsystem interconnection module based on a through silicon via under proton irradiation. The method comprises: constructing a three-dimensional finite element model containing a through silicon via, a redistribution layer and a micro-bump, adjusting material parameters to extract scattering parameters, and establishing a correlation model between material characteristics and scattering parameters; constructing an equivalent RLC circuit in an ADS environment and establishing a corresponding relationship between the equivalent RLC circuit and the scattering parameters; combining a proton irradiation experiment to obtain scattering parameters under different radiation fluences, and further establishing a correlation model between the radiation fluence and the RLC circuit parameters. The present application combines simulation and experimental methods to achieve precise modeling between the radiation dose, the circuit parameters and the scattering characteristics, and provides support for the electrical performance prediction and protection design of three-dimensional microsystems in complex radiation environments.

The present application relates to the technical field of semiconductor integrated circuits, and particularly relates to a method for realizing steep and high-uniformity dielectric etching based on high-purity octafluorocyclobutane and application thereof. The method for dielectric etching of the present application prepares a patterned mask on the surface of a dielectric layer material to be etched through an electron beam lithography process; etches the dielectric layer material covered with the patterned mask using plasma formed from an etching gas to realize a vertical etching groove with a width of 20 nm to 150 nm; and the etching gas comprises high-purity octafluorocyclobutane gas with a purity of more than 99.99999%. The method for dielectric etching of the present application takes advantage of the high purity of high-purity octafluorocyclobutane gas, reduces the damage of etching gases such as oxygen and high-fluorocarbon ratio gas to the sidewall etching protection layer, thereby improving the steepness of the sidewall of nanoscale silicon oxide via etching, and simultaneously making the etching process relatively stable under different etching sizes.

The utility model provides a kind of semiconductor packaging structure, the semiconductor packaging structure includes electric connection structure, by being provided with first support structure below photoelectric integrated chip, that is, a support structure of stacked through silicon via connection is provided below relatively thin photoelectric integrated chip, can reduce the risk of rupture of photoelectric integrated chip too thin on the basis of not increasing through silicon via depth, improve its yield and reliability, simultaneously, photoelectric integrated chip can also reduce the stress borne by it.

Systems, apparatus, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. In a three-dimensional integrated circuit, a first semiconductor die has a second die vertically stacked on top of it. The first die includes through-silicon via (TSV) interconnects that do not penetrate the first die. The first die includes one or more metal layers above the TSVs, said one or more metal layers being connected to a bonding pad interface via bonding pad vias. If signals transmitted through the TSVs of the first die are shared by the second die, the second die includes TSVs aligned with the bonding pad interfaces of the first die. If the second die does not share these signals, the second die includes an insulating portion on the wafer backside aligned with the bonding pad interfaces.

This invention discloses a narrow-angle polarization detection integrated chip covering communication frequency bands and its fabrication method, comprising: a top-layer chip, using silicon as a substrate, wherein the silicon has an array of through-holes; an array of through-hole grooves with an insulating layer on the upper surface of the silicon; a multi-dimensional composite metasurface, disposed within the array of through-hole grooves of the insulating layer and in contact with the silicon; silicon through-hole metal connecting pillars, uniformly arrayed within the through-holes of the silicon, and connected to each other through the insulating layer; electrodes, evenly distributed above the insulating layer on the upper surface of the silicon with the array of through-hole grooves of the insulating layer as the center, and in contact with the silicon through-hole metal connecting pillars; and a bottom-layer chip, containing a readout integrated circuit module, connected to the top-layer chip via an indium tin alloy. This invention achieves chip-level ultra-narrow-angle detection, integrates the characteristics of anisotropic trench structures, and expands the detection capability of silicon-based chips across the entire communication frequency band, making it suitable for wafer-level production.

The present disclosure relates to a semiconductor device including a through silicon via structure and a method of manufacturing the same. The semiconductor device can include a via hole, a first electrode, a second electrode, and a first protective insulating layer. The via hole can be formed to penetrate a substrate. The first electrode can include an electrode segment formed on a surface of the via hole. The second electrode can be formed on the first electrode along the surface of the via hole. The second electrode can include two ends placed below the surface of the substrate. The first protective insulating layer can be formed on the second electrode along the surface of the via hole. The first protective insulating layer can include two ends protruding upward from the two ends of the second electrode.

A quantum device including superconducting-semiconducting qubits and coupler designs based on high-quality, compact through-silicon vias (TSVs). An interposer probe wafer containing TSVs is used to contact a sample wafer with, for example, a superconductor-proximitized, epitaxially-grown, germanium quantum well. By utilizing the capacitance of the probe wafer TSVs, the majority of the electric field in the qubits is pulled away from lossy regions that are present in the semiconducting wafer. The probe wafer can reduce the qubit's electric field participation in the sample wafer by an order of magnitude for thin substrates and remains small even when the epitaxial layer thickness approaches 100 μμm. This scheme is extensible to multi-qubit systems that have tunable qubit-qubit couplings without magnetic fields. This approach shrinks the on-chip footprint of voltage-tunable superconducting qubits and is applicable to super-semi heterostructures in a variety of systems.

Three-dimensional heterogeneous integration memory stacks with reduced hybrid bond pad, through-silicon via, and package-level bond pad pitches (and associated systems and methods) are disclosed herein. In one embodiment, a memory stack includes an interface (IF) logic die and a plurality of memory cubes arranged in a vertical stack on the IF logic die. Each memory cube of the plurality of memory cubes includes a plurality of memory dies. The memory stack can further include gapfill material disposed over the IF logic die and laterally adjacent each of the memory cubes. The gapfill material can be further disposed over a topmost die of each memory cube, forming a continuous structure. The memory dies can include through-silicon vias and hybrid bond pads arranged with a pitch of less than or equal to 3 micrometers. The memory stack can be incorporated into a memory system with a logic die on a system substrate.

This invention provides a multi-chip packaging structure and manufacturing method, relating to the semiconductor field, comprising: N laterally arranged chip combinations, where N is an integer greater than 1, each chip combination including two back-to-back stacked chips; an interconnect mechanism including a stacking portion disposed between the chip combinations and a top RDL and a bottom RDL disposed above and below the stacking portion, wherein the top RDL and the bottom RDL are interconnected through the stacking portion, and the chips in each chip combination are bonded to the top RDL and the bottom RDL; a transition plate disposed below the interconnect mechanism; and a substrate disposed below the transition plate and bonded to the transition plate with solder balls. This application, through improvements to the interconnect mechanism and the transition plate, not only avoids the high threshold design of traditional interconnect schemes that require pre-reserved through-silicon vias inside the chips, but also utilizes the top RDL and bottom RDL of the interconnect mechanism, as well as the external stacking portion, to achieve efficient expansion of lateral interconnects between chips.

A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.