576 results about "Through-silicon via" patented technology

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention provides an MEMS (Micro Electro Mechanical System) micromirror array chip, a module and optical scanning equipment. The MEMS micromirror array chip comprises a plurality of micromirror structures, a substrate, a vertical lead structure and a capacitance angle sensing structure, according to the micro-mirror array chip integrated with the capacitive sensor, array-level real-time angle detection, feedback control and high-precision scanning angle detection are realized, and the micro-mirror array chip is fast in driving and resistant to interference; meanwhile, the wiring density is reduced by frequency division multiplexing isolation signals; in addition, the application of a monolithic integrated capacitance angle sensor in a high-density micro-mirror array chip is realized by a thick substrate with a silicon through hole; and finally, the micromirror array chip of the monolithic integrated capacitance angle sensor is used for precision optical scanning equipment, a photoelectric angle detector is omitted, optical scanning high-precision real-time angle detection and feedback control, high-precision angle detection and high-speed scanning are realized, the use design is convenient, and the cost is low.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through-silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

The invention discloses a vehicle gauge chip integrated packaging manufacturing process based on an etching technology. The vehicle gauge chip integrated packaging manufacturing process comprises the following steps: step 1, designing and preparing a substrate; step 2, preprocessing the chip; step 3, chip mounting and interconnection are carried out; step 4, plastic packaging and molding; 5, heat dissipation and reinforcement are carried out; step 6, image rotation correction and defect detection; step 7, performing post-working procedures and testing; high-density interconnection such as TSV (through silicon vias), RDL (redistribution layer) and micro bumps is realized by using an etching technology, the interconnection density is remarkably improved, the RDL wiring layer manufactured by using the etching technology has the line width less than 2 microns, high-density interconnection on the surface of a chip is realized, the integration level is further improved, the micro-channel is manufactured in the plastic package layer by using the etching technology, and the packaging efficiency is improved. And the copper radiating fins are embedded, so that the radiating efficiency is effectively improved, the problem of local heat accumulation caused by integration of the power chip and the logic chip is solved, a gap between the chip and the radiating cover plate is filled with a thermal interface material with high thermal conductivity, and the thermal resistance is reduced.

The present disclosure provides a miniature electrostatic chuck (ESC) for die-to-wafer (D2W) bonding. The ESC can be manufactured using conventional semiconductor processes, incorporating through-silicon-via (TSV) and through-dielectric-via (TDV) structures. The ESC with different sizes can be attached to and detached from a multi-axis robotic arm, allowing optimized D2W bonding processes.

A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.

In an embodiment, a method for fast prediction of hotspot temperatures in three-dimensional (3D) integrated circuit (IC) chips, can involve inputting a dataset comprising thermal simulation data and associated parameters for 3D IC chips, wherein the dataset includes variables such as power distribution, processor core location distribution, and Through Silicon Via (TSV) distribution, applying a K-fold CrossValidation (K-CV) algorithm to train a machine learning model using the inputted dataset, wherein the K-CV algorithm is employed to optimize the training process and prevent overfitting, utilizing a Support Vector Regression (SVR) algorithm within the trained machine learning model to predict hotspot temperatures of the 3D IC chips, and adjusting a cooling strategy for cooling the 3D IC chips, in response to monitoring the hotspot temperatures via the trained machine learning model. The 3D IC chip can include a multi-layer structure including a group of vertically stacked semiconductor layers.

The invention relates to an MEMS-CMOS device vertical interconnection integrated packaging preparation method, which comprises the following steps of: processing a TSV (Through Silicon Via) on a first silicon wafer (3), and filling crystalline silicon (2a); respectively processing a CMOS circuit layer and an RDL layer on the first silicon wafer, and processing a germanium bonding point (8) on the other surface of the first silicon wafer; a second SOI silicon wafer (10) and a third SOI silicon wafer (11) are fused and bonded to form a cavity (9), an aluminum / titanium / aluminum bonding point (12) is prepared on the third silicon wafer, an MEMS movable microstructure (13) is prepared on the third silicon wafer, the metal aluminum / titanium / aluminum bonding point and the MEMS movable microstructure are electrically connected, and the aluminum-germanium bonding point of the first silicon wafer and the aluminum-germanium bonding point of the third silicon wafer are subjected to eutectic bonding. According to the invention, the size of an integrated packaging chip of the MEMS device and the CMOS processing circuit is greatly reduced, and meanwhile, the RDL structure can realize wafer-level bonding packaging without considering the types, layout and size of the MEMS device and the CMOS circuit.

The invention discloses a miniaturized monolithic integration method of a geomagnetic sensor and an MCU (Microprogrammed Control Unit). The method comprises the following steps of (1) low-temperature CMOS circuit layer preparation, (2) TSV three-dimensional interconnection structure processing, (3) magnetic-core-free planar coil manufacturing, (4) low-temperature electromagnetic shielding layer integration and (5) structure release and vacuum packaging. Process conflicts and hysteresis errors introduced by ferromagnetic materials are eliminated through a non-magnetic-core design, a TSV (through silicon via) three-dimensional interconnection technology is adopted to replace traditional plane wiring, the size of the module is compressed to the millimeter level, meanwhile, a broadband electromagnetic shielding layer is integrated, and it is ensured that in a weak magnetic field (lt; and the signal-to-noise ratio in a detection scene is greater than or equal to 30dB. The low-temperature compatibility with a CMOS (complementary metal oxide semiconductor) process can be realized, the mass production feasibility needs to adapt to a standard semiconductor production line, the cost of a single chip is reduced by more than 30%, and the method is suitable for navigation equipment, consumer electronics and industrial sensing systems.

A 3D stacked chip is described. The 3D stacked chip includes a first die and a second die stacked on the first die. The 3D stacked chip also includes a first through-silicon via (TSV) extending through the second die and landing on the first die. The first TSV is composed of a conductive inner layer and a dielectric liner having a first liner thickness. The 3D stacked chip further includes a second TSV extending through the second die landing on the first die. The second TSV is composed of a conductive inner layer and a dielectric liner having a second liner thickness different from the first liner thickness.

An electronic package is provided, in which an electronic module and a plurality of conductive pillars are embedded in an encapsulation layer, and a circuit structure is formed on the encapsulation layer, where the electronic module includes a carrier structure having conductive vias and at least a first electronic element disposed on the carrier structure. The first electronic element has a plurality of conductors in a form of conductive through-silicon vias, and at least a second electronic element is disposed on the circuit structure. Therefore, the design of the electronic module can reduce the layout area occupied by the electronic element on a surface of a packaging zone of the circuit structure, such that other functional elements can be added to the electronic package according to requirements, and the electronic package can improve functional requirements of the end product.

The invention provides an edge coupling light emitting type 3D optical co-packaging preparation method supporting plastic packaging. The method adopts a 3D stacking scheme that an electric chip is arranged on the upper portion and an optical chip is arranged on the lower portion, and comprises the steps that S1, a plurality of rewiring layers and a micro bonding pad are prepared on the upper portion of the optical chip; s2, enabling the optical chip to be electrically connected with the electric chip through the multi-layer rewiring layer and the micro bonding pad; and S3, leading out signal input and output interfaces of the electric chip, the optical chip and the ASIC / switching chip downwards through silicon through holes in the optical chip, and realizing electric connection with the ASIC / switching chip through a substrate or an adapter plate. According to the invention, plastic package can be supported, the light emitting efficiency of the optical port is not influenced by a plastic package material after RDL and EIC bonding and plastic package processes are manufactured, the adhesion of the plastic package material or PI particles on the optical port during mechanical cutting is relieved, and the coupling efficiency is ensured.

The invention provides a maskless etching method of a silicon through hole. The method comprises the following steps: etching a first dielectric layer by adopting a first continuous radio frequency wave plasma etching process; etching the second dielectric layer by adopting a pulse plasma etching process; and further etching the second dielectric layer by adopting a second continuous radio frequency wave plasma etching process. According to the pulse plasma etching, bias power is periodically turned on and turned off, polymer protection layers are formed at the corners and the side walls of the silicon through holes in the bias power turning-off stage, and meanwhile etching of the bottoms of the holes is kept. According to the method, dynamic balance is established between etching and protection, so that the problem that a high-dielectric-constant film layer is exposed due to insufficient corner protection in a traditional process is effectively solved, the thickness of a corner protection layer larger than 100 nm can be reserved, and the yield and reliability of a chip are remarkably improved.

The embodiment of the invention provides a three-dimensional stacked chip system, a memory access method and electronic equipment. The chip system comprises a substrate; the one or more calculation core particles are arranged on the substrate; one or more memory core grains, each memory core grain is stacked above the corresponding calculation core grain through a silicon through hole, and the calculation core grains and the memory core grains are packaged into a first chip; and the one or more input and output core particles are arranged on the substrate at one side of the calculation core particles and are connected with each calculation core particle through substrate wiring, the input and output core particles are packaged into a second chip, and no direct communication path exists between the input and output core particles and the one or more memory core particles. By adopting the technical scheme, the transmission delay between the calculation core particle and the memory core particle can be reduced.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

Methods and devices of having an enclosure structure formed in a multi-layer interconnect and a through-silicon-via (TSV) extending through the enclosure structure. In some implementations, a protection layer is formed between the enclosure structure and the TSV.

A silicon photonic bridge and method of manufacturing an integrated circuit semiconductor package may be provided. The system may include an interposer layer formed from a combination of organic and inorganic materials. The silicon photonic bridge may be embedded within the interposer layer. The silicon photonic bridge may include an electrical integrated circuit (IC) configured to process electrical signals and drive the photonic IC (PIC), and a PIC configured to process optical signals, an optical connector element(s) configured to interface the PIC with fiber and a silicon bridge configured to interface between an ASIC integrated on top of the interposer with the EIC. A silicon photonic bridge may be electrically and optically enabled to convert the electrical signal from the ASIC above the interposer to an optical signal going into fiber, and vice versa. Through-silicon vias (TSVs) may extend through the optical engine.

The invention relates to the technical field of microelectronics and MEMS manufacturing, in particular to a bulk acoustic resonator with a double-layer piezoelectric film and a preparation method thereof, according to the method, a heterogeneous integrated key structure is formed by a first piezoelectric layer and a second piezoelectric layer which are deposited on the two sides of a middle electrode layer respectively, the physical and process limits of a single-layer piezoelectric film FBAR are broken through, the high-frequency band is improved, and the high-frequency band is improved. A wider bandwidth is realized; middle electrode layer tuning is combined with back silicon through hole leading-out, front routing inductance is eliminated, and the low-loss characteristic of the filter under high frequency is guaranteed; the self-heating problem under large bandwidth and high power is effectively inhibited through heat dissipation integrated packaging, and the power bearing capacity is improved; the method is compatible with a CMOS (complementary metal oxide semiconductor) process and can be directly embedded into an existing production line, so that the volume is further reduced while the bulk acoustic wave resonator with the double-layer piezoelectric film can effectively cover a frequency band of more than 3GHz, and the problem that a single-layer piezoelectric film and a matched process thereof cannot meet the requirements of a next-generation radio frequency front end on high frequency, large bandwidth, high power and wafer-level packaging is solved.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a landing pad in a back-end-of-line structure; a backside power distribution network in a backside dielectric layer; and a through silicon via extending from the backside dielectric layer to the landing pad in the back-end-of-line structure, where the through silicon via has a first portion of a first width and a second portion of a second width and a discontinuous increase in width from the first width of the first portion to the second width of the second portion. A method of forming the same is also provided.

This application relates to the field of semiconductor device technology and provides a method for fabricating a pressure sensor based on flip-chip bonding technology, as well as the pressure sensor itself. The method includes growing an oxide layer on a substrate; depositing a sensitive thin film layer on the oxide layer; depositing a piezoresistive resistor on the sensitive thin film layer; depositing a wiring layer on the sensitive thin film layer; depositing a silicon capping layer on the wiring layer; depositing stop structures of different heights and positions on the cavity of the silicon capping layer; the silicon capping layer, the sensitive thin film layer, and the wiring layer forming a closed cavity structure; the stop structures being enclosed within the closed cavity structure; etching through-silicon vias (TSVs) on the silicon capping layer and applying a redistribution layer process to connect the TSVs and the wiring layer; depositing a solder resist layer on the silicon capping layer; and etching the back side of the substrate to form a pressure-sensitive cavity. This application provides a protection method that effectively protects the component structure while maintaining or improving the response frequency and sensitivity to meet the requirements of high dynamic performance.

A structure according to the present disclosure includes a bottom metal feature, a semiconductor substrate disposed over the bottom metal feature, an interconnect structure disposed over the semiconductor substrate, a top metal feature over the interconnect structure, a via structure extending from a bottom surface of the top metal feature, through the interconnect structure and the semiconductor substrate, to contact a top surface of the bottom metal feature. The via structure includes a bottom portion disposed in the semiconductor substrate and a top portion disposed in the interconnect structure. The bottom portion and the top portion taper toward the top metal feature. The bottom portion includes a first tapering angle and the top portion includes a second tapering angle smaller than the first tapering angle.

Embodiments of the present application provide a three-dimensional stacked chip system, a memory access method and an electronic device. The chip system comprises: a substrate; one or more computing dies arranged on the substrate; one or more memory dies, each of which is arranged above a corresponding computing die by a through-silicon via stack, and the computing dies and the memory dies are packaged as a first chip; and one or more input / output dies arranged on the substrate on a side of the computing dies and connected to each of the computing dies through substrate wiring, the input / output dies are packaged as a second chip, and there is no direct communication path between the input / output dies and the one or more memory dies. The above technical solution can reduce the transmission delay between the computing dies and the memory dies.

The invention relates to the field of integrated circuit manufacturing, in particular to an integrated circuit and a packaging method thereof. Etching an open groove in the blank area; embedding the embedded core particles into the open groove to obtain an integrated chip; a graphical insulation blocking layer is arranged on the upper surface of the integrated chip; obtaining a top wiring layer on the basis of the insulation blocking layer; inversely mounting external core particles on the top wiring layer; the external core particles are electrically connected with the embedded core particles through the top wiring layer. The core particles and the chip are silicon-based integrated circuits, thermal expansion coefficients are highly matched, and heat dissipation is facilitated; on one hand, the integration level of the core particles of the packaging device is improved, and on the other hand, vertical short-distance interconnection between the core particles is provided, so that the signal quality is guaranteed; through silicon vias penetrating through the embedded core particles are prevented from being formed in the embedded core particles, so that the signal transmission path is shortened, and meanwhile, the low production cost and the high embedded core particle setting flexibility are guaranteed.

This application discloses a method and electronic device for detecting transmission parameters of through-silicon vias (TSVs), applied in the field of integrated circuit technology. The method includes: determining whether the total length of the TSV to be tested is greater than a preset first length; if so, dividing the TSV into multiple via segments such that the length of each segment is no greater than the first length; if not, treating the TSV as a TSV composed of single-segment vias; for each via segment, obtaining the pad capacitance, via pillar capacitance, anti-pad capacitance, via inductance, and via resistance of the via segment using preset parameter calculation rules, and constructing an equivalent circuit model of the via segment; cascading the equivalent circuit models of each via segment of the TSV to form an equivalent circuit model of the TSV, and performing transmission parameter detection on the TSV. Applying the scheme of this application can effectively determine the transmission parameters of the TSV, improving efficiency and ensuring the accuracy of the scheme.

The invention provides a silicon-based driving chip, a packaging device and a control method, belongs to the technical field of chip integration, and solves the technical problems of large plane space occupation and low heat dissipation of a miniature display driving chip in the prior art. The pixel electrode array is arranged on the first surface of the silicon substrate, and the second surface is opposite to the first surface; the silicon through holes vertically penetrate through the silicon substrate; and the active circuit system is arranged on the second surface of the silicon substrate and outputs a driving electric signal to the pixel electrode array through a plurality of wires. The packaging device comprises a display panel which is provided with a plurality of electrode salient points, corresponds to a pixel electrode array of a silicon-based driving chip in position and is electrically connected with the pixel electrode array through a flip-chip bonding process; and one surface of the packaging substrate is provided with a plurality of connecting salient points, and the connecting salient points are connected with the second surface of the silicon-based driving chip. The driving module is applied to micro display equipment and based on three-dimensional integrated packaging.