789 results about "Through-silicon via" patented technology

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

A package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on the upper portion of the first logic die and a lower TSV on the lower portion of the first logic die. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive via penetrates through the molding material. The redistribution layer is over the first logic die and the molding material.

A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.

A solid-state electronic miniature clock featuring a multi-layered silicon chip. A first circuit layer includes an electron paramagnetic resonance sensor, while the second layer comprises a silicon substrate with an etched trench housing single atom-doped fullerene molecules. Magnets are strategically placed on the silicon substrate and a third circuit layer to establish a baseline magnetic field. The chip incorporates through silicon vias (TSVs) filled with copper, forming a copper coil for enhanced antenna performance. Thermal management is achieved through vacuum cavities for isolation, strategically placed metals for heat generation, and thermo-electric materials, such as a bilayer of Bi$_2$Te$_3$ and Bi$_2$Se$_3$, for temperature regulation. A feedback loop monitors and adjusts the temperature, ensuring stability. Fabrication techniques include Deep Reactive Ion Etching (DRIE), electrochemical deposition, and photolithographic patterning, providing precise control over the chip's structure and functionality.

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention provides an MEMS (Micro Electro Mechanical System) micromirror array chip, a module and optical scanning equipment. The MEMS micromirror array chip comprises a plurality of micromirror structures, a substrate, a vertical lead structure and a capacitance angle sensing structure, according to the micro-mirror array chip integrated with the capacitive sensor, array-level real-time angle detection, feedback control and high-precision scanning angle detection are realized, and the micro-mirror array chip is fast in driving and resistant to interference; meanwhile, the wiring density is reduced by frequency division multiplexing isolation signals; in addition, the application of a monolithic integrated capacitance angle sensor in a high-density micro-mirror array chip is realized by a thick substrate with a silicon through hole; and finally, the micromirror array chip of the monolithic integrated capacitance angle sensor is used for precision optical scanning equipment, a photoelectric angle detector is omitted, optical scanning high-precision real-time angle detection and feedback control, high-precision angle detection and high-speed scanning are realized, the use design is convenient, and the cost is low.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention relates to a three-dimensional high-density interconnection method for a substrate and an IC chip, and the method comprises the following steps: carrying out the multi-layer dielectric composite processing of a preset silicon substrate, and obtaining a silicon through hole array structure with a preset depth-to-width ratio; performing metal filling on the silicon through hole array structure to obtain a three-dimensional interconnection conductive path; performing surface treatment on the three-dimensional interconnection conductive path to obtain a micro bump structure with gradient metallization; performing laser-assisted bonding on the micro bump structure to obtain a silicon bridge-substrate temporary structural body; carrying out bottom filling on the silicon bridge-substrate temporary structure body through a supercritical fluid auxiliary injection technology to obtain a packaging structure body with a stress release function; and a preset IC chip and the packaging structure body are assembled and fixed to obtain a three-dimensional high-density interconnection packaging body, and the technical problem that a traditional two-dimensional plane interconnection method is difficult to meet the requirement of high-density integration is solved.

Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through-silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.

The invention discloses a method for constructing an unsteady thermal stress analytical model of a through silicon via, which belongs to the technical field of microelectronics and comprises the following steps of: establishing a transient thermal conduction equation and a temperature field boundary condition of the through silicon via; solving the transient heat conduction equation to obtain a transient temperature field analytical model, and obtaining transient temperature field distribution according to the transient temperature field analytical model; establishing an equilibrium equation and a mechanical boundary condition based on a working environment of the through silicon via, and determining a displacement field of the through silicon via and a basic form of a stress field analytical model according to the equilibrium equation and the transient temperature field analytical model; coupling the transient temperature field and the transient stress field according to the mechanical boundary condition and the basic form of the displacement field and stress field analytical model to obtain an unsteady thermal stress analytical model; and obtaining the unsteady thermal stress according to the unsteady thermal stress analytical model. According to the method, the problem that temperature field distribution and thermal stress change along with time are not considered in a thermal stress analysis model is solved, and real-time prediction of thermal stress distribution in the silicon through hole is realized.

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

A semiconductor device includes a through-silicon via (TSV) in a substrate, wherein the TSV extends through the substrate. The semiconductor device further includes an ESD cell in the substrate, the ESD cell comprising a set of diodes electrically connected in parallel to each other. The semiconductor device further includes an antenna electrically connected to the TSV and extending in a first direction parallel to a major axis of the TSV. The semiconductor device further includes a conductive pillar electrically connected to the ESD cell, wherein the antenna is between the TSV and the conductive pillar.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

A 3D stack package structure includes a first chip, a second chip, a through-silicon via (TSV), and a multi-layer protective structure. The second chip is bonded to the first chip. The second chip includes an interconnect structure composed of multiple metal layers and a plurality of vias respectively connecting upper and lower layers of the multiple metal layers. The TSV extends through the second chip. The multi-layer protective structure is disposed within the second chip and surrounds the TSV. The multi-layer protective structure includes: multiple protective layers, each having an opening for passage of the TSV; and a plurality of sealing rings, respectively connecting upper and lower layers of the multiple protective layers and surrounding the TSV.

The invention provides a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a lower package including a first substrate, a first chip, and a first redistribution layer; and an upper package disposed on the lower package and including a second substrate, a second chip, and a plurality of internal connection terminals disposed on the second substrate and connected to the first redistribution layer. The first substrate comprises a concave part, the first chip is arranged in the concave part in a mode that the active surface of the first chip faces downwards, the heat conduction material fills the remaining space of the concave part, and the first redistribution layer is located on the first substrate, the heat conduction material and the first chip. The first chip includes a plurality of through silicon vias, the second chip is electrically connected to the plurality of through silicon vias via the plurality of internal connection terminals and the first redistribution layer, the first substrate further includes a signal via configured to communicate the semiconductor package with the outside, and a dummy via configured to dissipate heat of the first chip to the outside.

Example methods and apparatus for embedding interconnect bridges having through silicon vias in substrates are disclosed. An example semiconductor package a bridge die disposed in a recess of an underlying substrate, the bridge die including a via that electrically couples a first contact on a first side of the bridge die and a second contact on a second side of the bridge die, the recess extending to a first surface of the underlying substrate; a bond material to electrically and mechanically couple the first contact and an interconnect of the underlying substrate; and a fill material positioned between the first side of the bridge die and the first surface of the underlying substrate.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

The invention discloses a vehicle gauge chip integrated packaging manufacturing process based on an etching technology. The vehicle gauge chip integrated packaging manufacturing process comprises the following steps: step 1, designing and preparing a substrate; step 2, preprocessing the chip; step 3, chip mounting and interconnection are carried out; step 4, plastic packaging and molding; 5, heat dissipation and reinforcement are carried out; step 6, image rotation correction and defect detection; step 7, performing post-working procedures and testing; high-density interconnection such as TSV (through silicon vias), RDL (redistribution layer) and micro bumps is realized by using an etching technology, the interconnection density is remarkably improved, the RDL wiring layer manufactured by using the etching technology has the line width less than 2 microns, high-density interconnection on the surface of a chip is realized, the integration level is further improved, the micro-channel is manufactured in the plastic package layer by using the etching technology, and the packaging efficiency is improved. And the copper radiating fins are embedded, so that the radiating efficiency is effectively improved, the problem of local heat accumulation caused by integration of the power chip and the logic chip is solved, a gap between the chip and the radiating cover plate is filled with a thermal interface material with high thermal conductivity, and the thermal resistance is reduced.

The invention discloses a fan-out packaging structure and a preparation method thereof. The fan-out packaging structure comprises a power supply substrate; the adapter plate is located on one side of the power supply substrate and electrically connected with the power supply substrate; the redistribution layer is located on the side, away from the power supply substrate, of the adapter plate and electrically connected with the adapter plate; the functional chip layer is located on the side, away from the power supply substrate, of the redistribution layer and electrically connected with the redistribution layer; wherein the adapter plate comprises an organic plastic package layer and a plurality of conductive capacitor chips coated in the organic plastic package layer; the conductive capacitor chip is provided with a silicon through hole, and the silicon through hole in the conductive capacitor chip is used for providing a power signal of the power supply substrate to the functional chip in the functional chip layer through the redistribution layer. According to the technical scheme provided by the invention, the fan-out requirement of a large-size chip is met, the product yield and the effective DTC density are improved, and the problems of packaging warping and internal stress concentration are solved.

A semiconductor device includes one or more core dies, through silicon vias that penetrate the one or more core dies, and a processor connected to the one or more core dies through a through silicon via of the through silicon vias. The processor generates a first command set including plural commands and plural clock signals having different phases for a target core die among the one or more core dies, and performs a training operation for the target core die based on the first command set and the plural clock signals.

The present disclosure provides a miniature electrostatic chuck (ESC) for die-to-wafer (D2W) bonding. The ESC can be manufactured using conventional semiconductor processes, incorporating through-silicon-via (TSV) and through-dielectric-via (TDV) structures. The ESC with different sizes can be attached to and detached from a multi-axis robotic arm, allowing optimized D2W bonding processes.

A semiconductor device comprises a wafer with an active interposer comprising one or more active components in an active component layer. The semiconductor device comprises a first chiplet that is mounted on the wafer and above the active interposer, a second chiplet that is mounted on the wafer and above the active interposer, and an interconnect layer having an interconnection that bridges between the first chiplet and the second chiplet. The interconnect layer is configured to transfer at least one of power and a signal from a bottom-side bump on a bottom side of the wafer to at least one of the first chiplet and the second chiplet, directly or indirectly, through a TSV of the active interposer.

Methods for fabricating glass cores with conductive vias (e.g., TGVs), as well as related devices, are disclosed. Methods described herein are based on fabricating pillars of conductive materials (e.g., metals or metal alloys) on a temporary support, inserting the pillars into corresponding via openings in a glass core, and at least partially filling the remaining space in the openings with a filler material.

A chip package includes a first integrated-circuit (IC) chip; a second integrated-circuit (IC) chip over the first integrated-circuit (IC) chip; a connector over the first integrated-circuit (IC) chip and on a same horizontal level as the second integrated-circuit (IC) chip, wherein the connector comprises a substrate over the first integrated-circuit (IC) chip and a plurality of through vias vertically extending through the substrate of the connector; a polymer layer over the first integrated-circuit (IC) chip, wherein the polymer layer has a portion between the second integrated-circuit (IC) chip and connector, wherein the polymer layer has a top surface coplanar with a top surface of the second integrated-circuit (IC) chip, a top surface of the substrate of the connector and a top surface of each of the plurality of through vias; and an interconnection scheme on the top surface of the polymer layer, the top surface of the second integrated-circuit (IC) chip, the top surface of the connector and the top surface of each of the plurality of through vias.