920 results about "Through-silicon via" patented technology

The invention provides a silicon bridge chip packaging method and a silicon bridge chip packaging structure, which can reduce the manufacturing cost and improve the heat dissipation effect of a packaging body. A silicon through hole and a first dielectric substance layer are manufactured on the first surface of a silicon wafer, a groove is manufactured by avoiding the silicon through hole, a silicon bridge chip is mounted in the groove, a rewiring layer is arranged on the first surface of the silicon wafer, and the silicon bridge chip is packaged by the rewiring layer. Welding salient points are arranged on the rewiring layer, and the welding salient points are connected to the silicon bridge chip through lines on the rewiring layer; at least two chips are connected with the welding bumps, so that the chips are connected through the silicon bridge chip, the first surface of the silicon wafer is subjected to plastic packaging, the second surface, away from the silicon bridge chip, of the silicon wafer is thinned until the bottom of the silicon through hole is exposed, then a second dielectric substance layer is manufactured, and metal bumps are arranged; and thinning the plastic packaging layer on the first surface of the silicon wafer to expose the back surface of the chip, cutting the silicon wafer into single packaging bodies, inversely welding the single packaging bodies on the first surface of the substrate through the metal bumps, and arranging solder balls on the second surface of the substrate.

The invention discloses a preparation method and structure of an interposer embedded with a silicon bridge and a high-density silicon capacitor, and belongs to the field of advanced packaging of integrated circuits. The method can be used for 2.5 D advanced packaging high-density interconnection; the interposer structure comprises an interposer back RDL rewiring layer, an intermediate layer which is formed by embedding a silicon bridge and a high-density silicon capacitor by using a high-molecular epoxy resin material EMC, and an RDL rewiring layer on the front side of the interposer. High-density vertical interconnection between the upper RDL layer and the lower RDL layer is achieved through an electroplating ultrahigh copper column penetrating through the resin material, micron-level and submicron-level ultrahigh-density interconnection can be achieved through a silicon bridge embedded in the EMC resin, and high-performance packaging-level power supply decoupling can be achieved through a high-density silicon capacitor embedded in the resin. The preparation method of the structure is easy to implement, the cost is greatly reduced compared with that of the TSV silicon adapter plate interposer, and the method can be used for large-scale mass production of 2.5 D interposers.

A system, method, and computer program product are provided for cooperation memory system. The system includes a first semiconductor platform including at least one first circuit, and at least one additional semiconductor platform stacked with the first semiconductor platform and including at least one additional circuit. The system further includes an adjustment of at least one aspect of the system, for repairing one or more faulty components of the memory subsystem capable of including: a through-silicon via (TSV) between the first memory and the second memory, and a memory cell of at least one of the first memory or the second memory.

The invention discloses a photonic integrated circuit chip and a silicon optical integration platform, and aims to provide a specific waveguide structure on the photonic integrated circuit chip to realize efficient coupling with a common single-mode fiber, and meanwhile, a suspended structure is not introduced, so that the overall structure has relatively high mechanical stability. The method can pass high-temperature and high-humidity reliability test conditions of the photon integrated circuit chip, and is compatible with reflow soldering, silicon through hole and other processes.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. The stack may include, e.g., three or more power components. Through-silicon vias in some or all of the power components can allow for connections through one power component to another. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.

The invention provides a packaging structure and a forming method thereof, in the forming method, a bridge chip assembly is firstly formed, a silicon through hole of a bridge chip is exposed in a mode of firstly depositing a protection layer and then thinning the silicon through hole, the protection layer can protect a substrate in the thinning process, and the substrate is prevented from being damaged. Metal ions generated by thinning the silicon through hole can be prevented from being migrated and diffused into the substrate, so that the problem of reliability failure of the packaging structure caused by migration and diffusion of the metal ions is avoided; meanwhile, when the bridge chip assembly is plastically packaged, the bottom surface of the bridge chip assembly is provided with an adhesion layer, the adhesion layer is removed after plastic packaging, so that the bottom surface of the bridge chip assembly is higher than the bottom surface of the first plastic packaging layer, and after bottom rewiring layers are formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly, the bottom rewiring layers are formed on the bottom surface of the first plastic packaging layer and the bottom surface of the bridge chip assembly. The thickness of the bottom rewiring layer located on the bottom face of the bridge chip assembly is larger than that of the bottom rewiring layer located on the bottom face of the first plastic packaging layer, namely, the bottom of the bridge chip assembly is provided with a thicker dielectric layer, so that the connection strength of all connection points of the bridge chip assembly is guaranteed, higher stress buffering is provided for the bridge chip, and the reliability of the bridge chip assembly is improved. And the reliability of the packaging structure is improved.

The invention discloses a TSV-based multi-layer microsystem interconnection module total dose effect simulation modeling method, and relates to the technical field of three-dimensional integrated microsystems, and the method comprises the steps: obtaining geometric parameters and material parameters of a multi-layer three-dimensional microsystem interconnection module, building a finite element model of a microsystem module based on the geometric parameters and the material parameters, and carrying out the simulation modeling of the TSV-based multi-layer microsystem interconnection module total dose effect. Setting boundary conditions and port excitation; scattering parameters under different material conditions in the finite element model are extracted, frequency points are fixed, and a relational expression of the scattering parameters and material parameters is established; an RLC equivalent circuit model is constructed, and an equivalent circuit extraction method is obtained; according to an equivalent circuit extraction method, in combination with a relational expression of scattering parameters and material parameters, establishing a relationship between return loss parameters and equivalent circuit parameters; and establishing a relation model between the radiation dose and the resistance, inductance and capacitance in the equivalent circuit according to the relation between the return loss parameter and the equivalent circuit parameter. According to the invention, a scientific basis is provided for the reliability design of the three-dimensional microsystem in the radiation environment.

A package structure includes an interconnect structure, a first logic die, a molding material, a conductive via, and a redistribution layer. The interconnect structure is attached to a package substrate. The first logic die is disposed over the interconnect structure. The first logic die includes an upper through-silicon via (TSV) on the upper portion of the first logic die and a lower TSV on the lower portion of the first logic die. The upper portion of the first logic die includes a device layer and a power transmission layer, and the upper TSV penetrates through the device layer and physically connected to the power transmission layer. The molding material is over the interconnect structure and surrounds the first logic die. The conductive via penetrates through the molding material. The redistribution layer is over the first logic die and the molding material.

A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component.

A solid-state electronic miniature clock featuring a multi-layered silicon chip. A first circuit layer includes an electron paramagnetic resonance sensor, while the second layer comprises a silicon substrate with an etched trench housing single atom-doped fullerene molecules. Magnets are strategically placed on the silicon substrate and a third circuit layer to establish a baseline magnetic field. The chip incorporates through silicon vias (TSVs) filled with copper, forming a copper coil for enhanced antenna performance. Thermal management is achieved through vacuum cavities for isolation, strategically placed metals for heat generation, and thermo-electric materials, such as a bilayer of Bi$_2$Te$_3$ and Bi$_2$Se$_3$, for temperature regulation. A feedback loop monitors and adjusts the temperature, ensuring stability. Fabrication techniques include Deep Reactive Ion Etching (DRIE), electrochemical deposition, and photolithographic patterning, providing precise control over the chip's structure and functionality.

A skip-level through-silicon via structure is provided that enables low resistance via connection for backside power distribution by skipping one or more intermediate backside metal layers. The skip-level through-silicon via structure can enable a greater design flexibility for power grid. The skip-level through-silicon via structure has a large size that provides lower through-silicon via resistance as compared with conventional through-silicon via structures.

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

The invention provides an MEMS (Micro Electro Mechanical System) micromirror array chip, a module and optical scanning equipment. The MEMS micromirror array chip comprises a plurality of micromirror structures, a substrate, a vertical lead structure and a capacitance angle sensing structure, according to the micro-mirror array chip integrated with the capacitive sensor, array-level real-time angle detection, feedback control and high-precision scanning angle detection are realized, and the micro-mirror array chip is fast in driving and resistant to interference; meanwhile, the wiring density is reduced by frequency division multiplexing isolation signals; in addition, the application of a monolithic integrated capacitance angle sensor in a high-density micro-mirror array chip is realized by a thick substrate with a silicon through hole; and finally, the micromirror array chip of the monolithic integrated capacitance angle sensor is used for precision optical scanning equipment, a photoelectric angle detector is omitted, optical scanning high-precision real-time angle detection and feedback control, high-precision angle detection and high-speed scanning are realized, the use design is convenient, and the cost is low.

The invention discloses an IC (integrated circuit) chip packaging detection method for realizing system-in-package and 3D (three-dimensional) packaging, which relates to the technical field of chip packaging detection, and comprises the following steps: vertically stacking a plurality of DRAM (dynamic random access memory) core particles on a basic logic core particle with a micro-bump array on the surface through silicon through holes, and activating a self-detection circuit to obtain a suspicious area coordinate list; dividing regional risk levels through a targeted scanning scheduling algorithm, and generating a differentiated scanning parameter set; for each suspicious area, controlling an external X-ray source to collect multispectral projection data according to the differential scanning parameter set; performing three-dimensional reconstruction on the multiple groups of multispectral projection data by using an enhanced reconstruction model embedded with physical priori knowledge to obtain enhanced three-dimensional body data; and performing automatic defect identification on the enhanced three-dimensional body data, and outputting the identified defect as a detection result. The invention aims to solve the problems of difficulty in perspective imaging and insufficient resolution of internal defects of the high-density 3D stacked chip.

The invention provides a high-density photoelectric common connection pinboard based on a low-loss silicon nitride grating coupler. The invention aims to overcome the difficulty that the existing photoelectric heterogeneous chip is difficult to integrate, stack and package, and realizes high-density interconnection between the chip and the interposer by using a grating coupling structure and a silicon through hole technology, thereby realizing high-integration low-loss packaging of the heterogeneous chip on the interposer. According to the invention, high-efficiency optical interconnection between the heterogeneous chip and the photoelectric co-connection intermediate layer is realized through the high-efficiency grating coupler, and high-density electrical interconnection between the chip and the photoelectric co-connection intermediate layer is realized through the TSV technology and the RDL technology. Meanwhile, the optical interconnection efficiency between the interposer and the chip is improved by utilizing the electrode patterning advantage of the RDL technology, and the self-alignment between the chip and the interposer is realized. The method has extremely high compatibility to the packaging scene of the existing photoelectric heterogeneous chip, so that the method has great significance in improving the integration density and reducing the interconnection loss of a photoelectric heterogeneous integrated system and promoting the practicability of the photoelectric heterogeneous integrated system.

The invention relates to a three-dimensional high-density interconnection method for a substrate and an IC chip, and the method comprises the following steps: carrying out the multi-layer dielectric composite processing of a preset silicon substrate, and obtaining a silicon through hole array structure with a preset depth-to-width ratio; performing metal filling on the silicon through hole array structure to obtain a three-dimensional interconnection conductive path; performing surface treatment on the three-dimensional interconnection conductive path to obtain a micro bump structure with gradient metallization; performing laser-assisted bonding on the micro bump structure to obtain a silicon bridge-substrate temporary structural body; carrying out bottom filling on the silicon bridge-substrate temporary structure body through a supercritical fluid auxiliary injection technology to obtain a packaging structure body with a stress release function; and a preset IC chip and the packaging structure body are assembled and fixed to obtain a three-dimensional high-density interconnection packaging body, and the technical problem that a traditional two-dimensional plane interconnection method is difficult to meet the requirement of high-density integration is solved.

Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through-silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.

The invention provides a chip packaging structure and electronic equipment, relates to the technical field of chips, and can meet the requirement of high bandwidth density between chips on the basis of supporting integration of heterogeneous chips (die). The chip packaging structure comprises a first chip, an electronic element and a hybrid adapter plate with a novel structure. The hybrid adapter plate comprises a silicon interposer and a rewiring layer, the front surface of the silicon interposer is provided with a metal wiring layer, and the silicon interposer is provided with a silicon through hole. The first chip is arranged on the front surface of the silicon interposer and is electrically connected with the metal wiring layer. Or the hybrid adapter plate comprises a first rewiring layer, a second rewiring layer, a bridge chip and a metal connecting structure, the bridge chip and the metal connecting structure are located between the two rewiring layers, and the bridge chip achieves interconnection between the first chips through the first rewiring layer. The second redistribution layer is connected with the first redistribution layer through a metal connection structure. The electronic component is located on the back face of the redistribution layer and connected with the redistribution layer or connected with the redistribution layer through the substrate.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall. The IC structure further includes a logic die with memory controller and processor circuit under the memory stack and electrically connected to the plurality of edge pads of each semiconductor memory die, and a packaging substrate under and electrically connected to the logic die with memory controller and processor. There is no interposer between the packaging substrate and the logic die with memory controller and processor circuit, and there is no TSV in each semiconductor die.

An integrated circuit (IC) layer stack is disclosed that integrates bypass chiplets in the IC layer stack without requiring fabrication of through-silicon vias (TSV) in a digital device for signals and power to a memory stack located above the digital device. Not requiring adding TSVs to an existing design high-performance digital device significantly reduces and / or eliminates digital device modification costs and time to manufacture new products consisting of three-dimensional stacked memory and digital device organizations. The bypass chiplets may be passive with just through conductors in silicon, or active with logic circuits therein. Flexibility of placement of the bypass chiplets in the IC layer stack in combination with an active interposer provides for many possible configurations of IC layer stacks. The digital device may be a microcontroller, a microprocessor, a PLA, an ASIC, a DSP, a GPU, a FPGA, neural processing unit, tensor processing unit, or any combination thereof.

The invention discloses a method for constructing an unsteady thermal stress analytical model of a through silicon via, which belongs to the technical field of microelectronics and comprises the following steps of: establishing a transient thermal conduction equation and a temperature field boundary condition of the through silicon via; solving the transient heat conduction equation to obtain a transient temperature field analytical model, and obtaining transient temperature field distribution according to the transient temperature field analytical model; establishing an equilibrium equation and a mechanical boundary condition based on a working environment of the through silicon via, and determining a displacement field of the through silicon via and a basic form of a stress field analytical model according to the equilibrium equation and the transient temperature field analytical model; coupling the transient temperature field and the transient stress field according to the mechanical boundary condition and the basic form of the displacement field and stress field analytical model to obtain an unsteady thermal stress analytical model; and obtaining the unsteady thermal stress according to the unsteady thermal stress analytical model. According to the method, the problem that temperature field distribution and thermal stress change along with time are not considered in a thermal stress analysis model is solved, and real-time prediction of thermal stress distribution in the silicon through hole is realized.

Methods, systems, and methods of manufacture are described for integrating memory and compute die in a stacked configuration in an integrated circuit package without through silicon via. A packaging apparatus that includes a first semiconductor die comprising multiple memory cells and a second semiconductor die comprising compute logic representing a Processing-in-Memory (PiM) architecture. The PiM architecture is configured to process data stored at the memory cells. The first semiconductor die and the second semiconductor die are: i) arranged in a stacked configuration and ii) coupled to exchange signal communications that allow for processing, at the second semiconductor die, data routed from a memory cell of the first semiconductor die.

A non-volatile memory apparatus includes a stack of memory dies with multiple layers. Each layer has multiple memory die, and the stack includes separate parallel through silicon vias (TSVs) for each memory die. The non-volatile memory apparatus also includes a memory controller in electrical communication with the separate parallel TSVs for each memory die and configured to perform a high bandwidth read process for data stored in the stack across all or multiple of the memory dies.

A semiconductor device includes a through-silicon via (TSV) in a substrate, wherein the TSV extends through the substrate. The semiconductor device further includes an ESD cell in the substrate, the ESD cell comprising a set of diodes electrically connected in parallel to each other. The semiconductor device further includes an antenna electrically connected to the TSV and extending in a first direction parallel to a major axis of the TSV. The semiconductor device further includes a conductive pillar electrically connected to the ESD cell, wherein the antenna is between the TSV and the conductive pillar.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

A 3D stack package structure includes a first chip, a second chip, a through-silicon via (TSV), and a multi-layer protective structure. The second chip is bonded to the first chip. The second chip includes an interconnect structure composed of multiple metal layers and a plurality of vias respectively connecting upper and lower layers of the multiple metal layers. The TSV extends through the second chip. The multi-layer protective structure is disposed within the second chip and surrounds the TSV. The multi-layer protective structure includes: multiple protective layers, each having an opening for passage of the TSV; and a plurality of sealing rings, respectively connecting upper and lower layers of the multiple protective layers and surrounding the TSV.

Semiconductor device structures and methods of forming the same are described. The structure includes a through silicon via (TSV) disposed in the interconnect structure and the substrate, a protection structure in the interconnect structure surrounding the TSV, and an active region surrounding the protection structure. The spacing between the protection structure and the active region is free of dummy devices. The embodiment of the invention also relates to a semiconductor package.

The present application relates to the technical field of dies, and provides a die packaging structure and an electronic device, which can satisfy the high-bandwidth density requirement for dies while supporting heterogeneous die integration. The die packaging structure comprises a first die, an electronic element and a hybrid interposer of a novel structure. The hybrid interposer comprises a silicon interposer and a redistribution layer, a metal wiring layer is provided on the front surface of the silicon interposer, and a through silicon via is formed in the silicon interposer. The first die is disposed on the front surface of the silicon interposer and is electrically connected to the metal wiring layer. Alternatively, the hybrid interposer comprises a first redistribution layer, a second redistribution layer, a bridge die located between the two redistribution layers, and a metal connecting structure, and the bridge die achieves interconnection between first dies by means of the first redistribution layer. The second redistribution layer is connected to the first redistribution layer by means of the metal connecting structure. The electronic element is located on the back surface of the redistribution layer, is connected to the redistribution layer or is connected to the redistribution layer by means of a substrate.

The invention provides a layout and logic diagram comparison LVS verification method, which is applied to a three-dimensional integrated circuit (3D IC) comprising at least two bare chip stacked layer by layer and at least one through silicon via (TSV), and comprises the following steps: acquiring a first netlist file; obtaining a first layout file, wherein the first layout file comprises a circuit layout of the three-dimensional integrated circuit; according to the first layout file, constructing a simplified model of the three-dimensional integrated circuit, the simplified model comprising a connection relationship and a stack structure of the at least two bare chips and the at least one TSV in a circuit layout; and comparing the first netlist file with the simplified model to obtain LVS verification information of the three-dimensional integrated circuit. According to the method, the 3D IC is simplified into a plurality of independent models, and then the models are converted into LVS verification of the 2D stacked model, so that the operation efficiency of the LVS verification is optimized.