32 results about "Thermal oxide" patented technology

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

The utility model relates to the field of tail gas treatment, and discloses a liquid-containing industrial carbon monoxide waste gas treatment device which comprises a heat exchanger, a liquid separation tank, a wire mesh demister and an RTO combustion furnace which are sequentially connected in series through pipelines, and a diluent introduction pipeline is connected between the wire mesh demister and the RTO combustion furnace. Liquid-containing industrial carbon monoxide waste gas is cooled through the heat exchanger and then passes through the liquid separation tank and the wire mesh demister to obtain high-concentration carbon monoxide waste gas, a diluent is introduced through the diluent introduction pipeline to dilute the high-concentration carbon monoxide waste gas, and then the high-concentration carbon monoxide waste gas enters the RTO combustion furnace to be subjected to combustion treatment. The liquid-containing industrial carbon monoxide waste gas treatment device provided by the utility model can effectively solve the potential safety hazard in the industrial production process and ensure the safe operation of the industrial production.

Aspects of the present disclosure are directed to an apparatus including a circuit region and a fluidic region. In a particular example, the circuit region with logical circuits thereon, includes a thermal oxide layer on a silicon substrate, and a dielectric layer over the field oxide layer, the dielectric layer including a doped dielectric film. The microfluidic device further includes a fluidic region including fluid ports formed through a surface of the apparatus and including an un-doped dielectric film. The fluidic region includes an aperture in the dielectric layer, where the aperture is defined by a dielectric wall which forms part of the dielectric layer. A sealing film deposited over the dielectric wall may prevent the doped dielectric film from contacting fluid contained in the fluid port.

The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

The invention relates to a PZT target material and a preparation process thereof, and relates to the technical field of PZT target materials. The preparation process of the PZT target material comprises the following steps: preparing an SOI silicon wafer; selecting a silicon wafer or a silicon-on-insulator wafer as a substrate; silicon wafer doping: doping silicon on the surface of the silicon wafer; depositing an insulating layer: growing a thermal oxide layer or a chemical vapor deposition SiNx layer on the surface, doped with silicon, of the silicon wafer to serve as the insulating layer; depositing a lower electrode layer; a PZT piezoelectric layer is deposited, specifically, radio frequency magnetron sputtering is conducted on the lower electrode layer at the sputtering temperature (500-600 DEG C), the deposition rate is 35-48 nm / min, and the PZT piezoelectric layer is formed; after sputtering, keeping the annealing temperature of 465 DEG C in the chamber and annealing for 5 minutes; etching the PZT piezoelectric layer; etching the lower electrode layer; depositing a top layer; etching the insulating layer; depositing a top layer electrode; etching the top layer silicon; and etching the bottom silicon and the silicon dioxide. The method has the effect of ensuring the piezoelectric property of the prepared PZT target material.

This invention discloses a heterogeneous integrated electro-optic modulator and its alignment method based on write field splicing compensation, relating to the field of silicon-based optoelectronics technology. The modulator comprises, from bottom to top, a silicon substrate with a thermal oxide layer, a bottom patterned waveguide layer, an intermediate transition dielectric layer, a top electro-optic thin film layer, and a top traveling-wave electrode structure. The bottom waveguide layer has a write field splicing region along the light propagation direction, within which a thermal compensation structure is configured, and a dedicated alignment mark is provided within a designated area. This mark is formed synchronously with the waveguide layer and the compensation structure within the same photolithographic write field. The top traveling-wave electrode structure is overlaid across layers based on this mark, forming a predetermined spatial matching relationship with the write field splicing region. This invention can solve the problems of optical scattering loss caused by long-distance bottom waveguide field-separated exposure splicing and the limited accuracy of cross-layer overlay after heterogeneous bonding, and achieves precise overlay positioning of the cross-layer traveling-wave electrode.

Method for producing a semiconductor silicon wafer, which is composed of a silicon wafer substrate and a monocrystalline epitaxial silicon layer on it, comprising: a step (S2) of forming a silicon oxide layer with a thickness of at least 300 nm or thicker only on the back side of the silicon wafer substrate by the CVD process at a temperature of not more than 500 °C, wherein the silicon wafer substrate is produced from a monocrystalline silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity set to not more than 1.05 mΩ·cm, and a solid solution oxygen concentration of not more than 0.9×10 18 atoms / cm² 3 exhibits and on whose front surface a monocrystalline epitaxial silicon layer is to be formed; a heat treatment step (S4) after the step of forming the silicon oxide layer, in which the substrate is held in an oxidizing atmosphere at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes; a step (S5) of removing the surface oxide layer, which is formed as a thermal oxide layer on the front surface of the substrate during the heat treatment step, after the heat treatment step; and a step of depositing a monocrystalline epitaxial silicon layer on the substrate after the step of removing the surface oxide layer.

A method of manufacturing a gate-all-around electronic device is described. The method includes forming a thermal oxide layer by enhancing in-situ steam generation processing in combination with atomic layer deposition of a low-K layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the gate-all-around (GAA). The passivation processing after deposition of the low-K layer reduces bulk traps and enhances the breakdown performance of the GAA transistor.

To provide a method for evaluating a silicon single crystal wafer, which is useful for suppressing the occurrence of dislocation at a place where a Line & Space pattern is formed.SOLUTION: Forming a plurality of L & S patterns on a surface of the Si single crystal wafer by a SiN film while changing a formation direction of the L & S patterns, forming a thermal oxide film on a surface of the Si single crystal wafer on a side where the L & S patterns are formed, performing a first process of removing the thermal oxide film, and performing a second process of visualizing dislocations existing at a formation position of the L & S patterns as dislocation pits by selective etching; The evaluation method of the Si single crystal wafer includes a process of measuring the density of dislocation pits for each L & S pattern, and a process of determining and evaluating the formation direction of the L & S pattern having the lowest density of dislocation pits as the optimum formation direction from the measurement result.SELECTED DRAWING: Figure 1

The invention provides a preparation process of a groove type silicon carbide gate oxide layer, a groove type silicon carbide wafer with a gate oxide layer and a metal oxide semiconductor field effect transistor. The method comprises the following steps of: depositing and growing a thin oxide layer after etching a groove, depositing polycrystalline silicon, filling the whole groove with the polycrystalline silicon, only reserving the polycrystalline silicon at the bottom of the groove by adopting a polycrystalline silicon back-etching process, and finally performing a thermal oxidation process. Silicon carbide is oxidized in a high-temperature oxygen atmosphere, and polycrystalline silicon at the bottom of the groove is oxidized into an oxide layer; the method not only can ensure that a layer of high-quality thermal oxide is generated on the side wall of the trench as a gate oxide layer, but also can realize that the oxide layer formed by oxidation of polycrystalline silicon at the bottom of the trench is thicker than the oxide layer on the side wall of the trench, thereby improving the voltage endurance capability of the bottom of the trench device.

This invention provides a method for preparing a standard silicon wafer and a method for calibrating a planarity measurement device, comprising: providing a silicon wafer; performing a first heat treatment on the silicon wafer to grow an oxide layer on the surface of the silicon wafer; and performing a second heat treatment on the silicon wafer after the oxide layer has grown to improve the surface roughness of the oxide layer through a high-temperature decomposition reaction; wherein the first heat treatment includes: heating to a first heat treatment temperature and maintaining the first heat treatment time in an atmosphere containing oxygen; the second heat treatment includes: heating to a second heat treatment temperature and maintaining the second heat treatment time in an atmosphere containing argon. The preparation method provided by this invention, by combining a two-step process of "thermal oxidation growth" and "high-temperature decomposition and reconstruction," creates a standard wafer surface that possesses both the purity of the thermal oxide layer and the specific and uniform surface roughness obtained through high-temperature decomposition, meeting the stringent calibration requirements of non-contact planarity measurement devices that are extremely sensitive to cleanliness.

A base plate of a substrate support assembly for supporting a semiconductor substrate in a processing chamber includes a first component made of a first material including a metal and a non-metal. The first material has a first coefficient of thermal expansion. A layer coating the first component is made of a second material. The second material has a second coefficient of thermal expansion. The first and second coefficients of thermal expansion are different.

A micro-electro-mechanical (MEMS) device is provided that includes a fixed body delimiting a cavity; a suspended structure extending cantilevered from the fixed body, above the cavity, and including a suspended semiconductive region; and a transducer arranged above the suspended structure. The suspended structure further includes a compensation region of thermal oxide, which extends below the suspended semiconductive region. A method of manufacturing a MEMS device is also provided.

The present invention is a method for manufacturing an epitaxial wafer by forming a single-crystal silicon layer on a single-crystal silicon wafer via an oxygen-atom layer, the method including the steps of removing a native oxide film, forming a thermal oxide film on a surface of the single-crystal silicon wafer from which the native oxide film has been removed, thinning the thermal oxide film, and after thinning the thermal oxide film, epitaxially growing single-crystal silicon to form an epitaxial wafer in which the single-crystal silicon layer is formed on the single-crystal silicon wafer via the oxygen-atom layer. This provides the method for manufacturing an epitaxial wafer, in which, when manufacturing a silicon epitaxial wafer, the oxygen-atom layer can be introduced into an epitaxial layer stably and easily.

The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

The invention provides a wafer large-thickness thermal oxide layer and a preparation method thereof, and belongs to the technical field of component preparation of semiconductor devices. According to the method, thermal oxide layers with certain thicknesses are prepared on two wafers respectively, the two thermal oxide layers are bonded together, one wafer is removed, and the wafer with the thermal oxide layer with the overlapped thickness is obtained; the method comprises the following steps of: preparing one wafer with a thermal oxide layer, bonding the other wafer with the thermal oxide layer prepared in advance onto the wafer with the thermal oxide layer with the superposed thickness to bond the thermal oxide layers together, and then removing one wafer on the obtained bonding structure to obtain the wafer with the thermal oxide layer with larger thickness. The operation is repeated, and the thermal oxide layer with the required thickness can be obtained. The thermal oxide layer prepared by the method can meet the requirements of thickness, preparation efficiency and preparation cost. The theoretical thickness of the thermal oxide layer prepared by the method can reach 50 microns.

The present application belongs to the technical field of semiconductors, and discloses a germanium-silicon multiple avalanche layer-based germanium-on-insulator SPADs sensor structure and a preparation method therefor. The structure comprises: a sensor wafer, a passivation layer, N-type electrodes, P-type electrodes, and a readout circuit. The sensor wafer comprises a thermal oxide layer, a reflector, an aluminum oxide layer, a P-type heavily doped germanium layer, an intrinsic germanium sensing layer, an intrinsic germanium quantum well sensing layer, a P-type charge layer, an intrinsic germanium-silicon multiple avalanche layer, and an N-type heavily doped germanium layer which are sequentially stacked. The sensor wafer further comprises multiple rectangular trenches distributed at preset intervals. The passivation layer covers the N-type heavily doped germanium layer and inner walls of each rectangular trench. Each N-type electrode is disposed within a rectangular trench, and penetrates through the passivation layer to connect to the P-type heavily doped germanium layer. Each P-type electrode penetrates through the passivation layer to connect to the N-type heavily doped germanium layer. The readout circuit is separately connected to the N-type electrodes and the P-type electrodes. According to the present application, lattice mismatch defects can be removed, thereby reducing the dark current, dark count rate, and avalanche breakdown voltage of a sensor.

The present invention is a method for forming a thermal oxide film on a semiconductor substrate, including: a correlation acquisition step of providing a plurality of semiconductor substrates each having a chemical oxide film having a different constitution formed by cleaning, performing a thermal oxidization treatment under identical thermal oxidization treatment conditions to form a thermal oxide film, and determining a correlation between the constitution of the chemical oxide film and a thickness of the thermal oxide film in advance; a cleaning condition determination step of determining the constitution of the chemical oxide film based on the correlation obtained in the correlation acquisition step so that a thickness of a thermal oxide film to be formed on a semiconductor substrate is a predetermined thickness, and determining cleaning conditions for forming a chemical oxide film having the determined constitution of the chemical oxide film; a substrate cleaning step of cleaning the semiconductor substrate under the determined cleaning conditions; and a thermal oxide film formation step of performing a thermal oxidization treatment on the cleaned semiconductor substrate under conditions identical to the thermal oxidization treatment conditions in the correlation acquisition step to form a thermal oxide film on a surface of the semiconductor substrate. Consequently, a thermal oxide film is formed with the target film thickness with excellent reproducibility.

To provide a light-emitting device that can suppress breaking of the hermetic seal of a light-emitting element, and a manufacturing method thereof.SOLUTION: A light-emitting device includes: a first substrate 21 as a silicon substrate and a second substrate 22 as a silicon substrate bonded to an upper surface of the first substrate and having an opening exposing an area on the upper surface, a first insulating film 24 formed in another area other than one area on the upper surface of the first substrate being a thermally-oxidized film, a second insulating film 25 formed in the one area being an insulating film other than a thermally-oxidized film; a first upper surface electrode 31; a second upper surface electrode 32 formed on a second through-hole group in the one area; a light-emitting element 13 disposed across the first upper surface electrode and the second upper surface electrode on the one area; a first lower surface electrode 28 formed on a first through-hole group on a lower surface of the first substrate; a second lower surface electrode 29 formed on the second through-hole group on the lower surface of the first substrate; and a translucent member 15 with translucency bonded to an upper surface of the second substrate and sealing a space including the opening.SELECTED DRAWING: Figure 2

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

This invention discloses a semiconductor dielectric layer structure and its fabrication method. The semiconductor dielectric layer structure includes a semiconductor substrate, an epitaxial layer on the surface of the substrate, multiple trenches in the epitaxial layer, a thermal oxide layer on the surface of the epitaxial layer, in-situ doped polysilicon filling the trenches, a gate oxide layer formed between the in-situ doped polysilicon and the trenches, a silicon nitride layer on the surface of the thermal oxide layer adjacent to the trenches, a first deposited oxide layer on the surface of the silicon nitride layer, a second deposited oxide layer on the surface of the first deposited oxide layer, and a portion of the second deposited oxide layer, the silicon nitride layer, and the thermal oxide layer being hollowed out to form contact holes. The bottom end of the contact hole extends to the surface of the epitaxial layer, and the bottom edge of the contact hole extends to the in-situ doped polysilicon, exposing the gate oxide layer on the inner wall of the trench. The second deposited oxide layer and the gate oxide layer together form the sidewall structure of the in-situ doped polysilicon. This invention can prevent sharp corners of the semiconductor interface from being exposed due to contact hole etching.

The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps of: providing a silicon substrate, and pre-cleaning the silicon substrate; forming a high-temperature silicon oxide layer on the silicon substrate by adopting a low-pressure chemical vapor deposition method; the thermal oxide layer is formed at the interface of the silicon substrate and the high-temperature silicon oxide layer, hydrogen is used in the process of forming the thermal oxide layer, and H reacts with chlorine in the HTO thin film to generate HCl, so that the residual quantity of chlorine in the thin film is reduced, and the reliability and the performance of a device are improved.

To provide a light-emitting device that can suppress breaking of the hermetic seal of a light-emitting element, and a manufacturing method thereof.SOLUTION: A light-emitting device includes: a substrate structure 11 having a first substrate 21 comprising single-crystal silicon and including a first insulating film 24 that is a thermally-oxidized film formed on upper and lower surfaces thereof, and a second substrate 22 comprising single-crystal silicon, bonded to the upper surface of the first substrate 21, and having an opening exposing one area on the upper surface of the first substrate 21; a light-emitting element 13 disposed across a first upper surface electrode 31 and a second upper surface electrode 32 on the one area; and a translucent member 15 with translucency formed on an upper surface of the second substrate 22 and sealing a space including the opening. Respective <110> orientations of silicon crystals of the first substrate 21 and the second substrate 22 are offset from one another in a planar view from a direction perpendicular to the upper surface of the first substrate.SELECTED DRAWING: Figure 2

This invention provides a base plate for a substrate support assembly and a method for manufacturing the same, which minimize stress on the spray coating by modifying the dimensional design. [Solution] The base plate of a substrate support assembly for supporting a semiconductor substrate in a processing chamber comprises a first component made of a first material including metals and nonmetals. The first material has a first coefficient of thermal expansion (CTE). A layer coating the first component is made of a second material. The second material has a second coefficient of thermal expansion. The first and second coefficients of thermal expansion are different.

The patent relates to the technical field of investment precision casting, in particular to a casting method of high-temperature alloy hollow triad high-pressure guide vane, which comprises the following steps: S1: making a hollow triad high-pressure guide vane mold; S2: pressing a triad high-pressure guide vane model; S3: bonding a mold group; S4: making an oxide ceramic mold shell; S5: preheating the oxide ceramic mold shell; S6: pouring liquid metal; and S7: taking out the hollow triad high-pressure guide vane. The triad high-pressure guide vane model is prepared by using the whole pressing mode, compared with the mode that a single vane is pressed first and then is assembled and spliced into a triad vane, the model size consistency is better, the model deformation is smaller, the production efficiency is higher, and the cost is lower, and the problems of metallurgical defects, size out-of-tolerance and low qualified rate in the casting process of the high-temperature alloy hollow triad high-pressure guide vane are solved.

The invention particularly relates to a groove type integrated circuit chip and a preparation method thereof, the groove type integrated circuit chip comprises a plurality of uniformly arranged cellular structures, each cellular structure comprises a groove, and the upper part of each groove comprises control gate polycrystalline silicon and a gate oxide layer composed of a thermal oxide layer and a second gate oxide layer; the lower part comprises shield gate polycrystalline silicon, an ONO oxide layer and an isolation oxide layer; the ONO oxide layer sequentially comprises a thermal oxide layer, a silicon nitride layer and a CVD oxide layer from outside to inside; according to the invention, the gate oxide layer is composed of the thermal oxide layer and the second gate oxide layer, which can effectively control and reduce the expansion of the trench, and is helpful for further reducing the pitch and optimizing the RSP; meanwhile, the protection layer oxide layer is added in the technological process, the silicon nitride layer can be effectively protected from being torn in the IPO thermal oxidation process, the IDSS electric leakage problem is thoroughly solved, and the reliability of the chip is improved.

The invention discloses a shield gate trench type MOSFET manufacturing method for controlling IPO thickness, and relates to the technical field of semiconductors. Etching a groove on the epitaxial wafer, then filling photoresist, and exposing to the top of the groove; then performing wet etching on the side wall oxide layer to a specified depth; removing the photoresist; then, 100 to 400 thermal oxide layers are grown; the preparation method comprises the following steps of: depositing 100 to 400 percent of Nitride (Si3N4); depositing a thin oxide layer; depositing polycrystalline silicon; etching the polycrystalline silicon to a specified depth; carrying out thermal oxidation on the polycrystalline silicon to a specified thickness; performing wet etching on the thin oxide layer on the side wall of the groove; performing hot phosphoric acid etching on the thin Nitride on the side wall of the groove; performing wet etching on the thin oxide layer on the side wall of the groove; growing a gate oxide layer, and depositing gate polycrystalline silicon to form a gate electrode; and then completing subsequent processes such as body region injection and trap pushing, source electrode injection and annealing, interlayer dielectric deposition and the like according to a traditional process, and finally forming a complete structure of the shield gate type trench MOSFET. By means of the manufacturing method, the shield gate type trench MOSFET capable of accurately controlling the IPO thickness is formed, the technological parameter variables are few, the technology is simple, and the manufacturing cost is low.

This invention discloses a grate bar for a roasting trolley, comprising a chromium-nickel alloy substrate and a thermally sprayed composite coating deposited on its surface after a sealing treatment. The thermally sprayed composite coating comprises a CoNiCrAlY base layer and a CoCrAlYTa-based high-temperature gradient surface layer. The CoCrAlYTa-based high-temperature gradient surface layer comprises CoCrAlYTa and heat-resistant oxides, with the content of the heat-resistant oxides distributed in a gradient along the coating. This invention, using a chromium-nickel alloy substrate combined with a thermally sprayed composite coating, achieves a good balance of high-temperature wear resistance, resistance to impurity adhesion, high-temperature oxidation resistance, and erosion resistance, effectively extending its service life in belt-type roasting trolley operating systems and offering wide applicability.

The invention provides a deep trench isolation structure and a manufacturing method thereof, the deep trench isolation structure comprises a substrate and a strip-shaped structure formed by isolation of an isolation trench penetrating into the substrate, and the strip-shaped structure comprises a column body and protrusions arranged on the two sides of the column body in a staggered mode. The structural design of an original silicon column is changed, the protrusions are arranged on the two sides of the silicon column at intervals, the width of the DTI silicon column is increased equivalently through the protrusions, and the silicon column is prevented from falling or inclining laterally; furthermore, by controlling the relation between the height of the single-side protrusion and the thickness of the isolation thermal oxidation layer, it is ensured that the protrusion part is fully oxidized in the thermal oxidation process, and it is avoided that the silicon column falls down or inclines laterally, and filling of the isolation groove with the follow-up filling material is not affected. In addition, according to the deep trench isolation structure provided by the invention, the space size of the original design is not changed, the size of a DTI silicon column is not increased, and the total size of the isolation structure is reduced.

This invention provides a method for improving gate-source leakage current. The method includes: providing a base structure comprising a trench, a first dielectric layer, and a first conductive material, wherein the top surface of the first conductive material is lower than the trench opening; thermally oxidizing the base structure; growing a second dielectric layer on the exposed surface of the first conductive material; wet etching the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the rate difference between the second and first dielectric layers in the etching solution; and depositing a third dielectric layer to fill the trench after wet etching. This invention improves the morphology of the field oxide layer after etching back through the protective effect of the thermal oxide layer, eliminates the potential for voids during subsequent dielectric filling, prevents leakage failure due to thin insulation, and significantly improves the consistency of the gate-source leakage current and its yield performance.