60 results about "Thermal oxide" patented technology

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.

[Problem] To provide a polishing end point detection device and method, and a CMP device capable of accurately detecting a polishing end point when polishing a workpiece having a thin film thickness. [Solution] A polishing end point detection device (70) is provided with: a measurement unit (71) that, during polishing of a workpiece (W), radiates measurement light onto the workpiece (W), disperses reflected light from the workpiece (W), and acquires a spectral waveform indicating the relationship between the wavelength and reflectance of the reflected light; the reflectivity is the ratio of the intensity of the reflected light to the reference intensity of each wavelength component obtained in advance; and a detection unit (72) that calculates the film thickness of the thermal oxide film by applying Fourier analysis to the spectral waveform. The reference intensity is calculated by bringing a sample workpiece having substantially the same reflectance characteristic as a substrate of a workpiece (W) into contact with a polishing pad (5) in a state where a CMP slurry is interposed between the polishing pad (5) and the sample workpiece, and irradiating the sample workpiece with measurement light through an observation window (80) of the polishing pad (5) by a measurement unit (71). And the reflected light from the sample workpiece is split.

The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method capable of reducing leakage and shrinking a keep out zone.The semiconductor device includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip and provided with a PN junction portion in a depth direction by forming an N-type well on a front surface of a substrate of P-type or forming a P-type well on a front surface of a substrate of N-type, and a through electrode provided in a through hole penetrating the substrate. The through electrode is configured such that a ferroelectric film or a thermal oxide film having an insulating property for at least the PN junction portion is provided along an inner wall surface of the through hole. The present technology can be applied to, for example, a stacked CMOS image sensor.

The invention discloses a multi-time programmable memory device for controlling short circuit and a preparation method thereof, and relates to the field of semiconductors, the multi-time programmable memory device comprises a substrate, the surface of the substrate is provided with an epitaxial layer, and a buried oxide layer is arranged between the substrate and the epitaxial layer; a tunneling layer and a floating gate region are sequentially arranged at one end, far away from the buried oxide layer, of the epitaxial layer, and an insulating layer is deposited on the surface of the floating gate region; two sides of the floating gate region are respectively provided with a first groove and a second groove, and thermal oxide layers are formed in the first groove and the second groove; a control gate region is deposited on the surface, away from the tunneling layer, of the insulating layer, and a thin film oxide layer is deposited on the surface, close to the control gate region, of the multi-time programmable memory device for controlling short circuit; a drain region is formed in the first groove, and a source region is formed in the second groove; the surface of the drain region forms a cathode, and the surface of the source region forms an anode. According to the invention, the condition of short circuit between the control gate region and the floating gate region under the condition of long-time high-voltage programming is effectively avoided, and the service life of the storage unit is prolonged.

The utility model relates to the field of tail gas treatment, and discloses a liquid-containing industrial carbon monoxide waste gas treatment device which comprises a heat exchanger, a liquid separation tank, a wire mesh demister and an RTO combustion furnace which are sequentially connected in series through pipelines, and a diluent introduction pipeline is connected between the wire mesh demister and the RTO combustion furnace. Liquid-containing industrial carbon monoxide waste gas is cooled through the heat exchanger and then passes through the liquid separation tank and the wire mesh demister to obtain high-concentration carbon monoxide waste gas, a diluent is introduced through the diluent introduction pipeline to dilute the high-concentration carbon monoxide waste gas, and then the high-concentration carbon monoxide waste gas enters the RTO combustion furnace to be subjected to combustion treatment. The liquid-containing industrial carbon monoxide waste gas treatment device provided by the utility model can effectively solve the potential safety hazard in the industrial production process and ensure the safe operation of the industrial production.

Aspects of the present disclosure are directed to an apparatus including a circuit region and a fluidic region. In a particular example, the circuit region with logical circuits thereon, includes a thermal oxide layer on a silicon substrate, and a dielectric layer over the field oxide layer, the dielectric layer including a doped dielectric film. The microfluidic device further includes a fluidic region including fluid ports formed through a surface of the apparatus and including an un-doped dielectric film. The fluidic region includes an aperture in the dielectric layer, where the aperture is defined by a dielectric wall which forms part of the dielectric layer. A sealing film deposited over the dielectric wall may prevent the doped dielectric film from contacting fluid contained in the fluid port.

The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.

To provide a method for measuring the resistivity of a silicon single crystal, with which a precise resistivity derived from a dopant can be measured for a silicon single crystal with resistivity of 100 Ω cm or higher, the silicon single crystal being grown with addition of nitrogen by a MCZ method.SOLUTION: There is provided a method for measuring the resistivity of a silicon single crystal with resistivity of 100 Ω cm or higher, the silicon single crystal being grown with addition of nitrogen by an MCZ method. The method includes: performing oxidation heat treatment at a temperature of 1,100 to 1,250°C for 90 to 240 minutes on a substrate sliced from the silicon single crystal to form a thermal oxide film on a surface of the substrate; and measuring the resistivity of the substrate after removing the thermal oxide film from the surface of the substrate.SELECTED DRAWING: Figure 1

The invention relates to a PZT target material and a preparation process thereof, and relates to the technical field of PZT target materials. The preparation process of the PZT target material comprises the following steps: preparing an SOI silicon wafer; selecting a silicon wafer or a silicon-on-insulator wafer as a substrate; silicon wafer doping: doping silicon on the surface of the silicon wafer; depositing an insulating layer: growing a thermal oxide layer or a chemical vapor deposition SiNx layer on the surface, doped with silicon, of the silicon wafer to serve as the insulating layer; depositing a lower electrode layer; a PZT piezoelectric layer is deposited, specifically, radio frequency magnetron sputtering is conducted on the lower electrode layer at the sputtering temperature (500-600 DEG C), the deposition rate is 35-48 nm / min, and the PZT piezoelectric layer is formed; after sputtering, keeping the annealing temperature of 465 DEG C in the chamber and annealing for 5 minutes; etching the PZT piezoelectric layer; etching the lower electrode layer; depositing a top layer; etching the insulating layer; depositing a top layer electrode; etching the top layer silicon; and etching the bottom silicon and the silicon dioxide. The method has the effect of ensuring the piezoelectric property of the prepared PZT target material.

This invention discloses a heterogeneous integrated electro-optic modulator and its alignment method based on write field splicing compensation, relating to the field of silicon-based optoelectronics technology. The modulator comprises, from bottom to top, a silicon substrate with a thermal oxide layer, a bottom patterned waveguide layer, an intermediate transition dielectric layer, a top electro-optic thin film layer, and a top traveling-wave electrode structure. The bottom waveguide layer has a write field splicing region along the light propagation direction, within which a thermal compensation structure is configured, and a dedicated alignment mark is provided within a designated area. This mark is formed synchronously with the waveguide layer and the compensation structure within the same photolithographic write field. The top traveling-wave electrode structure is overlaid across layers based on this mark, forming a predetermined spatial matching relationship with the write field splicing region. This invention can solve the problems of optical scattering loss caused by long-distance bottom waveguide field-separated exposure splicing and the limited accuracy of cross-layer overlay after heterogeneous bonding, and achieves precise overlay positioning of the cross-layer traveling-wave electrode.

To provide a liquid-repellent member with excellent water-repellent performance and oil-repellent performance, and a method for producing the same.SOLUTION: A liquid-repellent member with a liquid-repellent surface on its surface comprises a metal member, and a liquid-repellent layer composed of a liquid-repellent material, the metal member having a thermal oxide film, and the liquid-repellent material containing at least either of a fluorine-containing compound and a silicon-containing compound. The thermal oxide film has a predetermined macro uneven portion on its surface and also has fine irregularities on a surface of the macro uneven portion. A method for producing the liquid-repellent member comprises: a thermal oxide film forming step for forming a predetermined thermal oxide film on a surface of a metal base that forms a metal member by a laser treatment of irradiating the film with laser beams; and a liquid-repellent layer forming step for forming a liquid-repellent layer on the outermost surface of the metal member by applying a liquid-repellent material to the thermal oxide film.SELECTED DRAWING: Figure 1

The present invention provides a method for preparing a device structure of an SGT MOS tube, the method comprising: sequentially forming a first thermal oxide layer, an isolation layer, and a trench oxide layer on the surface of an epitaxial layer and on the sidewalls of a first groove of the epitaxial layer; thinning the thickness of the first thermal oxide layer while meeting the thickness requirements of the trench sidewall oxide layer to reduce consumption of the epitaxial layer, thereby improving the voltage resistance of the SGT tube; depositing a first polysilicon layer in a groove formed by the trench oxide layer, and removing a portion of the trench oxide layer in the first groove; because the isolation layer is provided, an inter-gate oxide layer on the surface of the protruding portion of the first polysilicon layer can be formed to the required thickness, thereby reducing the gate-source capacitance of the SGT tube; depositing a second polysilicon layer and performing a first ion implantation and a second ion implantation on the epitaxial layer on both sides of the first groove; depositing an interlayer dielectric layer on the substrate to complete the preparation of the device structure.

Method for producing a semiconductor silicon wafer, which is composed of a silicon wafer substrate and a monocrystalline epitaxial silicon layer on it, comprising: a step (S2) of forming a silicon oxide layer with a thickness of at least 300 nm or thicker only on the back side of the silicon wafer substrate by the CVD process at a temperature of not more than 500 °C, wherein the silicon wafer substrate is produced from a monocrystalline silicon ingot grown by the Czochralski process, is doped with phosphorus, has a resistivity set to not more than 1.05 mΩ·cm, and a solid solution oxygen concentration of not more than 0.9×10 18 atoms / cm² 3 exhibits and on whose front surface a monocrystalline epitaxial silicon layer is to be formed; a heat treatment step (S4) after the step of forming the silicon oxide layer, in which the substrate is held in an oxidizing atmosphere at a constant temperature of at least 1100 °C and at most 1250 °C for at least 30 minutes and at most 120 minutes; a step (S5) of removing the surface oxide layer, which is formed as a thermal oxide layer on the front surface of the substrate during the heat treatment step, after the heat treatment step; and a step of depositing a monocrystalline epitaxial silicon layer on the substrate after the step of removing the surface oxide layer.

The application discloses a structure for improving the reliability of a vertical power device, wherein a trench gate penetrating a channel region and a source region formed on the surface of the channel region are arranged in a device unit region, a second trench structure penetrating the channel region is arranged in a terminal region, a first thermal oxide layer covers all regions of the terminal region and the device unit region, in the terminal region, the first thermal oxide layer is directly used to perform thermal oxidation on the material of a first epitaxial layer and the material of a second conductive material layer, in the device unit region, the first thermal oxide layer is directly used to perform thermal oxidation on the material of the first epitaxial layer and the material of a gate conductive material layer, the interface characteristics between the material of the first thermal oxide layer and the first epitaxial layer and the continuous extension structure of the first thermal oxide layer without etching are used to improve the reliability of the vertical power device. The application further discloses a manufacturing method of the structure for improving the reliability of the vertical power device. The application can improve the reliability and reduce the process cost.

A method of manufacturing a gate-all-around electronic device is described. The method includes forming a thermal oxide layer by enhancing in-situ steam generation processing in combination with atomic layer deposition of a low-K layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the gate-all-around (GAA). The passivation processing after deposition of the low-K layer reduces bulk traps and enhances the breakdown performance of the GAA transistor.

To provide a method for evaluating a silicon single crystal wafer, which is useful for suppressing the occurrence of dislocation at a place where a Line & Space pattern is formed.SOLUTION: Forming a plurality of L & S patterns on a surface of the Si single crystal wafer by a SiN film while changing a formation direction of the L & S patterns, forming a thermal oxide film on a surface of the Si single crystal wafer on a side where the L & S patterns are formed, performing a first process of removing the thermal oxide film, and performing a second process of visualizing dislocations existing at a formation position of the L & S patterns as dislocation pits by selective etching; The evaluation method of the Si single crystal wafer includes a process of measuring the density of dislocation pits for each L & S pattern, and a process of determining and evaluating the formation direction of the L & S pattern having the lowest density of dislocation pits as the optimum formation direction from the measurement result.SELECTED DRAWING: Figure 1

The present invention is a method for measuring the resistivity of a single crystal silicon having a resistivity of 100 [Omega] cm or more grown by adding nitrogen by the MCZ method, characterized in that: a substrate cut from the single crystal silicon is subjected to an oxidation heat treatment at a temperature of 1100-1250 DEG C for 90-240 minutes to form a thermal oxide film on the surface of the substrate; after the thermal oxide film is removed from the surface of the substrate, the resistivity of the substrate is measured. As a result, provided is a method for measuring the resistivity of a single crystal silicon with which it is possible to measure the accurate resistivity derived from a dopant on a single crystal silicon having a resistivity of 100 [Omega] cm or more grown by adding nitrogen by the MCZ method.

A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.

A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.

The invention provides a preparation process of a groove type silicon carbide gate oxide layer, a groove type silicon carbide wafer with a gate oxide layer and a metal oxide semiconductor field effect transistor. The method comprises the following steps of: depositing and growing a thin oxide layer after etching a groove, depositing polycrystalline silicon, filling the whole groove with the polycrystalline silicon, only reserving the polycrystalline silicon at the bottom of the groove by adopting a polycrystalline silicon back-etching process, and finally performing a thermal oxidation process. Silicon carbide is oxidized in a high-temperature oxygen atmosphere, and polycrystalline silicon at the bottom of the groove is oxidized into an oxide layer; the method not only can ensure that a layer of high-quality thermal oxide is generated on the side wall of the trench as a gate oxide layer, but also can realize that the oxide layer formed by oxidation of polycrystalline silicon at the bottom of the trench is thicker than the oxide layer on the side wall of the trench, thereby improving the voltage endurance capability of the bottom of the trench device.

This invention provides a method for preparing a standard silicon wafer and a method for calibrating a planarity measurement device, comprising: providing a silicon wafer; performing a first heat treatment on the silicon wafer to grow an oxide layer on the surface of the silicon wafer; and performing a second heat treatment on the silicon wafer after the oxide layer has grown to improve the surface roughness of the oxide layer through a high-temperature decomposition reaction; wherein the first heat treatment includes: heating to a first heat treatment temperature and maintaining the first heat treatment time in an atmosphere containing oxygen; the second heat treatment includes: heating to a second heat treatment temperature and maintaining the second heat treatment time in an atmosphere containing argon. The preparation method provided by this invention, by combining a two-step process of "thermal oxidation growth" and "high-temperature decomposition and reconstruction," creates a standard wafer surface that possesses both the purity of the thermal oxide layer and the specific and uniform surface roughness obtained through high-temperature decomposition, meeting the stringent calibration requirements of non-contact planarity measurement devices that are extremely sensitive to cleanliness.

Provided is a method for determining a cleaning condition for a semiconductor wafer, the method being capable of satisfactorily controlling the thickness of a thermal oxide film. A method for determining a cleaning condition of a semiconductor wafer according to the present invention comprises: a step for determining a cleaning correlation between a cleaning condition and the thickness and surface state of a chemical oxide film formed on each surface of a plurality of semiconductor wafers after a cleaning step; a step in which, for each of the one or more heat treatment conditions, the heat treatment correlation between the amount of increase in the thickness of the oxide film after the heat treatment step and the thickness and surface state of the chemical oxide film after the heat treatment step is determined for the thermal oxide film formed on the surface of each of the plurality of semiconductor wafers after the heat treatment step; a step for determining a heat treatment condition in the heat treatment step, and determining a target thickness of a thermal oxide film formed on the surface of the semiconductor wafer in the heat treatment step under the determined heat treatment condition; and a step for determining a cleaning condition under which the thickness of a thermal oxide film formed on the surface of the semiconductor wafer in the heat treatment step under the determined heat treatment condition becomes the target thickness.

A base plate of a substrate support assembly for supporting a semiconductor substrate in a processing chamber includes a first component made of a first material including a metal and a non-metal. The first material has a first coefficient of thermal expansion. A layer coating the first component is made of a second material. The second material has a second coefficient of thermal expansion. The first and second coefficients of thermal expansion are different.

A micro-electro-mechanical (MEMS) device is provided that includes a fixed body delimiting a cavity; a suspended structure extending cantilevered from the fixed body, above the cavity, and including a suspended semiconductive region; and a transducer arranged above the suspended structure. The suspended structure further includes a compensation region of thermal oxide, which extends below the suspended semiconductive region. A method of manufacturing a MEMS device is also provided.

A method for manufacturing a SiC semiconductor device (10), comprising the steps of: providing a SiC substrate (20) having a SiC epitaxial layer (30) thereon, treating the SiC epitaxial layer (30) with plasma immersion ion implantation (PIII) using dopants of a first material (35). The method further comprises thermally oxidizing a top surface (31) of the SiC epitaxial layer (30) to grow a thermal oxide layer (40), and etching the thermal oxide layer (40). The method further comprises implanting dopants of a second material (36) into the SiC epitaxial layer (30) to create a drain (50) and a source (60), activating the dopants with an activation anneal, and depositing a metal gate (70).

The application discloses a preparation method of a low-leakage mesa structure SiC phototransistor, which comprises the following steps: standard cleaning of a SiC epitaxial wafer; alignment mark etching of the epitaxial wafer, then photoetching to form a mask film, ion implantation, thermal annealing, formation of a P + region; photoetching to form a mask etching film, mesa formation by using inductive coupling plasma technology; passivation of the obtained SiC epitaxial wafer; specifically comprising growth of a sacrificial oxide layer, removal of the sacrificial oxide layer by using a BOE solution and then growth of a thermal oxide layer, then PECVD of a 1-micron oxide layer; preparation of a back electrode, formation of an n-type ohmic contact by electron beam evaporation of a metal Ni electrode; preparation of a front electrode, formation of an ohmic contact by electron beam evaporation of Ni / Ti / Al / ni / Au, finally evaporation of Al to form a wire bonding area, and obtaining of a SiC novel phototransistor. + By ion implantation of a P + region at the edge of the mesa SiC NPN device, the gain value at the edge of the device is greatly reduced, and the purpose of reducing the leakage of the device is achieved.

The present invention is a method for manufacturing an epitaxial wafer by forming a single-crystal silicon layer on a single-crystal silicon wafer via an oxygen-atom layer, the method including the steps of removing a native oxide film, forming a thermal oxide film on a surface of the single-crystal silicon wafer from which the native oxide film has been removed, thinning the thermal oxide film, and after thinning the thermal oxide film, epitaxially growing single-crystal silicon to form an epitaxial wafer in which the single-crystal silicon layer is formed on the single-crystal silicon wafer via the oxygen-atom layer. This provides the method for manufacturing an epitaxial wafer, in which, when manufacturing a silicon epitaxial wafer, the oxygen-atom layer can be introduced into an epitaxial layer stably and easily.

This invention provides a waveguide wafer, a composite modulator, and a method for fabricating the same, relating to the field of electro-optic modulation devices. The waveguide wafer includes: a SiO2 thermal oxide layer on the top surface of a silicon substrate; a first SiO2 cladding layer on the top surface of the SiO2 thermal oxide layer; a waveguide structure within the first SiO2 cladding layer; metal electrodes within the first SiO2 cladding layer and the SiO2 thermal oxide layer; a bonding interface located on the top surface of the first SiO2 cladding layer above the waveguide structure; the SiO2 thickness between the bonding interface and the top surface of the waveguide structure is a preset thickness; the bonding interface is treated to a preset flatness and protected by a sacrificial layer to prevent over-etching during the etching of the second SiO2 cladding layer; the sacrificial layer is removed after the second SiO2 cladding layer is etched; the second SiO2 cladding layer, after etching, is located on the top surface of the first SiO2 cladding layer, excluding the bonding interface. This method can obtain a bonding interface with controllable thickness and a flat surface.

The present subject matter relates to systems and methods for producing a MOSFET by applying a nitridation pre-treatment (e.g., plasma or thermal) directly on a silicon carbide surface. The nitridation pre-treatment can be followed by a deposited gate oxide. In this way, instead of using a thermal oxide and a thermal nitrogen oxide anneal, nitrogen is introduced at the interface to passivate traps without any thermal oxidation of the silicon carbide. In addition, the post-anneal step can be performed, resulting in an improvement in mobility.