6 results about "Thermal oxide" patented technology

This invention discloses a heterogeneous integrated electro-optic modulator and its alignment method based on write field splicing compensation, relating to the field of silicon-based optoelectronics technology. The modulator comprises, from bottom to top, a silicon substrate with a thermal oxide layer, a bottom patterned waveguide layer, an intermediate transition dielectric layer, a top electro-optic thin film layer, and a top traveling-wave electrode structure. The bottom waveguide layer has a write field splicing region along the light propagation direction, within which a thermal compensation structure is configured, and a dedicated alignment mark is provided within a designated area. This mark is formed synchronously with the waveguide layer and the compensation structure within the same photolithographic write field. The top traveling-wave electrode structure is overlaid across layers based on this mark, forming a predetermined spatial matching relationship with the write field splicing region. This invention can solve the problems of optical scattering loss caused by long-distance bottom waveguide field-separated exposure splicing and the limited accuracy of cross-layer overlay after heterogeneous bonding, and achieves precise overlay positioning of the cross-layer traveling-wave electrode.

This invention provides a method for preparing a standard silicon wafer and a method for calibrating a planarity measurement device, comprising: providing a silicon wafer; performing a first heat treatment on the silicon wafer to grow an oxide layer on the surface of the silicon wafer; and performing a second heat treatment on the silicon wafer after the oxide layer has grown to improve the surface roughness of the oxide layer through a high-temperature decomposition reaction; wherein the first heat treatment includes: heating to a first heat treatment temperature and maintaining the first heat treatment time in an atmosphere containing oxygen; the second heat treatment includes: heating to a second heat treatment temperature and maintaining the second heat treatment time in an atmosphere containing argon. The preparation method provided by this invention, by combining a two-step process of "thermal oxidation growth" and "high-temperature decomposition and reconstruction," creates a standard wafer surface that possesses both the purity of the thermal oxide layer and the specific and uniform surface roughness obtained through high-temperature decomposition, meeting the stringent calibration requirements of non-contact planarity measurement devices that are extremely sensitive to cleanliness.

A micro-electro-mechanical (MEMS) device is provided that includes a fixed body delimiting a cavity; a suspended structure extending cantilevered from the fixed body, above the cavity, and including a suspended semiconductive region; and a transducer arranged above the suspended structure. The suspended structure further includes a compensation region of thermal oxide, which extends below the suspended semiconductive region. A method of manufacturing a MEMS device is also provided.

The present invention is a method for manufacturing an epitaxial wafer by forming a single-crystal silicon layer on a single-crystal silicon wafer via an oxygen-atom layer, the method including the steps of removing a native oxide film, forming a thermal oxide film on a surface of the single-crystal silicon wafer from which the native oxide film has been removed, thinning the thermal oxide film, and after thinning the thermal oxide film, epitaxially growing single-crystal silicon to form an epitaxial wafer in which the single-crystal silicon layer is formed on the single-crystal silicon wafer via the oxygen-atom layer. This provides the method for manufacturing an epitaxial wafer, in which, when manufacturing a silicon epitaxial wafer, the oxygen-atom layer can be introduced into an epitaxial layer stably and easily.

This invention provides a method for improving gate-source leakage current. The method includes: providing a base structure comprising a trench, a first dielectric layer, and a first conductive material, wherein the top surface of the first conductive material is lower than the trench opening; thermally oxidizing the base structure; growing a second dielectric layer on the exposed surface of the first conductive material; wet etching the first dielectric layer, wherein the second dielectric layer protects the first dielectric layer on the side of the first conductive material from excessive lateral etching by utilizing the rate difference between the second and first dielectric layers in the etching solution; and depositing a third dielectric layer to fill the trench after wet etching. This invention improves the morphology of the field oxide layer after etching back through the protective effect of the thermal oxide layer, eliminates the potential for voids during subsequent dielectric filling, prevents leakage failure due to thin insulation, and significantly improves the consistency of the gate-source leakage current and its yield performance.

This invention provides a method for manufacturing a composite film layer and a flash memory device to improve flash memory read interference. The method includes: providing a semiconductor substrate with a floating gate; depositing a first oxide layer on the surface of the floating gate; performing rapid thermal annealing on the first oxide layer in a nitrogen-containing atmosphere to densify the first oxide layer and grow a thermal oxide layer between the floating gate and the first oxide layer; and sequentially depositing a charge trapping layer and a second oxide layer on the surface of the first oxide layer. This invention utilizes a deposition-annealing process to remove impurities while growing a high-quality thermal oxide layer at the interface, effectively reducing the consumption of polysilicon for the floating gate, avoiding pitting defects and plasma damage, and significantly improving the read interference characteristics of the flash memory.