127 results about "Carrier lifetime" patented technology

The invention relates to the technical field of organic compound solar cells, and provides a large-size perovskite assembly pre-illumination synergistic aging test system and method, and the system comprises a light attenuation subsystem, a current-voltage test subsystem, and a control and region light supplement array subsystem. The method comprises the following steps: the light attenuation subsystem obtains the physical and chemical state change of the perovskite component through processing dual-band cooperative irradiation; the current-voltage test subsystem calculates the variance of the carrier lifetime to obtain a performance uniformity evaluation result of the perovskite assembly; a performance uniformity evaluation result forms a PID algorithm output signal through the control subsystem; the control subsystem processes a PID algorithm output signal to obtain an LED intensity adjusting signal for each light supplementing area; lED intensity adjusting signals pass through the area light supplementing array subsystem to form a uniform illumination environment, and a compensated perovskite component surface light field is obtained. According to the invention, a multi-parameter coupled accelerated aging platform is provided for the reliability research of the perovskite component.

The embodiment of the invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the steps of providing a substrate; the substrate is provided with a first surface and a second surface which are arranged oppositely; forming a passivation layer on at least one side of the first surface and the second surface of the substrate; under a normal temperature condition, carrying out first light treatment by adopting a light beam with a first wavelength; the minority carrier lifetime in the substrate after the first light treatment is greater than or equal to 2000 [mu] s.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region and a second region which are sequentially distributed; the first region is adjacent to the first surface and the second region is adjacent to the first region. The second region is recessed into the silicon substrate by a first distance relative to the first region; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface; the second surface comprises groove regions and doped regions which are alternately arranged, and the groove regions are recessed towards the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region; wherein the first distance is greater than or equal to the second distance.

The invention belongs to the technical field of solar cells, and particularly discloses a texturing additive, a texturing solution and a texturing method of a back contact cell. The texturing additive for the back contact battery comprises the following components in percentage by mass: 1.0%-5.0% of sodium carboxymethyl cellulose, 0.03%-0.2% of sodium lignin sulfonate, 0.003%-0.03% of paeoniflorin, 0.005%-0.05% of salvianolic acid B, 0.001%-0.01% of polyhexamethylene biguanide hydrochloride, 0.3%-1.0% of a buffering agent, 0.01%-0.1% of a surfactant and the balance of water. The components interact with each other, and the texturing additive is added into the texturing liquid to improve the flatness of the texturing surface and effectively solve the problem that the texturing surface is not fully distributed, so that the minority carrier lifetime and the open voltage of the back contact battery are improved, and the photoelectric conversion efficiency of the battery is improved.

The invention relates to the technical field of solar cells, in particular to a preparation method of a single-wave precisely doped N-type BC cell. The invention discloses a preparation method of a single-wave precisely doped N-type BC battery. The preparation method comprises the following steps: S1, pre-treating an N-type silicon wafer; s2, performing boron doping on the front surface of the silicon wafer by adopting infrared single-wavelength laser to form a P + shallow junction; performing phosphorus doping on the back surface of the silicon wafer by adopting ultraviolet single-wavelength laser to form an N + region; s3, carrying out single-frequency microwave annealing treatment; s4, preparing a tunneling oxide layer, a boron-doped polycrystalline silicon passivation layer and a surface laminated passivation film; s5, carrying out laser grooving and copper electrode electroplating; s6, cutting the edge of the silicon wafer by adopting single-wavelength femtosecond laser; and S7, low-temperature annealing treatment. According to the method, the doping accuracy is improved, the service life of N-type silicon wafer carriers is ensured, the carrier recombination loss is remarkably reduced, the contact resistance and edge recombination loss is reduced, and the filling factor and the conversion efficiency of the cell are improved.

The application discloses a photovoltaic silicon monocrystal wafer group, a crystal column group, a photovoltaic cell and a photovoltaic module. The wafer group comprises rectangular silicon wafers cut from the middle of a base circle silicon wafer and axisymmetric non-rectangular polygonal silicon wafers symmetrically cut from the periphery of the rectangular silicon wafers. The cutting size of the rectangular silicon wafers is determined according to the distribution of vacancy-type point defect density C V and interstitial-type point defect density C I of the base circle silicon wafer and the distribution of minority carrier lifetime in different radial regions of the base circle silicon wafer, so that the rectangular silicon wafers are located in the region of C V ‑ C I ≥0, and the ratio d of the distance between the four corners of the rectangular silicon wafer and the minimum point of the minority carrier lifetime in the edge region of the base circle silicon wafer to the diameter of the base circle silicon wafer is 2%≤d≤8%. The method is based on the quality distribution rule of the silicon wafer to divide the silicon wafers into two types, and different cell processes are adopted to fully tap the potential of each type, so that the area utilization rate of the base circle silicon wafer is more than 90% while high-quality photovoltaic modules are obtained.

This application provides a passivation structure and its preparation method, as well as a silicon solar cell and its preparation method. The passivation structure includes a first aluminum oxide layer, a first aluminum nitride layer, a second aluminum oxide layer, and a second aluminum nitride layer stacked together. The first aluminum oxide layer directly contacts the silicon edge and repairs cutting damage and dangling bonds through chemical passivation. It adapts to the p-type silicon region with a negative fixed charge. The first aluminum nitride layer passivates the n-type silicon with a positive fixed charge. The high hydrogen content enhances defect repair, and the dense structure blocks impurities from intruding. The second aluminum oxide layer supplements the negative charge to improve the passivation effect of the p-type silicon and forms stress complementarity with the aluminum nitride layer to prevent film cracking. The second aluminum nitride layer resists stringing and lamination damage, blocks moisture and corrosion, and ensures long-term performance. This structure achieves optimal simultaneous passivation of p / n-type silicon through charge complementarity and synergistic hydrogen passivation, improving the minority carrier lifetime at the cell edge, the implicit open-circuit voltage, and the module power, and solving the pain points of incomplete passivation and poor stability.

The invention relates to the technical field of photovoltaic cells and materials thereof, and discloses a crystalline silicon wafer for preparing a crystalline silicon photovoltaic cell, a silicon ingot and a laminated photovoltaic cell. The crystal silicon wafer has one of the following characteristics: 1) the crystal silicon wafer is a lithium crystal silicon wafer of lithium-doped silicon; and 2) the crystal silicon wafer is an alloy crystal silicon wafer, the alloy crystal silicon wafer comprises a substrate, an alloy area containing silicon, tin and germanium alloy elements is locally prepared on the substrate, the alloy crystal silicon wafer is formed, and the alloy area of the alloy crystal silicon wafer comprises the following alloy elements in percentage by atomic number: 5-53% of silicon, 2-12% of tin and the balance of germanium. Compared with the prior art, the current output potential is improved, the photoelectric conversion efficiency is improved, lithium in the lithium crystal silicon wafer effectively passivates defects in crystalline silicon, the minority carrier lifetime of the crystalline silicon is prolonged, the mobility of the crystalline silicon is improved, a better lithium interface passivation effect is achieved, and the function of resisting the ultraviolet induced degradation effect is achieved.

The invention discloses a silicon carbide epitaxial wafer for inhibiting irradiation induced defects, a preparation method and application, and belongs to the technical field of semiconductor materials, the silicon carbide epitaxial wafer comprises an n-type or p-type silicon carbide wafer as a substrate, and an epitaxial layer doped with group IV atoms is epitaxially grown on the substrate. The preparation method comprises the following steps: cleaning an n-type or p-type silicon carbide wafer; placing the cleaned silicon carbide wafer in epitaxial growth equipment and keeping a vacuum environment; raising the temperature of the vacuum environment, and introducing monosilane, propane, nitrogen / hydrogen carrying trimethyl aluminum and gas containing at least one atom of germanium, tin and lead after the temperature is stable; and growing an epitaxial layer on the silicon carbide wafer. The silicon carbide epitaxial wafer is used for producing an anti-radiation silicon carbide power device. According to the invention, generation of carbon vacancies in a silicon carbide device in an irradiation process and minority carrier lifetime degradation caused by the generation of the carbon vacancies can be effectively inhibited, so that the reliability of the silicon carbide epitaxial wafer and a power device thereof under particle irradiation application is improved.

Device for controlling at least one light-emitting diode (LED1) to generate short light pulses (LP),- with an H-bridge (H) consisting of a first half-bridge (HB1: T1, T2) with a first transistor (T1) and a second transistor (T2) and a second half-bridge (HB2: T2, T3) with a third transistor (T3) and a fourth transistor (T4),- wherein the H-bridge (H) is controlled by a control unit (ST) and- wherein the H-bridge (H) can be operated by the control unit (ST) in pulsed mode (GPB) and in quasi-continuous mode (QDB) and- wherein the first half-bridge (HB1: T1, T2) is supplied with electrical energy from a first positive supply voltage (VCC1) and a first negative supply voltage (GND1) and- wherein the second half-bridge (HB2: T3,T4) is supplied with electrical energy from a second positive supply voltage (VCC2) and a second negative supply voltage (GND2) and- wherein the light-emitting diode (LED1) is connected with its cathode (K) to the output of the first half-bridge (HB1: T1, T2) and- wherein the light-emitting diode (LED1) is connected with its anode (A) to the output of the second half-bridge (HB2: T3, T4) and- wherein the first positive supply voltage (VCC1) and the second positive supply voltage (VCC2) can be equal and- wherein the first negative supply voltage (GND1) and the second negative supply voltage (GND2) can be equal and- wherein the light source, in particular the one or more light-emitting diodes (LED1), represents the load of the H-bridge (H) between the output of the first half-bridge (HB1: T1, T2) and the output of the second half-bridge (HB2: T3, T4) and- wherein the control device (ST) is designed to operate in pulsed mode (GPB) a “PAn” condition,in which a forward voltage in the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a turn-on time (τpp), and- wherein the control device (ST) is designed so that in pulsed operation (GPB) a "PAus" state, in which a reverse voltage against the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a clearing time (τpn), and- wherein the clearing time (τpn) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1), and- wherein the turn-on time (τpp) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1).

The invention provides a photoconductive switch of a comb electrode, which comprises a semi-insulating gallium arsenide substrate layer, a low-temperature gallium arsenide layer and an insulating protective layer, and is characterized in that the low-temperature gallium arsenide layer is formed on the semi-insulating gallium arsenide substrate layer, and the insulating protective layer is arranged on the low-temperature gallium arsenide layer; a switch anode and a switch cathode are respectively formed on the inner side of the low-temperature gallium arsenide layer surface insulation protection layer; a comb-shaped electrode is arranged on the surface of the low-temperature gallium arsenide layer and located at the switch anode. According to the invention, by arranging the comb-shaped electrode structure, a plurality of comb-tooth electrodes which are distributed in a staggered manner are formed in the electrode region, so that the action area of incident light and a semiconductor active region is increased under an illumination condition, and generation and collection of photon-generated carriers are facilitated; meanwhile, the distribution state of an electric field near the electrode is improved, and the possibility of local electric field concentration is reduced; in addition, a low-temperature gallium arsenide material is adopted as the photoconductive layer, the service life of a current carrier is short, and the device is suitable for photoelectric trigger application scenes with requirements for response speed and stability.

The utility model discloses back contact solar cell and photovoltaic module. The back light surface of back contact solar cell forms the P area, N area and the interval area between both of them of alternate distribution, the back light surface includes central region and edge area, the area ratio of N area in central region is less than the area ratio of N area in edge area, the area ratio of interval area in central region is greater than the area ratio of interval area in edge area. Therefore, can enhance the edge passivation effect of back contact solar cell to prolong the minority carrier lifetime of edge area, reduce the recombination loss of edge area, improve the passivation uniformity of battery whole, and then be favorable to the promotion battery's efficiency.

The invention discloses a wide-band-gap perovskite solar cell and a full-perovskite laminated solar cell. Methyl ammonium bromide and guanidine bromide are jointly doped into the perovskite precursor solution to partially replace formamidine iodide, and a multi-element A-site alloy structure is introduced into the perovskite solar cell, so that defects in a perovskite layer are reduced, the service life of a carrier is prolonged, surface non-radiation is inhibited, the voltage loss of a device is reduced, and the performance of the device is improved. Therefore, the performance of the perovskite solar cell is obviously improved.

The invention relates to the technical field of solar cells, and provides a silicon wafer gettering method, a silicon wafer, a cell, a preparation method, an assembly and a photovoltaic system, and the method comprises the steps: determining an impurity-containing silicon wafer from a plurality of silicon wafers produced by a crystal pulling furnace; the impurity-containing silicon wafers are silicon wafers of which the minority carrier lifetime is smaller than the mean value of the minority carrier lifetime of the silicon wafers; and gettering the impurity-containing silicon wafer to absorb impurities in the silicon wafer. Therefore, impurities in the silicon wafer can be reduced, the minority carrier lifetime of the silicon wafer is prolonged, and the photoelectric conversion efficiency of the cell is improved.

This invention relates to the field of optical inspection technology, specifically to a micro LED wafer-level rapid defect localization system based on photoluminescence. A broadband pulse excitation module outputs pulsed laser light matching the characteristics of the material under test; a two-dimensional scanning platform carries the wafer and achieves nanometer-level precise positioning; a time-resolved acquisition module collects fluorescence signals and converts them into time-resolved photoluminescence data; a data processing and control module synchronously controls the operation of each module, receives and processes the time-resolved photoluminescence data, extracts the transient luminescence intensity and carrier lifetime of each detection point, compares the two-dimensional feature vector formed by these two parameters with a preset defect feature database, identifies the defect type of each micro LED chip, and generates a wafer-level defect fingerprint spectrum. This system can accurately distinguish different types of failure modes such as epitaxial defects, surface state defects, and poor electrode contact, significantly improving detection efficiency and defect classification accuracy.

The invention discloses a method for monitoring metal pollution in an ion implantation process by using PFG and a PFG metal pollution monitoring system of an ion implanter. The method comprises the following steps: providing a P-type semiconductor wafer, and carrying out ion implantation and annealing treatment on the P-type semiconductor wafer; adopting a plasma gun as an electron source to neutralize positive charges on the surface of the P-type semiconductor wafer in ion implantation treatment; and measuring the diffusion length of a carrier of the P-type semiconductor wafer, calculating the service life of the carrier according to the diffusion length, and outputting a PFG metal pollution degree result. The SPV method is adopted, and the service life of the carriers is calculated by measuring the diffusion length of the carriers in the silicon crystal, so that the PFG metal pollution degree is monitored, the PFG metal pollution condition of the ion implanter can be monitored efficiently and accurately, process parameters are adjusted in time, and the manufacturing quality of semiconductor devices is ensured.

This application relates to the technical field of solar cells, and provides a method, device, and storage medium for determining the minority carrier lifetime of a solar cell. The method includes: determining the open-circuit voltage decay data of the solar cell according to the grayscale value image of the solar cell; the open-circuit voltage decay data refers to the difference between the first open-circuit voltage and the second open-circuit voltage; the first open-circuit voltage is the open-circuit voltage when the solar cell is irradiated with a light source; the second open-circuit voltage is the open-circuit voltage after the photogenerated carriers excited by the light source neutralize the charges on the surface of the solar cell; determining the minority carrier lifetime of the solar cell according to the open-circuit voltage decay data. Thus, it is possible to test the minority carrier lifetime on the surface of the solar cell when there are charges on the surface of the solar cell.

The application relates to the field of photovoltaic technology and discloses a passivated contact solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a substrate layer with opposite first and second surfaces; forming an oxide layer on the first surface of the substrate layer; performing laser sintering treatment on the surface of the oxide layer; forming a first doped layer on the oxide layer after the laser sintering treatment; forming a second doped layer on the second surface of the substrate layer; forming a first electrode connected with the first doped layer on the first surface side of the substrate layer; and forming a second electrode connected with the second doped layer on the second surface side of the substrate layer. In the application, the laser sintering treatment on the oxide layer realizes accurate optimization of the surface of the oxide layer, improves the surface and interface characteristics, further reduces the surface recombination rate of the oxide layer and the substrate layer and the first doped layer, improves the carrier lifetime, and thus the photoelectric conversion efficiency and stability of the cell are improved, and the power generation efficiency is improved.

The invention relates to the technical field of photovoltaic cells, in particular to a back contact crystalline silicon cell and a preparation method thereof. A back contact crystalline silicon cell comprises a silicon substrate layer, a composite layer, a tunneling oxide layer, a second passivation layer, a composite doped silicon layer and a back electrode layer. A composite layer is arranged on the first surface of the silicon substrate layer; a tunneling oxide layer is arranged on the second surface; a second passivation layer is arranged on the surface of the tunneling oxide layer; a composite doped silicon layer is arranged on the surface of the second passivation layer, and the composite doped silicon layer comprises a first antimony doped layer, a phosphorus-antimony doped layer and a second antimony doped layer which are sequentially stacked in the direction from the silicon substrate layer to the second passivation layer; and a back electrode layer is arranged on the surface of the composite doped silicon layer. According to the back contact crystalline silicon cell, the contact resistivity of the back electrode can be reduced, the service life of a carrier is prolonged, accurate adaptation of the doping structure and the BC interdigital electrode is achieved, back side parasitism is reduced, the preparation process can be simplified, the cost is reduced, and the long-term reliability of the cell and the conversion efficiency of the cell are improved.

According to the gallium nitride-based semiconductor laser with the gradually-changed polarized optical phonon energy waveguide layer, a fitting curve of In ion strength distribution or In atom concentration distribution of an upper waveguide layer and a lower waveguide layer is tested through SIMS, and a fitting curve of polarized optical phonon energy distribution meets any function distribution of Log3P1, Lop2P2 and Biphase. The spatial continuous regulation and control of the phonon energy of the optical field are realized, so that the LO phonon energy is continuously and gradually changed along the propagation direction, the phonon energy gradient is formed, the LO phonon scattering is improved, the inelastic scattering and energy relaxation of carriers and LO phonons are inhibited, the carrier transportation and phonon scattering are optimized, the service life of the carriers and the gain retention time are prolonged, and the optical field performance is improved. According to the invention, the threshold current density is reduced, the thermal stability of the laser is improved, the use power and the use temperature of the laser are improved, meanwhile, the phonon energy valley value is matched with the quantum well gain peak, the scattering loss is inhibited, additional scattering caused by phonon energy mutation is avoided, the light field limitation is enhanced, and the slope efficiency is improved.

The application discloses an anti-interface rough scattering quantum cascade laser active region and a preparation method thereof. The application forms a topological interface state protected by chiral symmetry as a lasing upper energy level at the butt joint interface between a first superlattice region and a second superlattice region, the wave function of the topological interface state is strictly zero in the thick barrier center and the interface, thereby the non-radiation loss caused by the interface roughness scattering is inhibited from the root, and the upper energy level carrier lifetime is significantly prolonged. Based on this, the threshold current density of the quantum cascade laser is greatly reduced, and high-efficiency lasing of 10 μm wavelength can be realized at room temperature. Meanwhile, a mixed epitaxy process combining molecular beam epitaxy and metal organic chemical vapor deposition is adopted, the nanometer precision energy band design of the core active region is ensured, and the efficient growth of the thick film waveguide layer is realized, which is beneficial to the practicalization and large-scale preparation of the device.

The invention belongs to the field of battery preparation, and relates to a TCO layer coating method for reducing amorphous silicon damage of an HJT battery and the HJT battery. According to the method, the technology of low-power-density H2-free of the bottom layer and high-power-density H2 of the top layer is adopted, the film thickness is comprehensively adjusted, the film forming efficiency cannot be reduced, and meanwhile through reasonable technological condition adjustment, the obtained whole film layer is excellent in photoelectric characteristic. According to the method, the minority carrier lifetime of the battery piece after top layer film deposition is verified to be not attenuated, the minority carrier lifetime is not attenuated to represent that the non-microcrystalline silicon layer and the microcrystalline silicon layer are not damaged, the film forming speed and the battery characteristics are not reduced, and the damage of the non-microcrystalline silicon can be reduced.

This invention discloses a perovskite active layer passivating agent, a perovskite solar cell, and a preparation method thereof, relating to the field of perovskite solar cell technology. The invention uses a combination of formamidine thiocyanate (FASCN) and dodecyl ammonium bromide (DABr) as passivating agents. Through the "phase screening" effect of FA⁺ and the coordination regulation of SCN⁻, n=3 single-phase quasi-two-dimensional perovskite is selectively generated on the wide-bandgap perovskite surface, completely suppressing the n=2 phase and eliminating multiphase energy level disorder. Simultaneously, it achieves triple synergistic passivation: SCN⁻ coordinates and passivates lead defects, Br⁻ fills halogen vacancies, and FA⁺ occupies A-site vacancies, resulting in a 27% reduction in trap density and a 12-fold increase in carrier lifetime. The resulting perovskite solar cell exhibits a 6.8% increase in efficiency, significantly enhanced thermal stability, and a 4-fold increase in T80 lifetime. Furthermore, it is fully compatible with existing preparation processes and suitable for large-scale production.

This disclosure provides a solar cell, a semi-finished cell, and a fabrication method thereof, belonging to the field of solar cell technology. The semi-finished cell includes a cell body and a porous silicon layer serving as a texturing precursor. The porous silicon layer is disposed at least on the front surface of the cell body, with a porosity of 30%–70% and an average pore depth of 50 nm–500 nm. By preparing a porous silicon layer at least on the front surface of the cell body, this disclosure provides numerous and uniform nucleation sites for subsequent alkaline texturing. In an alkaline solution, the corrosion reaction preferentially begins from the pore edges, guiding the uniform and dense growth of the pyramid texture. Furthermore, the porous silicon layer serves as an effective anti-reflection structure, forming a dual anti-reflection effect with the subsequently formed pyramid textured surface, reducing reflection. In addition, the uniform textured surface further formed from the porous silicon layer has lower surface recombination, which is beneficial for improving minority carrier lifetime and increasing cell efficiency.

The invention provides an N-type phosphorus-doped monocrystalline silicon crystal bar minority carrier lifetime and resistivity axial distribution prediction method, and relates to the technical field of monocrystalline silicon crystal bar detection. The method comprises the following steps: S1, obtaining basic parameters of a crystal bar; s2, carrying out segmented K parameter prediction; s2 comprises the steps of S21, determining a predicted position coordinate; s22, calculating segment endpoint parameters; the step S1 comprises calculating the total length of the crystal bar and measuring the minority carrier lifetime and resistivity of the head of the first section of the crystal bar and the minority carrier lifetime and resistivity of the tail of the tail section of the crystal bar by using an instrument. By detecting the electrical properties of the head and the tail of the head section of the crystal bar, the electrical properties of other sections are accurately predicted, and cost reduction and efficiency improvement are realized.

The invention discloses a gradient annealing-based TOPCon solar cell and a preparation method thereof, and relates to the technical field of cell production, and the method comprises the steps: carrying out a three-stage gradient annealing process on a silicon-based substrate on which a tunneling oxide layer is formed, and comprises the steps: heating the silicon-based substrate to 400-450 DEG C in a mixed atmosphere of H2 and N2, and filling dangling bonds in the tunneling oxide layer; heating the silicon-based substrate to 600-650 DEG C by adopting a pulse heating mode, and switching the atmosphere into a mixed atmosphere of O2 and N2 to form a SiOxNy transition region; and cooling the silicon-based substrate to 300-350 DEG C, putting the silicon-based substrate into plasma equipment, treating the silicon-based substrate in a mixed atmosphere of H2 and Ar for 3 minutes, and exciting hydrogen free radicals to permeate into the interface to repair the interface defects. According to the method, low-temperature hydrogen annealing is set, H atoms are promoted to diffuse to a SiO2 / Si interface in a low-temperature area, dangling bonds are repaired, Si-O bond rearrangement is induced in a medium-temperature area, a compact tunneling layer is formed, then hydrogen free radicals are excited to permeate to the interface and interface defects are repaired through the plasma treatment step, the minority carrier lifetime is prolonged, and the photoelectric conversion rate is improved.

This invention discloses a method for preparing high sheet resistance shallow pn junction single-crystal silicon wafers based on rapid boron diffusion, comprising the following steps: S1: depositing a boron-containing precursor on the textured silicon wafer surface; S2: depositing a low-temperature oxide layer on the surface of the boron-containing precursor; S3: placing the silicon wafer with the deposited low-temperature oxide layer in a rapid thermal processing device, rapidly heating it to 1050-1350℃ at a heating rate of 5-200℃ / s, holding it at this temperature for 20-600s, and then rapidly cooling it to complete the diffusion and activation of boron atoms in the silicon wafer. This invention employs a combination of low-temperature deposition and rapid boron diffusion, which can significantly shorten the boron diffusion time, reduce energy consumption, and shorten the high-temperature processing time. It also suppresses the formation of oxygen precipitate defects at the source, eliminating problems such as black cores and black rings in batteries, and significantly improving carrier lifetime and material electrical performance.

It is possible to estimate the carrier lifetime, and the Z-axis in the depth direction of the SiC epitaxial layer. 1 / 2 The present invention provides a SiC epitaxial wafer and a SiC device having a SiC epitaxial layer in which variations in center density are suppressed. [Solution] The SiC epitaxial wafer consists of a SiC substrate 1 and a first surface 1A of the substrate, Z 1 / 2 A SiC epitaxial layer 2 having a center 3 inside, and the Z of the SiC epitaxial layer 1 / 2 The uniformity of the center density in the depth direction is less than 0.5% / μm.

This invention discloses a light-emitting chip and its fabrication method, as well as an optical communication system. The light-emitting chip includes at least two light-emitting units. When the at least two light-emitting units are arranged horizontally, the light-emitting chip also includes a connecting electrode disposed on one side of the backlight surface of the light-emitting unit, which is used to connect two adjacent light-emitting units in series. And / or, when the at least two light-emitting units are arranged vertically, the light-emitting chip also includes a tunneling junction disposed between two adjacent light-emitting units, used to connect the two adjacent light-emitting units in series. This allows the light-emitting chip to form a series high-voltage chip, enabling high-voltage driving. Furthermore, the light-emitting chip exhibits a low RC constant, long carrier lifetime, and high parasitic effect. When used in optical communication, the light-emitting chip can improve the communication speed, facilitating high-speed communication.

The application relates to the technical field of communication devices, in particular to a method for improving quantum dot optical communication bandwidth, a quantum dot light-emitting structure and an experimental method for improving quantum dot optical communication bandwidth, which comprises the following steps: S1, providing a light-emitting chip; and S2, setting quantum dot color conversion materials with preset parameters on the light-emitting path of the light-emitting chip, so that the light emitted by the light-emitting chip passes through the quantum dot color conversion materials. Based on the principle of fluorescence resonance energy transfer, the application selects appropriate quantum dot concentration, adds a polar solvent to the quantum dot solution to generate an energy acceptor, enhances the energy transfer between the energy acceptor and the perovskite quantum dot, accelerates the recombination rate of carriers, reduces the carrier lifetime, and improves the communication bandwidth and rate.