278 results about "Carrier lifetime" patented technology

The variable excitation intensity time-resolved photoluminescence carrier lifetime test method comprises the following steps: S1, pulse excitation time-resolved photoluminescence response is carried out to obtain a time-dependent attenuation curve of the unbalanced carrier concentration of a to-be-tested sample, and S2, according to the attenuation curve, the time-dependent attenuation curve of the unbalanced carrier concentration of the to-be-tested sample is calculated. The carrier lifetime data under different excitation intensities are fitted to obtain the SRH lifetime and the surface composite lifetime of the sample, and the # imgabs0 # SRH composite lifetime, the # imgabs1 # radiation composite lifetime and the # imgabs2 # auger composite lifetime are obtained. The variable excitation intensity time-resolved photoluminescence carrier lifetime test method can accurately measure each component of the carrier lifetime.

The invention belongs to the technical field of back contact cells, and particularly relates to a joint passivation back contact cell and a post-texturing preparation method thereof, and the method comprises the steps: S102, sequentially forming a first semiconductor layer and a mask layer on the back surface of a silicon substrate; s103, cleaning and texturing are carried out, so that a texturing surface is formed on the light receiving surface of the silicon substrate, and the maximum height of a pyramid of the texturing surface of the light receiving surface is T1; s104, sequentially forming a passivation layer and an anti-reflection layer on the light receiving surface of the silicon substrate; s105, forming a second semiconductor opening region; s106, cleaning and etching are carried out, and a groove structure is at least formed in the second semiconductor opening region on the back surface of the silicon substrate; and S107, depositing a second semiconductor layer on the back surface, wherein the second semiconductor layer comprises an amorphous passivation layer and a second doped silicon layer. Under the conditions of simplifying the process steps and reducing the material cost, the interface contact resistance of the second semiconductor opening region can be reduced, the minority carrier lifetime is prolonged, and the cell efficiency and the double-sided rate are improved.

The present invention provides a single crystal furnace and a single crystal silicon rod annealing method, the single crystal furnace comprises: a main chamber comprising a furnace body and a throat structure located above the furnace body which are connected with each other, and the furnace body is used for forming a single crystal silicon rod; the auxiliary chamber is mounted above the throat structure; the flow guide cover is arranged in the main chamber and located at the throat structure, the flow guide cover comprises a cover body, and the cover body is provided with a middle flow channel allowing the silicon single crystal rod to penetrate through and an annular flow channel surrounding the middle flow channel; the throat structure is provided with an inlet which is communicated with an inlet of the annular flow channel so as to introduce a first fluid into the annular flow channel; an inlet of the middle flow channel is communicated with the auxiliary chamber so as to receive a second fluid introduced from the auxiliary chamber; and an outlet of the annular flow channel is communicated with an outlet of the middle flow channel, so that the first fluid and the second fluid are converged to cool the monocrystalline silicon rod, and the problem that the minority carrier lifetime of monocrystalline silicon is easily shortened by a monocrystalline silicon annealing process in the prior art is solved.

The invention discloses an online defect detection method for a main-grid-free photovoltaic cell panel, which comprises the following steps of: obtaining a life distribution diagram of a main-grid-free photovoltaic cell through time-resolved photoluminescence, and obtaining a heat dissipation diagram of the main-grid-free photovoltaic cell through optically-induced phase-locked thermal imaging; an ultrasonic diagram of the main-grid-free photovoltaic cell is obtained through laser ultrasound; preprocessing and registering the life distribution diagram, the heat dissipation diagram and the ultrasonic diagram so as to uniformly map the life distribution diagram, the heat dissipation diagram and the ultrasonic diagram to a cell coordinate system, extracting minority carrier life, heat dissipation power, ultrasonic propagation time delay offset and scattering energy, and forming a multi-modal feature together with a thermal phase; and based on the abnormal score, performing defect detection and classification on the multi-modal features of the possible defect area to obtain classification results of electrical defects, thermal defects and mechanical defects. The invention also discloses a system for realizing the method. According to the invention, full-coverage detection of electrical, thermal and mechanical defects is realized.

The invention discloses a preparation method of an intrinsic passivation structure, the intrinsic passivation structure and a battery, the intrinsic passivation structure comprises a base layer, the surface of which is provided with a first interface layer; the first intrinsic layer is arranged on the first interface layer, and a second interface layer is arranged on the surface of the first intrinsic layer; the second intrinsic layer is arranged on the second interface layer, and a third interface layer is arranged on the surface of the second intrinsic layer; and the doped microcrystalline silicon layer is arranged on the surface of the third interface layer. According to the invention, the surfaces of the base layer, the first intrinsic layer and the second intrinsic layer are treated, so that the contact between the intrinsic amorphous silicon and the crystalline silicon substrate is effectively improved, the generation of nano twin crystals is inhibited, the passivation effect is enhanced, and the minority carrier lifetime is prolonged.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region, a second region and a third region which are sequentially distributed; the first region is adjacent to the first surface and the third region is adjacent to the second surface. The second region is recessed towards the silicon substrate by a distance of 2-10 [mu] m relative to the first region; the first area is provided with a first pyramid structure, the second area is provided with a second pyramid structure, and the third area is provided with a third pyramid structure and / or a first texture structure; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface.

The invention discloses a secondary texturing method, a monocrystalline silicon wafer and a solar cell, the textured monocrystalline silicon wafer is immersed in a secondary texturing solution, and texturing is carried out for 100-200 s at 55-70 DEG C, so that the textured structure of the monocrystalline silicon wafer comprises a pyramid with the bottom edge length of 2-7 [mu] m, the top of the pyramid is round and full, the pyramid is overlooked, and the textured structure of the monocrystalline silicon wafer is obtained. And the side surface of the tower is provided with a step-shaped microstructure which is transited to the tower top layer by layer. The textured structure prepared by the method disclosed by the invention is beneficial to uniform growth of the amorphous silicon film, the passivation quality of amorphous silicon is improved, the service life of a carrier is prolonged, the light trapping effect is improved, and the reflectivity of a silicon wafer is reduced. Meanwhile, the prepared suede structure has a larger specific surface area, so that the contact area of the low-temperature conductive silver paste and the silicon wafer is larger, and the silver paste and the silicon wafer have better ohmic contact; the step-shaped microstructure of the tower surface enables the adhesive force of the silver paste to be increased on the surface of the pyramid, the width of the grid line can be reduced, the shading area and the silver paste consumption are reduced, and the purposes of reducing cost and improving efficiency of the HJT battery are achieved.

The invention discloses a high-voltage fast recovery diode with a positive temperature characteristic and a manufacturing method of the high-voltage fast recovery diode. A central region of the device is a P-type doped active region which is used as an anode when the device works in the forward direction; p-type doped field limiting rings are arranged on the two sides of the active region and serve as voltage dividing rings of the device, and the field limiting rings and the active region are doped independently; an N-type doped cut-off ring is arranged on the outermost periphery of the device and provides an electric field cut-off effect; a metal field plate is arranged above each field limiting ring to improve the distribution of a peripheral electric field and improve the stability of the device; except for the position of the contact hole, CVD, silicon nitride and polyimide in the vertical direction of the device are used as passivation layers of the device to isolate the influence of external moisture, charges and the like, so that the reliability of the device is improved; metal is directly deposited above the active region to serve as an anode of the device; and a layer of metal is evaporated on the back of the device after being thinned to serve as a device cathode. A platinum diffusion and electron irradiation process is used as a minority carrier lifetime control technology to adjust the temperature characteristic of the device.

The invention relates to the field of batteries, particularly provides a solar battery and a preparation method of the solar battery, and aims to solve the problem of serious minority carrier lifetime attenuation of the solar battery with a transparent conductive passivation layer under low injection concentration. To this end, the solar cell of the present invention comprises a first layer having a first conductivity type, a second layer having a second conductivity type, and a transparent conductive passivation layer; the second layer is arranged on the first surface of the first layer and has a second conduction type opposite to the first conduction type, so that a PN junction is formed between the first layer and the second layer; the transparent conductive passivation layer is arranged on a second surface, opposite to the first surface, of the first layer, and the transparent conductive passivation layer has a doping concentration capable of promoting majority carriers in the first layer to flow to the second surface. When the doping concentration is appropriate, the motion direction of the majority carriers can be influenced, so that the bending direction and degree of the energy band can promote the majority carriers to flow to the second surface of the first layer, and the service life of the minority carriers is prolonged.

The invention relates to the technical field of organic compound solar cells, and provides a large-size perovskite assembly pre-illumination synergistic aging test system and method, and the system comprises a light attenuation subsystem, a current-voltage test subsystem, and a control and region light supplement array subsystem. The method comprises the following steps: the light attenuation subsystem obtains the physical and chemical state change of the perovskite component through processing dual-band cooperative irradiation; the current-voltage test subsystem calculates the variance of the carrier lifetime to obtain a performance uniformity evaluation result of the perovskite assembly; a performance uniformity evaluation result forms a PID algorithm output signal through the control subsystem; the control subsystem processes a PID algorithm output signal to obtain an LED intensity adjusting signal for each light supplementing area; lED intensity adjusting signals pass through the area light supplementing array subsystem to form a uniform illumination environment, and a compensated perovskite component surface light field is obtained. According to the invention, a multi-parameter coupled accelerated aging platform is provided for the reliability research of the perovskite component.

The invention provides a silicon single crystal rod and a preparation method thereof, a silicon wafer and a solar cell, the silicon single crystal rod contains hydrogen element, the silicon single crystal rod has a center and an edge along the radial direction of the silicon single crystal rod, and (CH1-CH2) / CH2 is more than or equal to 0 and less than or equal to 35%; and the dislocation density of the silicon single crystal rod meets the condition that (rho1-rho2) / rho1 is greater than or equal to-80% and less than or equal to 80%. According to the silicon single crystal rod provided by the invention, the hydrogen element is doped, and the distribution uniformity of the hydrogen element in the radial direction of the silicon single crystal rod is controlled, so that the recombination effect of defects such as dislocation and vacancy on carriers is effectively reduced in the radial range of the whole silicon single crystal rod, the minority carrier lifetime is prolonged, meanwhile, the stress distribution in the silicon single crystal rod is improved, and the service life of the silicon single crystal rod is prolonged. And the stress is more uniformly released on the cross section of the whole silicon single crystal rod, so that the mechanical property of the silicon rod is enhanced.

The embodiment of the invention relates to a solar cell, a preparation method thereof and a photovoltaic module. The preparation method of the solar cell comprises the steps of providing a substrate; the substrate is provided with a first surface and a second surface which are arranged oppositely; forming a passivation layer on at least one side of the first surface and the second surface of the substrate; under a normal temperature condition, carrying out first light treatment by adopting a light beam with a first wavelength; the minority carrier lifetime in the substrate after the first light treatment is greater than or equal to 2000 [mu] s.

The invention relates to a silicon wafer defect detection method. The method comprises the following steps: providing a silicon wafer sample with oxygen concentration lower than 9ppma; carrying out first heat treatment on the silicon wafer sample under a first preset condition so as to generate oxygen evolution nucleation in a P-band region, a B-band region and / or an IDP region; performing secondary heat treatment on the silicon wafer sample under a second preset condition to generate oxygen evolution nucleation in a VDP region; performing third-time heat treatment on the silicon wafer sample under a third preset condition, so that oxygen evolution nuclei generated in the first-time heat treatment and the second-time heat treatment grow; and carrying out minority carrier lifetime test on the silicon wafer sample. Through a three-section heat treatment method, the oxygen precipitation amount of a part of crystal characteristic areas is increased, so that crystal characteristic area boundary distinguishing can be clearly carried out on a silicon wafer with the oxygen concentration below 9ppma.

The invention discloses a solar cell and a photovoltaic module, which are used for realizing light trapping, electric leakage prevention, minority carrier lifetime prolonging and cell efficiency improving. Comprising a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a passivation layer, the silicon substrate has a first surface, a second surface and a side surface. The first surface has a pyramid structure, and the side surface comprises a first region and a second region which are sequentially distributed; the first region is adjacent to the first surface and the second region is adjacent to the first region. The second region is recessed into the silicon substrate by a first distance relative to the first region; the first doped semiconductor layer and the second doped semiconductor layer with opposite conduction types are respectively arranged on the first surface and the second surface; the passivation layer is arranged on the first surface, the second surface and the side surface; the second surface comprises groove regions and doped regions which are alternately arranged, and the groove regions are recessed towards the silicon substrate by a second distance relative to the doped regions; the second doped semiconductor layer is located in the doped region, and the passivation layer is located in the trench region and the doped region; wherein the first distance is greater than or equal to the second distance.

The invention provides a cadmium telluride thin-film solar cell and a high-temperature doping method thereof, and the method comprises the steps: coating a wet film containing a doping substance on the surface of one side of a cadmium telluride absorption layer, and obtaining an ex-situ doped cadmium telluride absorption layer after high-temperature annealing. Wherein the doping substance comprises a V-group element fluoride, and the temperature of high-temperature annealing is greater than or equal to 200 DEG C. According to the cadmium telluride thin-film solar cell, the V-group element fluoride is adopted to carry out high-temperature doping at the temperature of 200 DEG C or above on the cadmium telluride absorption layer, the effective doping concentration is improved, meanwhile, the service life of a photon-generated carrier is considered, finally, the open-circuit voltage and the photoelectric conversion efficiency of the cadmium telluride thin-film solar cell are improved, and large-scale application and popularization are facilitated.

The invention belongs to the technical field of solar cells, and particularly discloses a texturing additive, a texturing solution and a texturing method of a back contact cell. The texturing additive for the back contact battery comprises the following components in percentage by mass: 1.0%-5.0% of sodium carboxymethyl cellulose, 0.03%-0.2% of sodium lignin sulfonate, 0.003%-0.03% of paeoniflorin, 0.005%-0.05% of salvianolic acid B, 0.001%-0.01% of polyhexamethylene biguanide hydrochloride, 0.3%-1.0% of a buffering agent, 0.01%-0.1% of a surfactant and the balance of water. The components interact with each other, and the texturing additive is added into the texturing liquid to improve the flatness of the texturing surface and effectively solve the problem that the texturing surface is not fully distributed, so that the minority carrier lifetime and the open voltage of the back contact battery are improved, and the photoelectric conversion efficiency of the battery is improved.

The invention discloses a wide-band-gap perovskite thin film based on interface engineering regulation and control and a preparation method and application thereof. The preparation method comprises the following steps: dissolving 4-hydroxyphenylethyl amine iodide powder in an FA0. 8Cs0. 2Pb (I0. 6Br0. 4) 3 precursor solution to obtain a wide-band-gap perovskite precursor solution with the doping concentration of 0.5-2mol%; the wide-band-gap perovskite thin film is obtained by performing two-step spin coating on the wide-band-gap perovskite precursor solution on a substrate and then performing two-step annealing, and when the wide-band-gap perovskite thin film is applied to a wide-band-gap perovskite solar cell or a laminated wide-band-gap perovskite solar cell, the stability and the performance of a device can be improved. The method is mainly characterized by improving the uniformity of the film, reducing non-radiative recombination, prolonging the service life of current carriers, improving filling factors and current density and improving the photoelectric conversion efficiency. According to the invention, generation of a two-dimensional phase is inhibited, a dipole layer is generated on an interface, energy level matching between a perovskite light absorption layer and an electron transport layer is promoted, interface connection is enhanced, and carrier transport capability is improved.

The invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery post-texturing method with a specific laser opening mode and a battery, and the process of forming a second semiconductor opening area comprises the following steps: rotating a target silicon wafer from a feeding position to a CCD camera position, and obtaining the position information of the target silicon wafer through a CCD camera, the position information is fed back to a laser marking mechanism and a mask mechanism which are arranged at a processing position, and the laser marking mechanism and the mask mechanism carry out alignment position adjustment according to the fed-back position information; and laser emitted by the laser marking mechanism passes through the mask plate and then is marked on a target silicon wafer to be processed. According to the invention, the edge of the opening area of the second semiconductor can be flat, the proportion of a laser opening edge transition area in the opening area of the second semiconductor is reduced to the greatest extent, the gradient of the junction of the opening area and the non-opening area is effectively improved, and Josc is obviously improved in a minority carrier lifetime test of a battery body, so that the battery efficiency is improved.

The invention relates to the technical field of solar cells, in particular to a preparation method of a single-wave precisely doped N-type BC cell. The invention discloses a preparation method of a single-wave precisely doped N-type BC battery. The preparation method comprises the following steps: S1, pre-treating an N-type silicon wafer; s2, performing boron doping on the front surface of the silicon wafer by adopting infrared single-wavelength laser to form a P + shallow junction; performing phosphorus doping on the back surface of the silicon wafer by adopting ultraviolet single-wavelength laser to form an N + region; s3, carrying out single-frequency microwave annealing treatment; s4, preparing a tunneling oxide layer, a boron-doped polycrystalline silicon passivation layer and a surface laminated passivation film; s5, carrying out laser grooving and copper electrode electroplating; s6, cutting the edge of the silicon wafer by adopting single-wavelength femtosecond laser; and S7, low-temperature annealing treatment. According to the method, the doping accuracy is improved, the service life of N-type silicon wafer carriers is ensured, the carrier recombination loss is remarkably reduced, the contact resistance and edge recombination loss is reduced, and the filling factor and the conversion efficiency of the cell are improved.

The invention discloses a perovskite solar cell and a preparation method thereof. The perovskite solar cell comprises a conductive glass substrate layer, an electron transport layer, a functional layer, a passivation layer, a hole transport layer and a metal electrode layer which are sequentially arranged from bottom to top, the functional layer is mainly composed of a perovskite light absorption layer I, or a monomer molecule passivation layer and a perovskite light absorption layer II which are sequentially arranged from bottom to top; the perovskite light absorption layer I is formed by coating the electron transport layer with a precursor solution I containing monomer molecules, and the monomer molecule passivation layer and the perovskite light absorption layer II are formed by sequentially coating the electron transport layer with a monomer molecule solution and a precursor solution II without monomer molecules. According to the perovskite solar cell, charge transfer and carrier lifetime are influenced by monomer molecules, so that the open voltage and the filling factor are greatly improved, and finally the photoelectric conversion efficiency of the perovskite solar cell is improved.

The application discloses a photovoltaic silicon monocrystal wafer group, a crystal column group, a photovoltaic cell and a photovoltaic module. The wafer group comprises rectangular silicon wafers cut from the middle of a base circle silicon wafer and axisymmetric non-rectangular polygonal silicon wafers symmetrically cut from the periphery of the rectangular silicon wafers. The cutting size of the rectangular silicon wafers is determined according to the distribution of vacancy-type point defect density C V and interstitial-type point defect density C I of the base circle silicon wafer and the distribution of minority carrier lifetime in different radial regions of the base circle silicon wafer, so that the rectangular silicon wafers are located in the region of C V ‑ C I ≥0, and the ratio d of the distance between the four corners of the rectangular silicon wafer and the minimum point of the minority carrier lifetime in the edge region of the base circle silicon wafer to the diameter of the base circle silicon wafer is 2%≤d≤8%. The method is based on the quality distribution rule of the silicon wafer to divide the silicon wafers into two types, and different cell processes are adopted to fully tap the potential of each type, so that the area utilization rate of the base circle silicon wafer is more than 90% while high-quality photovoltaic modules are obtained.

This application provides a passivation structure and its preparation method, as well as a silicon solar cell and its preparation method. The passivation structure includes a first aluminum oxide layer, a first aluminum nitride layer, a second aluminum oxide layer, and a second aluminum nitride layer stacked together. The first aluminum oxide layer directly contacts the silicon edge and repairs cutting damage and dangling bonds through chemical passivation. It adapts to the p-type silicon region with a negative fixed charge. The first aluminum nitride layer passivates the n-type silicon with a positive fixed charge. The high hydrogen content enhances defect repair, and the dense structure blocks impurities from intruding. The second aluminum oxide layer supplements the negative charge to improve the passivation effect of the p-type silicon and forms stress complementarity with the aluminum nitride layer to prevent film cracking. The second aluminum nitride layer resists stringing and lamination damage, blocks moisture and corrosion, and ensures long-term performance. This structure achieves optimal simultaneous passivation of p / n-type silicon through charge complementarity and synergistic hydrogen passivation, improving the minority carrier lifetime at the cell edge, the implicit open-circuit voltage, and the module power, and solving the pain points of incomplete passivation and poor stability.

The invention relates to the technical field of photovoltaic cells and materials thereof, and discloses a crystalline silicon wafer for preparing a crystalline silicon photovoltaic cell, a silicon ingot and a laminated photovoltaic cell. The crystal silicon wafer has one of the following characteristics: 1) the crystal silicon wafer is a lithium crystal silicon wafer of lithium-doped silicon; and 2) the crystal silicon wafer is an alloy crystal silicon wafer, the alloy crystal silicon wafer comprises a substrate, an alloy area containing silicon, tin and germanium alloy elements is locally prepared on the substrate, the alloy crystal silicon wafer is formed, and the alloy area of the alloy crystal silicon wafer comprises the following alloy elements in percentage by atomic number: 5-53% of silicon, 2-12% of tin and the balance of germanium. Compared with the prior art, the current output potential is improved, the photoelectric conversion efficiency is improved, lithium in the lithium crystal silicon wafer effectively passivates defects in crystalline silicon, the minority carrier lifetime of the crystalline silicon is prolonged, the mobility of the crystalline silicon is improved, a better lithium interface passivation effect is achieved, and the function of resisting the ultraviolet induced degradation effect is achieved.

The present invention provides a method for manufacturing a semiconductor structure. The method for manufacturing the semiconductor structure includes: providing a semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a diffusion film on a surface of the first epitaxial layer facing away from the semiconductor substrate, the diffusion film having diffusion atoms; after forming the diffusion film, performing an annealing treatment to allow the diffusion atoms to enter the first epitaxial layer, the diffusion atoms being suitable for filling atomic vacancies in the first epitaxial layer. The present invention introduces the diffusion atoms in the diffusion film into the first epitaxial layer to fill the vacancies inside the first epitaxial layer, reduces the deep-level defects in the first epitaxial layer, achieves the purpose of improving the carrier lifetime, avoids damage to the surface of the first epitaxial layer, is convenient to implement, and reduces the production cost.

The invention discloses a silicon carbide epitaxial wafer for inhibiting irradiation induced defects, a preparation method and application, and belongs to the technical field of semiconductor materials, the silicon carbide epitaxial wafer comprises an n-type or p-type silicon carbide wafer as a substrate, and an epitaxial layer doped with group IV atoms is epitaxially grown on the substrate. The preparation method comprises the following steps: cleaning an n-type or p-type silicon carbide wafer; placing the cleaned silicon carbide wafer in epitaxial growth equipment and keeping a vacuum environment; raising the temperature of the vacuum environment, and introducing monosilane, propane, nitrogen / hydrogen carrying trimethyl aluminum and gas containing at least one atom of germanium, tin and lead after the temperature is stable; and growing an epitaxial layer on the silicon carbide wafer. The silicon carbide epitaxial wafer is used for producing an anti-radiation silicon carbide power device. According to the invention, generation of carbon vacancies in a silicon carbide device in an irradiation process and minority carrier lifetime degradation caused by the generation of the carbon vacancies can be effectively inhibited, so that the reliability of the silicon carbide epitaxial wafer and a power device thereof under particle irradiation application is improved.

Device for controlling at least one light-emitting diode (LED1) to generate short light pulses (LP),- with an H-bridge (H) consisting of a first half-bridge (HB1: T1, T2) with a first transistor (T1) and a second transistor (T2) and a second half-bridge (HB2: T2, T3) with a third transistor (T3) and a fourth transistor (T4),- wherein the H-bridge (H) is controlled by a control unit (ST) and- wherein the H-bridge (H) can be operated by the control unit (ST) in pulsed mode (GPB) and in quasi-continuous mode (QDB) and- wherein the first half-bridge (HB1: T1, T2) is supplied with electrical energy from a first positive supply voltage (VCC1) and a first negative supply voltage (GND1) and- wherein the second half-bridge (HB2: T3,T4) is supplied with electrical energy from a second positive supply voltage (VCC2) and a second negative supply voltage (GND2) and- wherein the light-emitting diode (LED1) is connected with its cathode (K) to the output of the first half-bridge (HB1: T1, T2) and- wherein the light-emitting diode (LED1) is connected with its anode (A) to the output of the second half-bridge (HB2: T3, T4) and- wherein the first positive supply voltage (VCC1) and the second positive supply voltage (VCC2) can be equal and- wherein the first negative supply voltage (GND1) and the second negative supply voltage (GND2) can be equal and- wherein the light source, in particular the one or more light-emitting diodes (LED1), represents the load of the H-bridge (H) between the output of the first half-bridge (HB1: T1, T2) and the output of the second half-bridge (HB2: T3, T4) and- wherein the control device (ST) is designed to operate in pulsed mode (GPB) a “PAn” condition,in which a forward voltage in the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a turn-on time (τpp), and- wherein the control device (ST) is designed so that in pulsed operation (GPB) a "PAus" state, in which a reverse voltage against the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a clearing time (τpn), and- wherein the clearing time (τpn) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1), and- wherein the turn-on time (τpp) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1).

The invention provides a photoconductive switch of a comb electrode, which comprises a semi-insulating gallium arsenide substrate layer, a low-temperature gallium arsenide layer and an insulating protective layer, and is characterized in that the low-temperature gallium arsenide layer is formed on the semi-insulating gallium arsenide substrate layer, and the insulating protective layer is arranged on the low-temperature gallium arsenide layer; a switch anode and a switch cathode are respectively formed on the inner side of the low-temperature gallium arsenide layer surface insulation protection layer; a comb-shaped electrode is arranged on the surface of the low-temperature gallium arsenide layer and located at the switch anode. According to the invention, by arranging the comb-shaped electrode structure, a plurality of comb-tooth electrodes which are distributed in a staggered manner are formed in the electrode region, so that the action area of incident light and a semiconductor active region is increased under an illumination condition, and generation and collection of photon-generated carriers are facilitated; meanwhile, the distribution state of an electric field near the electrode is improved, and the possibility of local electric field concentration is reduced; in addition, a low-temperature gallium arsenide material is adopted as the photoconductive layer, the service life of a current carrier is short, and the device is suitable for photoelectric trigger application scenes with requirements for response speed and stability.

The invention discloses a chirp photoluminescence-based semiconductor carrier lifetime imaging method, which comprises the following steps of: exciting a semiconductor by using laser which is subjected to light intensity chirp modulation and has photon energy greater than the forbidden band width of the semiconductor after collimation and beam expansion; time domain characteristics of photoluminescence image signals emitted by the generated unbalanced carriers through radiative recombination are associated with chirp parameters of excitation light and the service life of semiconductor carriers, and the time domain characteristics are sampled and shot by a CCD and transmitted to a computer; convolution is carried out on a laser modulation signal and response functions corresponding to different carrier lifetime to obtain a series of reference signals, cross-correlation operation is carried out on the reference signals and discrete time domain signals of all pixel points of the CCD in different frames, and the carrier lifetime corresponding to the reference signal with the highest correlation peak value is the measured value of the pixel point. The whole image is the quantitative spatial distribution of the carrier lifetime of the sample. The method can provide a non-contact, high-signal-to-noise-ratio, quantitative, rapid and online electrical quality imaging characterization method for a semiconductor wafer production line.

A kind of tin lead perovskite photodetector based on introducing guanidinium ion and strontium ion and preparation method thereof, belong to perovskite photoelectric device technical field.The photodetector described in the application is composed of ITO conductive glass anode, PTAA anode buffer layer, tin lead perovskite film introducing guanidinium ion and strontium ion, C 60 / BCP cathode buffer layer, Cu cathode from bottom to top. + When A-site cation is doped with ion in perovskite, the carrier lifetime of perovskite material can be improved, and the open-circuit voltage of the device can be improved, the carrier diffusion length can be increased, the defects can be reduced, and the stability of the device can be improved;Sr 2+ Doping with ion in B-site of perovskite can increase conductivity, improve stability and optimize electrode performance, ultimately achieve the effect of passivating defects, reducing the capture of electrons by traps and improving photoelectric conversion efficiency, and the optimization effect mainly reflects on light and dark current and external quantum efficiency, and a high-performance photodetector is obtained.

A minority-carrier lifetime imaging system (100) and method for a semiconductor wafer. The system (100) comprises: a control module (110), which is used for generating a first electric pulse signal (Ep1) and a second electric pulse signal (Ep2); a light source module (120), which is used for generating a detection light beam (L1) and an excitation light beam (L2) on the basis of the first electric pulse signal (Ep1) and the second electric pulse signal (Ep2); a bearing module (130), which is used for fixing a wafer; a beam expansion module (140), which is used for enabling the detection light beam (L1) and the excitation light beam (L2) to be incident, by means of the beam expansion module (140), onto the wafer fixed on the bearing module (130), such that minority carriers on the wafer are converted from a ground state to an excited state under the excitation of the excitation light beam (L2), and the detection light beam (L1) detects the minority carriers in the excited state; and an imaging module (150), which is used for acquiring the minority carriers in the excited state that are detected by the detection light beam (L1), and generating a transient absorption image of the wafer, wherein the control module (110) is further used for generating a wafer minority-carrier lifetime image on the basis of the transient absorption image.