65186results about "Semiconductor/solid-state device manufacturing" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

In the present disclosure, a first semiconductor element of a bonded structure comprises a semiconductor-containing oxynitride bonding layer formed on a first substrate layer comprising a semiconductor material, e.g., a single crystal silicon. The semiconductor-containing oxynitride bonding layer is formed by exposing an upper surface of the first substrate layer to products of plasma containing nitrogen and oxygen at controlled plasma conditions. The second semiconductor element of the bonded structure may have a second substrate layer comprising a semiconductor material, e.g., a single crystal silicon, and a semiconductor-containing oxynitride bonding layer formed over the second substrate layer in the same way as the first semiconductor element. In some embodiments, the second semiconductor element may have a bonding layer comprising a dielectric material. After initial direct bonding of the first and second semiconductor elements, the bonded structure may go through an annealing process to strengthen the bonding.

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

The invention relates to the technical field of laser material processing, and discloses a laser annealing temperature control method and device.The method comprises the steps that the specific heat capacity, the heat conductivity coefficient, the heat diffusivity, the heat radiation rate, the heat reflectivity and the heat loss coefficient are obtained, and a material thermal characteristic model is established; performing grid division according to the material thermal characteristic model to obtain a laser energy density parameter; extracting a thermal strain coefficient according to the laser energy density parameter, and establishing a temperature-thermal strain mapping relation prediction model; dynamically adjusting a laser power proportion and a pulse width time sequence according to the temperature-thermal strain mapping relation prediction model to obtain temperature field distribution data; according to the temperature field distribution data, carrying out shortest path analysis to obtain a temperature regulation and control decision; and according to the temperature regulation and control decision, inputting a preset control regulation model, and combining reinforcement learning iteration optimization parameters to obtain a temperature control scheme. According to the method, large-range temperature crossing and fine adjustment in an extremely short time can be realized.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

The invention relates to the technical field of temperature measurement, in particular to a multi-zone temperature distribution real-time calibration method based on a heating body, which comprises the following steps of: 1, etching on the surface of a metal alloy heating body of which the resistance temperature coefficient is greater than a preset material threshold value to form N discrete series resistance heating units which are electrically connected in series but thermally discrete; 2, establishing a resistance-temperature dynamic relation library of each discrete series resistance heating unit; 3, synchronously measuring the real-time resistance value of each unit when the heating body works; 4, reversely deducing the temperature of a unit center point through a unit exclusive relational expression according to the real-time resistance value, and reconstructing a continuous temperature distribution matrix on the surface of the heating body in combination with a heat conduction equation; and 5, comparing the target temperature field with the real-time temperature field matrix, and adjusting the driving power of the corresponding unit in the out-of-tolerance region. Through continuous calibration and temperature adjustment, accurate control of a temperature field can be maintained in different use environments.

The invention discloses a vacuum adsorption device and an adsorption method, the device comprises a carrying table and a driving device, vacuum holes and sealing holes which are distributed in a staggered manner are formed in the surface of the carrying table, and a plurality of independently controlled vacuum areas are formed. Each area is provided with an independent vacuum pipeline, a pressure controller and a switch, and precise negative pressure regulation and control are achieved. The lifting sealing ring is arranged in the sealing hole, the height is adjusted through the driving device, and the position of the sealing ring and the warping state of the wafer are monitored in real time through the detection device. In the adsorption process, if warping exists, the height of the sealing ring is automatically adjusted, the wafer is flattened step by step in a subsection adsorption mode of subarea control, and global adsorption is started after the heights of all the sealing rings are consistent. According to the method, the problem that a traditional adsorption mode is poor in adaptability to large-warping wafers is effectively solved through the partition control and dynamic adjustment technology, the method has the advantages of being stable in adsorption, uniform in stress, low in breakage rate and the like, and the process compatibility and the production yield are remarkably improved.

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

A semiconductor structure includes a first transistor and a second transistor vertically stacked over the first transistor. The first transistor and the second transistor have horizontally aligned cell boundaries. A first set of one or more channels of the first transistor are horizontally offset from a second set of one or more channels of the second transistor within the horizontally aligned cell boundaries.

The invention discloses a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: carrying out the etching of a substrate through employing an etching technology, so as to form a high-aspect-ratio etching structure on the substrate; after a periodic cycle step of a preset number of times of etching process is completed every time, a treatment process different from the etching process is used, and partial thickness of a passivation layer deposited on the side wall of an intermediate structure formed before the high aspect ratio etching structure is formed is removed. And removing at least part of the protruding part which exists on the side wall and is exposed from the surface of the residual passivation layer. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using an organic vapor such as a carboxylic acid. In some implementations, the organic vapor is trifluoroacetic acid. In some implementations, the organic vapor is hexafluoro-acetylacetone. A metal-containing resist film such as an EUV-sensitive organo-metal oxide may be deposited on a semiconductor substrate using a dry or wet deposition technique. The metal-containing resist film on the semiconductor substrate may be developed using the organic vapor, or residue of metal-containing resist material formed on surfaces of a process chamber may be removed using the organic vapor.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

The invention relates to the technical field of chip processing, in particular to a chip multi-station welding self-adaptive clamping device which comprises a bearing frame, a support is arranged at the top of the bearing frame, a self-driven rotating disc is arranged in the support, a driving part of the self-driven rotating disc is arranged in the inner side of the support, and a gap is formed between the disc face of the self-driven rotating disc and the top face of the support. A plurality of positioning plates are symmetrically arranged on the top of the self-driven rotating disc in the circumferential direction, a plurality of clamping blocks are arranged on the tops of the positioning plates in a sliding and penetrating mode, and buffering parts are arranged in the clamping blocks. By means of single-shaft rotation driving of the self-driven rotary disc and threaded meshing transmission of the gradient disc, the spiral sleeve and the electric spiral rotary disc, synchronous control over clamping action of the clamping blocks and station switching of the rotary disc is achieved, an extra power source is not needed, the structure is remarkably simplified, and the multi-station welding efficiency is improved; the abutting rod spherical transition structure of the buffer part is designed to be matched with the rigidity of the second spring, the counter-acting force is automatically absorbed when the clamping block makes contact with the chip, and the clamping force is dynamically adjusted through the compression deformation quantity of the second spring to prevent the chip from being pressed and damaged.

A doped or undoped silicon carbide film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. One or more silicon-containing precursors are provided to a reaction chamber. Radical species, such as hydrogen radical species, are provided in a substantially low energy state or ground state and interact with the one or more silicon-containing precursors to deposit the silicon carbide film. A co-reactant may be flowed with the one or more silicon-containing precursors, where the co-reactant is a carbon-containing precursor and each silicon-containing precursor is a silane-based precursor with at least a silicon atom having two or more hydrogen atoms bonded to the silicon atom.

The invention discloses an automatic chip thermocompression bonding device and an intelligent calibration method, and belongs to the field of semiconductor packaging and manufacturing. The device comprises a main body frame, an alignment vision system, a side vision system, a bonding arm and a workbench, and micron-order alignment and eutectic bonding of a chip and a substrate can be realized. A bonding arm adopts a vacuum suction nozzle to suck a chip, a substrate is fixed on a workbench through vacuum adsorption, an alignment visual system realizes automatic precision calibration and position feedback of the device by using a calibration sheet, and micron-sized alignment and intelligent matching of chip thermocompression bonding process parameters are realized by collecting image feature recognition. The workbench is finely adjusted to align the marking points of the chip and the substrate, then the bonding arm carries out the thermocompression bonding process, and meanwhile, the side vision system monitors the precision and reliability of chip bonding. The chip alignment precision is high, the method is suitable for the scene that multiple chips are bonded at the same time, the problem that the equipment calibration efficiency is low in the thermocompression bonding process can be solved, and the process reliability can be improved.

The invention relates to the technical field of semiconductor mounting equipment, in particular to double-track die bonding equipment and a die bonding method. The double-track die bonding equipment comprises a bearing table, the bearing table is provided with a mounting area, a glue dipping area and a feeding area, and the glue dipping area and the feeding area are arranged adjacently and are adjacent to the same side of the mounting area; the mobile die bonding table assembly and the mobile transfer table assembly are arranged on the bearing table, the mobile die bonding table assembly comprises a first track, a second track, a first die bonding table and a second die bonding table, the first die bonding table is in sliding connection with the first track, and the second die bonding table is in sliding connection with the second track; the first track and the second track respectively extend from the glue dipping area to the mounting area. By introducing the design of the double die bonding tables which work alternately, glue dipping is only carried out on a partial area of the substrate each time, and chip mounting is immediately carried out on the partial area, so that the mounting quality and efficiency are ensured.

The invention provides a 2.5 D substrate packaging method and packaging structure, and relates to the technical field of semiconductor packaging. The 2.5 D substrate packaging method comprises the following steps: providing a carrier; wherein the carrier is provided with a flat part and a boss part; the boss part protrudes out of the flat part. Forming a first wiring layer on the boss part; forming a second wiring layer on the flat part; the first wiring layer and the second wiring layer are independent from each other. Mounting a first chip; the first chip comprises a plurality of first electric connection parts, at least one first electric connection part is electrically connected with the first wiring layer, and at least one first electric connection part is electrically connected with the second wiring layer; the length of the first electric connection part connected with the first wiring layer is smaller than that of the first electric connection part connected with the second wiring layer. Removing the carrier; and forming a solder ball on one side, far away from the first chip, of the second wiring layer. The inductance effect and the parasitic effect are reduced, the transmission path is shortened, the transmission efficiency is improved, and the chip integration level and the product performance are improved.

Embodiments of the present disclosure generally relate to an electrostatic chuck assembly suitable for use in cryogenic applications. In one or more embodiments, an electrostatic chuck assembly is provided and includes an electrostatic chuck having a substrate supporting surface opposite a bottom surface, a cooling plate having a top surface, where the cooling plate contains an aluminum alloy having a coefficient of thermal expansion (CTE) of less than 22 ppm / ° C., and a bonding layer securing the bottom surface of the electrostatic chuck and the top surface of the cooling plate.

The invention provides a packaging and sintering evaluation method and device for a power semiconductor device, and the method comprises the steps: carrying out the non-destructive scanning through a high-frequency acoustic microtechnique, carrying out the correction through combining with a temperature-sound velocity relation model, achieving the real-time monitoring of a sintering process, and solving a problem that the transient change cannot be captured. Through frequency domain conversion and an improved inverse Fourier transform algorithm, precise reconstruction of the microstructure of the sintering interface is realized, and the limitation that the microstructure is difficult to evaluate in the prior art is overcome. Based on the reconstructed microstructure, a detailed three-dimensional geometric model is established, and time domain finite element analysis is performed, so that comprehensive thermal stress evolution data is obtained, and the defect of surface information of a traditional method is overcome. And quantitative evaluation is carried out by using the multi-dimensional feature space and the preset discrimination model, so that comprehensive analysis of the sintering quality is realized, and the defect of lack of comprehensive quantitative evaluation capability is overcome. Through organic combination of the steps, the accuracy and comprehensiveness of packaging and sintering evaluation are remarkably improved.

Methods of forming a metal-containing layer on a semiconductor substrate are provided and may include performing multiple cycles of (a) co-flowing a metal-containing precursor and a reactant into a processing chamber housing the semiconductor substrate; and (b) after (a), flowing the reactant into a processing chamber housing the semiconductor substrate, wherein the reactant does not react with gas-phase metal-containing precursor. Methods of cleaning the processing chamber are also provided.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

The invention relates to a stacking packaging method and system for AI-DSP mixed audio processing chips, and the method comprises the following steps: employing a first bonding machine to carry out the flip-chip bonding of an AI chip and a DSP chip, and obtaining a flip-chip bonding chip; the flip-chip bonding chips are interconnected, and an interconnected chip structure is obtained; vertically stacking the interconnected chip structures to obtain a stacked chip structure; packaging the stacked chip structure by adopting a second bonding machine to obtain a packaging body; according to the AI-DSP mixed audio processing chip and the packaging method thereof, the packaging body is subjected to heat dissipation treatment through the preset heat dissipation substrate, the packaged AI-DSP mixed audio processing chip is obtained, and the technical problems that in a traditional packaging scheme, an AI chip and a DSP chip generally adopt different process nodes and manufacturing processes, and thermal expansion coefficients are not matched and stress distribution is uneven during direct integration are solved.

The invention relates to the technical field of semiconductor manufacturing, in particular to an automatic loading and unloading control system for semiconductor material plates. A clamping force dynamic control module; the path planning and obstacle avoidance module is used for dividing safety levels of loading and unloading areas on the basis of material plate stacking parameters, and generating an obstacle avoidance track by adopting an improved path search algorithm; optimizing an acceleration curve of the path according to the joint load data of the mechanical arm; the closed-loop verification module is used for carrying out deviation comparison on the actual pose of the tail end of the mechanical arm and the target coordinates, and if the deviation exceeds the limit, the visual positioning and morphology detection module is triggered to cooperatively reset to the path planning and obstacle avoidance module; the visual positioning and morphology detection module and the closed loop verification module are executed in sequence, and output parameters of the previous module serve as input parameters of the next module. Through close cooperation of the modules, efficient and accurate automatic loading and unloading control is achieved, the automation level is improved, and operation safety and accuracy are guaranteed.

The invention relates to a semiconductor cleaning anti-splash shield and semiconductor cleaning equipment, and the semiconductor cleaning anti-splash shield is used for preventing liquid drops thrown out by a rotating wafer (101) in the tangential direction from being splashed and comprises a shield body (1) which comprises a side wall (11), and the side wall (11) is annular and coaxially surrounds the wafer (101); the anti-splash assembly (2) is arranged in the cover body (1), the anti-splash assembly (2) comprises a first annular plate (21), a second annular plate (22) and an anti-splash component (20), the first annular plate (21) and the second annular plate (22) are both connected to the side wall (11) and are arranged at intervals from top to bottom in the height direction, and the anti-splash component (20) is connected between the first annular plate (21) and the second annular plate (22); the anti-splash component (20) and the side wall (11) are arranged at intervals in the radial direction of the cover body (1) to form an annular containing cavity (4), and the anti-splash component (20) is provided with a channel for liquid drops to enter the containing cavity (4).