139284results about "Semiconductor/solid-state device manufacturing" patented technology

A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.

The invention provides a defect detection method and system for integrated circuit manufacturing. Wherein in the integrated circuit packaging stage, packaged chips are divided into a first type of chips meeting a preset physical characteristic threshold value and a second type of chips exceeding the physical characteristic threshold value through a pneumatic sorting device; performing scanning electron microscope imaging on the surface of the second type of chip, generating a three-dimensional topological structure by using an image reconstruction technology, and positioning a micron-sized particle defect area by comparing reference type differences; synchronously applying high-frequency electric signal excitation in the sorting process, detecting impedance response of the second type of chips, and recording an abnormal signal sequence exceeding a preset frequency domain range; performing space-time correlation matching on the micron-sized particle defect area and the abnormal signal sequence, and judging that the defect is a multi-layer composite defect when a preset coupling condition is met; and dynamically adjusting the mesh diameter and vibration frequency parameters of the pneumatic sorting device. According to the technical scheme provided by the invention, accurate identification of the multi-layer composite defect of the chip is realized, and the defect interception efficiency is remarkably improved.

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

In the present disclosure, a first semiconductor element of a bonded structure comprises a semiconductor-containing oxynitride bonding layer formed on a first substrate layer comprising a semiconductor material, e.g., a single crystal silicon. The semiconductor-containing oxynitride bonding layer is formed by exposing an upper surface of the first substrate layer to products of plasma containing nitrogen and oxygen at controlled plasma conditions. The second semiconductor element of the bonded structure may have a second substrate layer comprising a semiconductor material, e.g., a single crystal silicon, and a semiconductor-containing oxynitride bonding layer formed over the second substrate layer in the same way as the first semiconductor element. In some embodiments, the second semiconductor element may have a bonding layer comprising a dielectric material. After initial direct bonding of the first and second semiconductor elements, the bonded structure may go through an annealing process to strengthen the bonding.

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

The invention provides a wafer factory-level real-time scheduling method in semiconductor manufacturing based on deep reinforcement learning, which relates to the technical field of semiconductors, and comprises the following steps: constructing a state space vector by collecting equipment state, batch information and process flow information based on deep reinforcement learning, inputting a pre-trained deep reinforcement learning network model, and constructing a state space vector; the model includes a value assessment network and a policy network. The model generates matching probability distribution of batches and devices, a hierarchical reinforcement learning method is adopted to decompose the distribution into two sub-tasks of batch selection and device allocation, and a plurality of candidate matching schemes are generated. And then evaluating the candidate schemes by applying a multi-target reward and punishment function, selecting an optimal scheduling scheme in combination with a Monte Carlo tree search algorithm, and issuing a processing instruction. And real-time processing data is collected in the working procedure processing process to update the state space vector, so that real-time scheduling is realized.

Photoresist rework of metal-containing photoresist is disclosed. Rework can be accomplished using a thermal process by exposing a substrate to an elevated temperature and an etch gas. Rework can be also accomplished using a wet process by exposing the substrate to an inorganic acidic solution. Residue or other contaminants may be cleaned up from the substrate after rework by exposure to high temperatures, plasma, or wet clean.

The invention relates to the technical field of chip mounting processing, and discloses an optical alignment system and method for chip mounting processing, and the method comprises the steps: collecting a target chip image and a target substrate image in a mounting process through an upper visual field camera disposed above a suction nozzle assembly and a lower visual field camera disposed above a substrate carrying platform; chip edge accurate coordinates in the target chip image are extracted, and reference mark accurate coordinates in the target substrate image are extracted; solving a chip mounting process compensation parameter matrix of an upper and lower camera-suction nozzle-substrate four-coordinate system in the chip mounting process based on the chip edge accurate coordinate and the reference mark accurate coordinate; calculating an X-Y-theta three-dimensional alignment compensation vector in the chip mounting process according to the mounting process compensation parameter matrix; on the basis of the X-Y-theta three-dimensional alignment compensation vector, the optimal mounting track parameter is calculated, an execution instruction sequence is generated, the problem of error accumulation caused by traditional independent calibration is effectively solved, and the alignment precision is remarkably improved.

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention discloses an AI-driven gold bonding wire process parameter optimization method and system, and relates to the technical field of semiconductor packaging, and the method comprises the steps: building a dual-channel deep learning network of a bonding process; the dual-channel deep learning network comprises a dynamic parameter optimization channel and a static parameter optimization channel; inputting bonding process dynamic data collected in real time and preset bonding process static data into the dynamic parameter optimization channel to obtain a dynamic process evaluation index; inputting preset bonding process static data into the static parameter optimization channel to obtain a static process evaluation index; and fusing the dynamic process evaluation index and the static process evaluation index through an adaptive weight fusion algorithm to obtain a comprehensive evaluation index, and optimizing the bonding process parameters. According to the invention, dynamic and static data are integrated through a dual-channel deep learning network architecture, intelligent and accurate optimization of bonding process parameters is realized in combination with an adaptive weight fusion algorithm, and the bonding quality and process stability are significantly improved.

The invention discloses a wafer cleaning and drying process, a wafer drying machine and a cleaning and drying structure assembly thereof, relates to the field of wafer cleaning equipment, and can solve the problem of poor regulation and control precision of an electromagnetic pump and a plurality of valves with different calibers through manual adjustment in the prior art. The wafer drying machine comprises a main body and a lifting mechanism connected to the main body. The cleaning and drying structure assembly comprises a drying groove body, a liquid inlet pipe, an IPA bubbling box, a first liquid discharging pipe and a controller. A groove cover is connected to a groove opening of the drying groove body; the first liquid discharge pipe is connected with an electromagnetic pump, a first valve and a flowmeter used for measuring the flow speed of liquid in the first liquid discharge pipe, and the electromagnetic pump and the flowmeter are both electrically connected to the controller so that the controller can control the flow of the electromagnetic pump according to signal feedback of the flow speed of the liquid in the first liquid discharge pipe by the flowmeter.

The invention discloses a wireless temperature measuring device suitable for a semiconductor vacuum chamber, and belongs to the technical field of wafer temperature measurement, a device main body comprises an upper silicon wafer and a lower silicon wafer, a wireless temperature measuring assembly is arranged between the upper silicon wafer and the lower silicon wafer, and the wireless temperature measuring assembly is composed of a circuit, a temperature measuring device, a battery and a master controller. The circuit is arranged between the upper silicon wafer and the lower silicon wafer, the temperature measuring device, the battery and the master controller are all electrically connected with the circuit, and the upper silicon wafer and the lower silicon wafer are bonded through high-temperature bonding glue; during specific implementation, temperature measurement is performed on the interior of the wafer through the temperature measurement device, obtained temperature data are uploaded to a cloud end through the master control, the battery is a power supply of the temperature measurement device and the master control, the wireless temperature measurement device can eliminate partial pollution caused by wired temperature measurement during use, through holes are prevented from being formed in the processing chamber, and the processing efficiency is improved. And the manufacturing difficulty is reduced and the temperature measurement effect is good.

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

The invention discloses an automatic wafer grinding system. The automatic wafer grinding system comprises a rack, a feeding unit, a first picking unit, a positioning unit, a reference piece bearing unit, a second picking unit, a machining unit, a cleaning unit and a discharging unit, wherein the feeding unit, the first picking unit, the positioning unit, the reference piece bearing unit, the second picking unit, the machining unit, the cleaning unit and the discharging unit are arranged on the rack. The information acquisition unit is used for acquiring material and position information of the wafers and the reference sheets, and the control system is used for controlling the units to transport and process the wafers. All the units are controlled through the information acquisition unit and the control system, automatic conveying and machining of wafers are achieved, the in-place precision and the machining efficiency of the wafers are improved, and the wafer machining quality is guaranteed. The invention further provides an automatic wafer grinding method, by means of the automatic wafer grinding system, the in-situ feeding and in-situ discharging principle of feeding and discharging is perfectly met, and meanwhile the labor intensity of operators is reduced.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

A wafer placement table 10 comprises: a ceramic plate 20 having a wafer placement surface 22 on the upper surface thereof; and a cooling plate provided on the lower surface of the ceramic plate 20. A refrigerant flow path 32 built into the cooling plate has a first portion 32x, and a second portion 32y branching from the first portion 32x into two or more paths that run in parallel to each other. The cross-sectional area of the first portion 32x is smaller than the sum of the cross-sectional areas of the paths of the second portion 32y.

The present disclosure relates to use of an acid for developing or treating a radiation-sensitive film including two or more elements having a high patterning radiation-absorption cross-section. The acid can be employed to form a pattern by a negative tone development process or to treat a developed pattern by further removing residual resist components.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography.

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell, an etching-free manufacturing method thereof and a cell assembly, and the method comprises the steps: depositing an intrinsic amorphous silicon layer on a backlight surface of a silicon wafer; forming first doped regions, second doped regions and co-doped regions between the first doped regions and the second doped regions on the outer surface of the intrinsic amorphous silicon layer, wherein the first doped regions and the second doped regions are alternately distributed; and arranging a hard mask on the outer surface of the co-doped region, and depositing a conductive film layer and a metal electrode on the backlight surface. According to the invention, the use of high-temperature laser and chemical etching is avoided, so that the damage to the battery and the environmental pollution are reduced, the production yield is remarkably improved, the production cost is remarkably reduced, the reliability of the battery is improved, the service life of the battery is prolonged, and good battery efficiency can be obtained.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

A laser processing apparatus irradiates a target with a laser light to form a modified region along a virtual plane in the target. The laser processing apparatus includes a support portion, an irradiation portion, a movement mechanism, and a controller. The controller performs a first processing process of irradiating a first portion in the target with the laser light under a first processing condition, and a second processing process of irradiating a second portion more on an inner side than the first portion in the target with the laser light under a second processing condition different from the first processing condition, after the first processing process.

A wafer processing method includes forming a bonded wafer by bonding a first wafer to a second wafer, irradiating a laser beam along a position separate inward from an outer circumferential edge by a predetermined distance in an annular manner and forming, inside the first wafer, an annular modified layer and cracks that extend from the modified layer toward a front surface side to cause warpage in the outer circumferential region. The method also includes detecting the amount of warpage of the outer circumferential region, determining whether or not bonding between the first wafer and the second wafer has been released on the basis of the amount of warpage of the outer circumferential region, deciding whether or not to execute a grinding step, and if so, grinding the first wafer from a back surface side.

The current invention offers a method for preparing an electronic integrated circuit (EIC) for the assembly of an optical engine. The method involves stacking a CMOS-based EIC wafer onto a short loop / interposer wafer through face-to-back bonding. This stacked configuration serves as a carrier for the thin CMOS wafers. Subsequently, the stacked wafers are thinned down to the desired height and undergo a via last process. In this process, the thick metal layer from the short loop / interposer wafer acts as an etch stop. The stacked EIC wafers can then be diced and attached to a photonic integrated circuit (PIC) wafer, resulting in the formation of an optical engine.

The invention provides a 2.5 D substrate manufacturing method and a packaging structure. The 2.5 D substrate manufacturing method comprises the following steps: providing a first carrier on which a metal part and an intermediate layer are mounted; a metal column is arranged in the intermediate layer; forming a protective layer covering the metal component and the interposer on the first carrier; a first recess is formed on the metal feature. The interposer and the protective layer are ground such that the interposer and protective layer surfaces are lower than the surface of the metal feature. Forming a first dielectric layer with a first opening on the surfaces of the intermediate layer and the protective layer; the first opening exposes the metal column. Forming a seed layer in the first opening; the seed layer extends to the surface of the metal part and fills the first groove. A wiring layer is formed on the seed layer. The bonding force of the seed layer and the first dielectric layer can be improved, the corrosion to the side wall of the interposer in the etching process is prevented, and the packaging quality and precision are improved.

The invention provides a chip production logistics network optimization method and system based on a graph neural network model, and relates to the technical field of chip production logistics optimizing.The method comprises the steps that logistics data of a plurality of process nodes of a chip production line are collected, node criticality scores are calculated, node types are determined, and the node types are determined; constructing a multi-level logistics network diagram comprising a material transmission edge and a priority-based resource competition edge; the method comprises the following steps: dividing logistics sub-networks, determining association strength among the sub-networks, constructing a sub-network state predictor and a cooperative scheduling module, and inputting a network topology structure and node features into a graph neural network for training to obtain an optimization model; and predicting a sub-network state change based on the optimization model to generate a resource allocation scheme and a node scheduling sequence, triggering an adjustment mechanism when a prediction state exceeds a threshold value, re-planning a material allocation and transmission path, and finally converting the scheme into an equipment control instruction and issuing the equipment control instruction to a process node.

The invention relates to the technical field of laser material processing, and discloses a laser annealing temperature control method and device.The method comprises the steps that the specific heat capacity, the heat conductivity coefficient, the heat diffusivity, the heat radiation rate, the heat reflectivity and the heat loss coefficient are obtained, and a material thermal characteristic model is established; performing grid division according to the material thermal characteristic model to obtain a laser energy density parameter; extracting a thermal strain coefficient according to the laser energy density parameter, and establishing a temperature-thermal strain mapping relation prediction model; dynamically adjusting a laser power proportion and a pulse width time sequence according to the temperature-thermal strain mapping relation prediction model to obtain temperature field distribution data; according to the temperature field distribution data, carrying out shortest path analysis to obtain a temperature regulation and control decision; and according to the temperature regulation and control decision, inputting a preset control regulation model, and combining reinforcement learning iteration optimization parameters to obtain a temperature control scheme. According to the method, large-range temperature crossing and fine adjustment in an extremely short time can be realized.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.