26899results about "Semiconductor/solid-state device manufacturing" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention relates to a stacking packaging method and system for AI-DSP mixed audio processing chips, and the method comprises the following steps: employing a first bonding machine to carry out the flip-chip bonding of an AI chip and a DSP chip, and obtaining a flip-chip bonding chip; the flip-chip bonding chips are interconnected, and an interconnected chip structure is obtained; vertically stacking the interconnected chip structures to obtain a stacked chip structure; packaging the stacked chip structure by adopting a second bonding machine to obtain a packaging body; according to the AI-DSP mixed audio processing chip and the packaging method thereof, the packaging body is subjected to heat dissipation treatment through the preset heat dissipation substrate, the packaged AI-DSP mixed audio processing chip is obtained, and the technical problems that in a traditional packaging scheme, an AI chip and a DSP chip generally adopt different process nodes and manufacturing processes, and thermal expansion coefficients are not matched and stress distribution is uneven during direct integration are solved.

The invention relates to the field of photovoltaic cell production, and discloses a main-grid-free photovoltaic cell series welding method and main-grid-free photovoltaic cell series welding device.The method comprises the steps that main-grid-free photovoltaic cell pieces and welding strips are conveyed to a pre-welding device, heating is conducted, so that the welding strips are pre-fixed to the surfaces of the corresponding main-grid-free photovoltaic cell pieces, and cell series arrays are obtained; synchronously transmitting the battery series and the back film layer to a heating and pressurizing device, and laying a front film layer on the battery series; and controlling the heating and pressurizing device to move to be in contact with the front film layer on the battery string, and heating and pressurizing the front film layer to obtain the battery string. The method comprises the following steps of: pre-fixing a battery piece and a welding strip, laminating, and heating and pressurizing a front film layer. During heating and pressurizing, a hold-down tool does not need to be placed on the front face, uneven heating is avoided, the problems of film bubbling and pseudo soldering are avoided, the welding quality can be guaranteed, and the conditions of pseudo soldering and grid breaking are reduced. And heating and pressurizing are carried out after pre-welding, so that the solder strip can be prevented from deviating.

The invention provides a data detection method and system, a detection device, computer equipment and a storage medium, and the method comprises the steps: obtaining a detection signal of each wafer surface in a planetary reaction cavity, and cutting the detection signal based on a trigger signal to obtain a first signal sequence and a second signal sequence; processing the first signal sequence by adopting a classification model to obtain a material type on each wafer; querying a corresponding optical model based on the material type; and performing iterative optimization on the optical model, the first signal sequence and the second signal sequence by adopting a decoupling algorithm to obtain a temperature detection value and a reflectivity detection value. According to the method, the original detection signal is segmented into the independent signal sequences based on the trigger signal, then the material type is determined according to the independent signal sequences, the corresponding optical model is selected according to the material type, and finally the temperature detection value and the reflectivity detection value with high accuracy are obtained through decoupling according to the optical model. Accurate analysis of a single wafer signal is realized, and process repeatability and stability are greatly improved.

To provide a stage unit and a processing system which are advantageous for accurately positioning an electronic component at a desired position.SOLUTION: The stage unit 10 includes the base 11, the stage 12 on which the electronic component is placed, the stage moving mechanism 13 that moves the stage 12 with respect to the base 11, the movement measuring sensor 37 capable of directly or indirectly measuring the movement amount of the stage 12, and the control unit that controls the stage moving mechanism 13 based on the movement instruction command signal and moves the stage 12 so as to be arranged at the adjustment position indicated by the movement instruction command signal. The control unit controls the stage moving mechanism 13 based on the movement amount of the stage 12 indicated by the measurement result of the movement measuring sensor 37 and the adjustment position.SELECTED DRAWING: Figure 1

The present disclosure provides an automated die bonding of LED substrates system in which an automated die bonding inspection module is used to determine the quality of incoming processing material and an automated die bonding process module is used to process the processing material, an automated die bonding post-process module is used to inspect the resultant process material for acceptability, and an automated die bonding historical module is used to analyze the post process results of the most recent process, against all historical data to find enhanced process changes in the automated die bonding process module and an automated die bonding integration module to update the automated die bonding process module based upon the results of the automated die bonding historical module.

The invention relates to a system and method for rapidly establishing steady state vacuum chamber pressure. According to the system, the set value of the vacuum valve is fixed, and the driving current of the MFC electromagnetic valve is used for adjusting the pressure of the cavity, so that the pressure is stabilized more quickly. The system can operate in a training mode and an inference mode. In the training mode, a PID controller is used for determining set values of an MFC and a vacuum valve; in an inference mode during substrate processing, these settings are quickly invoked and executed, thereby achieving efficient and stable pressure control.

The invention relates to a rapid gas delivery system and method for atomic layer etching. The system utilizes a compact gas buffer disposed near the gas distribution unit, enabling faster and more efficient delivery of gas to the chamber. The controller manages the gas flow of the gas buffer to maintain an amount of gas within the gas buffer required to perform a single ALE cycle. When one gas buffer delivers gas to the chamber for a partial ALE step, gas is concurrently delivered to the other gas buffer. The configuration not only can improve the efficiency, but also can save components such as a pressure gauge, thereby saving the cost.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

The invention relates to the field of packaging substrates, in particular to a heterogeneous stack-up packaging substrate and a manufacturing method thereof. A glass core plate is arranged in the packaging substrate, and one or more first core plates are arranged between the surface of the packaging substrate and the glass core plate; one or more circuit layers are arranged between the glass core plate and the first core plate; one or more circuit layers are arranged between the first core boards; one or more circuit layers are arranged between the first core board and the surface of the substrate; the packaging substrate is internally provided with a metal column, and the metal column is connected with the circuit layer. Different dielectric materials and different core plates are matched in the manufacturing process of the packaging substrate, so that the problem of warping of the dielectric materials caused by expansion and shrinkage and stress or temperature change in the stacking process can be effectively solved, and the flatness of the large-size substrate in the machining process is effectively ensured. The technology of an upper-layer thin circuit and a lower-layer thick circuit is realized. And the manufacturing feasibility of the large-size packaging substrate is greatly improved.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

The invention provides a preparation method of a package carrier plate, the package carrier plate and a package structure. The preparation method of the package carrier plate comprises the steps that conductive columns and filling materials are placed in through holes; and curing the filling material to form a filling part. The conductive columns do not need to be prepared in the through holes in an electroplating mode, so that the packaging carrier plate with a high aspect ratio can be prepared conveniently, pores generated in the conductive columns due to non-uniform diffusion of electroplating liquid medicine in the through holes can be avoided, and the electrical performance and the reliability of the packaging carrier plate are ensured. Meanwhile, the arrangement of the filling parts can enhance the connection stability between the conductive columns and the substrate.

According to the driving control circuit for the electrostatic chuck power supply and the electrostatic chuck power supply, the driving control circuit is arranged in the electrostatic chuck power supply, a high-voltage output voltage signal of a high-voltage amplifying circuit can be obtained through a signal generating and processing feedback circuit, and according to a negative feedback adjusting mechanism, the driving control circuit is used for driving the electrostatic chuck power supply. A power supply waveform control signal for controlling a high-voltage amplification circuit to output a high-voltage output voltage signal is adjusted, and the high-voltage output voltage signal output by the high-voltage amplification circuit is adjusted to be output, so that the effect of controlling the signal precision of the high-voltage output voltage signal output by the electrostatic chuck power supply is achieved, and the output stability of the electrostatic chuck power supply is improved. Therefore, the stability of an electrostatic field generated by the electrostatic chuck is guaranteed, and the wafer fixing process precision of the electrostatic chuck is ensured.

A composition for an organic optoelectronic device, an organic optoelectronic device, and a display device, the composition including a first compound represented by Chemical Formula I, a second compound represented by Chemical Formula II, and a third compound represented by a combination of Chemical Formula III and Chemical Formula IV,

The invention relates to a chip integrated heat dissipation system and a preparation method thereof, and belongs to the technical field of heat dissipation of semiconductor devices. The chip integrated heat dissipation system comprises a nano-diamond transition layer attached to a chip. A micro-column array supporting layer is arranged on one side, far away from the chip, of the nano-diamond transition layer; the micro-column array supporting layer is in contact with one surface of the diamond film, and the other surface of the diamond film is attached to the three-dimensional micro-channel heat dissipation layer. The invention also provides a preparation method of the chip integrated heat dissipation system. The chip integrated heat dissipation system provided by the invention has the advantage of efficient heat dissipation, and through the combination of the three-dimensional structure and the high heat conduction characteristic of diamond, the heat dissipation power density is remarkably improved, the junction temperature of the chip is reduced, and the heat dissipation requirement of a high-power device is met. The heat dissipation performance reliability is high, the thermal stress is eliminated through the gradient structure design, the interlayer binding force is improved, and the stable performance is still kept after multiple thermal cycles. And the preparation process is good in compatibility and convenient for large-scale production.

The invention relates to the technical field of wafer test equipment, in particular to a heating aging test tool which comprises a storage rack and further comprises a wafer clamp placed on the storage rack. The detection assembly comprises a plurality of elastic probes located on one side of the storage rack and a heating disc; and the hot air guide assembly comprises a ventilation male head arranged on one side of the heating disc, an air guide pipe is arranged on the side, away from the ventilation male head, of the heat conduction cover, the air amount in the cavity is gradually decreased from near to far away from the air guide pipe, and the air flow speed is gradually decreased. A hot air flow guide assembly is arranged on a conveying frame, heat of a heating disc is guided to the position above a wafer through airflow through a heat conduction cover, the space above the wafer is divided into a plurality of cavities, the space size and the space shape of each cavity are set, the air flow speed and the contained hot air amount of each space are adjusted, and therefore the heat conduction efficiency of the wafer is improved. The influence of heat loss in the air flow process is reduced, so that the heating effects of all parts of the wafer are similar, and the detection effect is improved.

Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

The CPO system packaging method provided by the embodiment of the invention comprises the following steps: by taking a high-resistance silicon wafer as a base material, completing processing of a silicon intermediate layer through spiral micro-channel etching, silicon through hole preparation, electroplating hole filling and back thinning; integrating the silicon optical chip and the electronic chip to the silicon interposer through the diamond micro bump array containing the copper core; installing a piezoelectric micropump at a corresponding fluid interface in the silicon intermediate layer, and filling adaptive liquid into the communicated flow channels in a vacuum environment; and after the reliability verification test is passed, carrying out system packaging by adopting an anti-static shielding bag. The CPO system adopting the packaging process has the advantages of high heat dissipation efficiency, ultrahigh integration precision and strong environmental adaptability.

A substrate support assembly includes a cooling plate and a chuck disposed on the cooling plate. The chuck includes one or more heating electrodes, and one or more clamp electrodes to electrostatically secure the chuck to the cooling plate. Another substrate support assembly includes a cooling plate, a first puck plate bonded to the cooling plate, and a second puck plate disposed on the first puck plate. The second puck plate includes one or more clamp electrodes to electrostatically secure the second puck plate to the first puck plate.

Semiconductor circuit structures with direct die heat removal structure are provided. The semiconductor circuit structure comprises a semiconductor substrate with an original semiconductor surface; a set of active regions within the semiconductor substrate; and a first shallow trench isolation (STI) region neighboring to the set of active regions and extending along a first direction. Wherein the first STI region includes a heat removing layer, and the material of the heat removing layer is different from SiO2.

The invention provides a temperature control system of an electrostatic adsorption disc and an improvement method of temperature control performance. According to the system, a temperature control layer is arranged in an electrostatic adsorption disc, and the temperature control layer comprises a graphite heat absorption layer and a graphene heat conduction layer; the system further comprises a laser generator and a controller. During working, the laser generator emits heating laser to the graphite heat absorption layer, so that the graphite heat absorption layer efficiently absorbs energy to generate heat, and then the heat is quickly and uniformly conducted to the surface of the electrostatic adsorption disc through the graphene heat conduction layer with ultrahigh heat conductivity. Laser heating is used for replacing traditional resistance heating, graphene heat conduction is used for replacing traditional metal heat conduction, the method has the advantages of being high in temperature switching speed, high in control precision, good in temperature uniformity and the like, and the temperature control performance of the electrostatic adsorption disc can be remarkably improved.

The invention provides a wafer thinning equipment control method and device, electronic equipment and a storage medium, and relates to the technical field of wafer thinning. The method comprises the following steps: monitoring spreading and thinning behaviors of a spin-coating liquid film in real time and generating a residual layer distribution diagram; according to an area indicated by the residual layer distribution map, obtaining local thickness information by analyzing a fluorescence signal received from the area; after a laser beam is used for scanning the surface of the wafer, micro-vibration signals are recognized and extracted by analyzing reflected light signals; dividing the surface of the wafer into a plurality of grid areas; and the risk of generating cracks in each grid area is evaluated, and a wafer surface risk thermodynamic diagram used for controlling the grinding head and the grinding fluid is generated. The method aims at solving a series of problems caused by a microcosmic residual layer on the surface of the wafer or surface energy difference in the wafer thinning process, early and accurate sensing of microcosmic abnormity on the surface of the wafer is achieved, and a control system is guided to conduct regional and self-adaptive grinding parameter adjustment.

An example polishing system, such as an electrochemical mechanical polishing (ECMP) system, includes a polishing pad assembly having a polishing pad. The example polishing system includes a bias source. The example polishing system includes a workpiece carrier operable to bring the semiconductor workpiece into contact with the polishing pad. In some implementations, the polishing pad assembly is operable to provide an electrically conductive path for one or more charge carriers to the bias source.

The utility model discloses a valve device and a semiconductor device processing device. The valve apparatus includes: a valve body including an external coil therein; the valve plate is movably arranged in the valve body, and the opening degree of the valve equipment is adjusted by adjusting the pose of the valve plate; and an internal coil provided inside the valve plate, the internal coil generating an eddy current through an alternating magnetic field generated in the valve body by an alternating voltage applied to the external coil to inductively heat the valve plate. By means of the valve equipment, the surface of the valve plate can be directly heated, the temperature of the valve plate is increased, and therefore blockage of the valve plate caused by deposition of reaction by-products on the valve plate in the carbon mask deposition process is reduced.

The invention provides an LPDDR packaging method, which can effectively reduce the packaging thickness and can effectively improve the heat dissipation capability of a product. The method is characterized in that redistributed solder balls are led out from each stacked LPDDR chip through vertical routing, then the whole stacked assembly is turned over, and an EMI plating layer is plated on the periphery of a plastic package body of the stacked assembly.

The invention provides a cooling device for semiconductor manufacturing, which is characterized in that a choke plate divides a cooling cavity into a first cavity and a second cavity, and the first cavity and the second cavity are respectively communicated with an air inlet and an air outlet; the return assembly is arranged on the shell and connected with the choke plate, and the return assembly is used for providing reset driving force for the choke plate in the first direction; an air flow channel for air circulation is formed between the choke plate and the liquid level of cooling liquid in the cooling cavity, the first cavity and the second cavity are communicated through the air flow channel, and when the air inlet pressure of the air inlet is increased, air flow pushes the choke plate to move towards one side of the second cavity so as to increase the size of the first cavity; and when the air inlet pressure is reduced, the return assembly drives the choke plate to reset towards one side of the first cavity. According to the cooling device for semiconductor manufacturing, the problems that in the prior art, due to fluctuation of the liquid level of cooling liquid, the cooling efficiency is reduced, and the gas-liquid separation effect is poor are solved.

The invention discloses a treatment method for helium holes of an electrostatic chuck, and belongs to the technical field of electrostatic chucks, and the treatment method comprises the following steps: S1, pretreating a gas passage opening and the surface of a substrate: cleaning the helium holes and fine cracks of the substrate, and roughening the surface of the substrate; s2, a ceramic piece is glued to the helium hole opening, wherein the ceramic piece and the side wall of the helium hole opening are tightly attached and bonded together through an adhesive; s3, filling the helium hole ceramic piece with insulating glue: filling holes, cracks and other fine interfaces; s4, grinding the insulation paste filling part to be flush with the surface of the substrate so as to keep the overall flatness; s5, performing meltallizing on the surface of the substrate by using a meltallizing process to obtain the meltallizing coating, uniformly covering the insulating glue filling layer with the meltallizing coating, and forming good combination with the substrate; and S6, grinding and polishing: after the meltallizing coating is completed, grinding or polishing the meltallizing coating to ensure that the surface of the meltallizing coating is smooth.

The invention provides a cutting height adjusting method and device of a cutting knife, wafer processing equipment and a medium, and relates to the technical field of wafer processing equipment.The method comprises the steps that the surface height difference between a sample silicon wafer on an auxiliary workbench and a to-be-processed wafer on a main working disc is measured; after the cutting knife cuts the sample silicon wafer to form a cutting mark, calculating a cutting depth value corresponding to the cutting mark; calculating the surface height information of the sample silicon wafer according to the cutting depth value of the cutting mark and the height information corresponding to the lowest point of the cutting knife when the cutting knife cuts the sample silicon wafer on the auxiliary workbench; and according to a preset cutting depth value, the surface height information of the sample silicon wafer and the surface height difference between the sample silicon wafer on the auxiliary workbench and the to-be-processed wafer, target cutting height information of the cutting knife when the cutting knife cuts the to-be-processed wafer is determined. After the height of the cutting knife is adjusted according to the target cutting height information, the cutting mark cut by the cutting knife has high-precision cutting depth.

Provided are organometallic compounds including a ligand LA ofAlso provided are formulations including these organometallic compounds. Further provided are OLEDs and related consumer products that utilize these organometallic compounds.

This disclosure relates generally to a patterning structure including an underlayer and an imaging layer, as well as methods and apparatuses thereof. In particular embodiments, the underlayer provides an increase in radiation absorptivity and / or patterning performance of the imaging layer.