361 results about "Single crystal substrate" patented technology

The invention relates to the technical field of defect characterization of silicon carbide single crystal substrate materials, in particular to a silicon carbide corrosion device and a working method thereof. The silicon carbide corrosion device comprises a crucible furnace, an inner lifting shaft and a basket; the crucible furnace comprises a furnace body and a furnace cover, a heating element is arranged outside the furnace body, the furnace body is provided with an oxygen inlet used for introducing oxygen and a gas discharge port used for discharging gas, the furnace cover covers the furnace body, the top of the furnace cover protrudes upwards to form an outer lifting shaft used for lifting the furnace cover, and the outer lifting shaft is provided with a through hole; the inner lifting shaft is inserted into the through hole of the outer lifting shaft, and the basket is installed at the bottom end of the inner lifting shaft and used for containing wafers. According to the method, different dislocation morphologies of the heavily nitrogen-doped substrate can be accurately distinguished, the corrosion efficiency is improved, the safety of operators is guaranteed, meanwhile, the operation process is simplified, and large-scale popularization and application are facilitated.

The invention belongs to the technical field of machining and cutting, and particularly relates to a temperature-sensing diamond cutter with local boron-doped cutting edges and a manufacturing method of the temperature-sensing diamond cutter. The temperature-sensing diamond cutter with the local boron-doped cutting edge comprises a diamond single crystal substrate, the diamond single crystal substrate has a certain thickness, a local boron-doped diamond single crystal layer is deposited at a corner position of the top surface of the diamond single crystal substrate, the corner position is used for arranging the cutter cutting edge, and the local boron-doped diamond single crystal layer is deposited at the corner position of the top surface of the diamond single crystal substrate. The local boron-doped diamond single crystal layer can be used as a temperature sensor to sense the temperature of an ultra-precise cutting edge micro-area by using the negative temperature coefficient thermosensitive characteristic of the local boron-doped diamond single crystal layer as a P-type semiconductor. Insulation of the outer surface of the boron-doped diamond layer is achieved, and the problem that when the tool cuts various workpieces with high conductivity, due to the fact that the thermal sensitive characteristic of the boron-doped diamond layer is affected by electric conduction between the tool and chips, the cutting temperature cannot be measured is solved.

The invention discloses a method for manufacturing a high-power nitride semiconductor microwave transistor on a gallium nitride substrate. The method mainly solves the problems that an existing device has a parasitic electric leakage channel at a homoepitaxial interface and is low in breakdown voltage. According to the scheme, the method comprises the following steps: firstly, selecting a p-type gallium nitride single-crystal substrate, carrying out surface pretreatment on the p-type gallium nitride single-crystal substrate to obtain a p-type gallium nitride single-crystal substrate containing a p-type AlN electric leakage isolation layer, and then sequentially growing a GaN channel layer, an AlN insertion layer and a barrier layer on the pretreated substrate; and finally, preparing an insulated gate dielectric layer and a gate electrode on the barrier layer, and manufacturing a source electrode and a drain electrode on two sides to complete device manufacturing. Through in-situ compensation of donor impurities based on the p-type AlN electric leakage isolation layer and ion implantation, complete isolation of a parasitic electric leakage channel at a homoepitaxial interface and a 2DEG conductive channel at a homoepitaxial GaN heterojunction interface is realized, transverse electric leakage of the device is effectively inhibited, and the voltage endurance capability and the output power of the device are improved.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which a Mn concentration in the substrate is 5×1017 cm−3 or more; and secondary ion mass spectrometry at a plurality of arbitrary points on the main surface reveals that a variation in the Mn concentration is within ±20% from an average value.

The invention relates to a femtosecond laser processing method for a periodic ferrocobalt oxide single crystal stripe nanostructure, which comprises the following steps of: firstly, preparing a strontium titanate single crystal substrate, and depositing a single crystal epitaxial ferrocobalt oxide film (CFO) on the substrate through pulsed laser; and the included angle between the polarization direction of the femtosecond laser and the lattice orientation of the film is adjusted according to a preset crystallographic direction, so that the surface of the film is induced by the femtosecond laser to form a stripe-shaped periodic surface structure. The single crystal epitaxial cobalt ferrite film prepared by the method has a highly ordered nano structure, and the specific surface area and surface active sites of the material are remarkably improved, so that the application performance of the material in the fields of gas sensing and the like is enhanced.

The present invention discloses a flexible sensor based on an oxide wrinkle structure and a preparation method thereof, comprising: using a solid-phase method to prepare a Sr3Al2O6 target material and a La-BaTiO3 target material respectively; using a pulsed laser deposition technique to prepare a "La-BaTiO3 / Sr3Al2O6 / SrTiO3" heterostructure using the Sr3Al2O6 target material and the BaTiO3 target material on a SrTiO3 single crystal substrate; using a water-soluble method to electrostatically adsorb a polydimethylsiloxane (PDMS) film on the "La-BaTiO3 / Sr3Al2O6 / SrTiO3" heterostructure. The La-BaTiO3 film was then peeled off from the structure to create a "La-BaTiO3 / PDMS" heterostructure. A gold (Au) electrode was grown on the "La-BaTiO3 / PDMS" heterostructure using magnetron sputtering to create an "Au / PDMS / La-BaTiO3" heterostructure. Another PDMS film was attached to the Au electrode surface of the "Au / PDMS / La-BaTiO3" heterostructure by electrostatic adsorption for encapsulation, resulting in a piezoresistive sensor with the "PDMS / Au / La-BaTiO3 / PDMS" heterostructure. This preparation method offers high process controllability, and the resulting flexible piezoresistive sensor exhibits high precision, high sensitivity, and high reliability. The flexible piezoresistive sensor can adapt to changes in various surfaces and shapes and has a wide range of applications.

According to the method, a high-pressure induction heating furnace is adopted, and under the nitrogen atmosphere of 2-5 MPa, a graphite crucible with the inner wall coated with silicon carbide (SiC) and a porous SiC carbon source are utilized to control the nitrogen content in a silicon melt and stabilize components; by introducing 0.05-0.30 wt% of an aluminum or yttrium cosolvent, the nitrogen dissolving efficiency and wettability are improved, in the method, a 10-30 DEG C temperature gradient of a carbon source region and a seed crystal region is established, convection of a nitrogen-containing silicon melt is induced, epitaxial growth of the beta-SiN single crystal is promoted, and the growth of the beta-SiN single crystal is further improved by controlling the immersion depth and the cooling rate of the seed crystal. And finally, the (0001)-oriented high-quality beta-SiN single crystal substrate with the thickness larger than or equal to 500 m and the dislocation density smaller than or equal to 1 * 10 cm is prepared. Compared with the traditional PVT and CVD methods, the method provided by the invention can effectively reduce the growth temperature and thermal stress, inhibit Si evaporation and significantly improve the crystal size and quality, and is suitable for the field of high-frequency and high-power semiconductor device manufacturing.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which an average density of etch pits during etching applied to the main surface using an alkaline etching solution is less than 1×106 cm−2; and in histograms of diameters of the etch pits in multiple different regions on the main surface, and among peaks appearing in the histograms, when a diameter of a first peak which is a smallest diameter is denoted as a, a diameter of a second peak which is a second smallest diameter is denoted as b, frequency of the first peak (the number of etch pits) is denoted as A, frequency of the second peak is denoted as B, the number of the etch pits constituting the first peak is denoted as α, and the number of the etch pits constituting the second peak is denoted as β, at least one of the following conditions (1), (2), and (3) is satisfied: (1) variation in a / b values in the multiple histograms is within ±5% of an average value. (2) variation in A / B values in the multiple histograms is within ±15% of an average value. (3) variation in α / β values in the multiple histograms is within ±30% of an average value.

Provided is an epitaxial wafer having a silicon epitaxial film on a silicon single crystal substrate having a resistivity of 10 [Omega] * cm or more and 5000 [Omega] * cm or less, the epitaxial wafer being characterized in that the concentration of carbon atoms in the silicon epitaxial film is 5 * 1017 atoms / cm < 3 > or more and less than 2 * 1019 atoms / cm < 3 >, and carbon defects are formed in the silicon epitaxial film. As a result, provided are: an epitaxial wafer and an SOI wafer which can be manufactured with a small number of steps without using a high-resistivity substrate, are easy to process, and more reliably reduce harmonics; and a method for manufacturing the epitaxial wafer and the SOI wafer.

There is provided a gallium nitride single crystal substrate, which is a gallium nitride single crystal substrate having a diameter of 50 mm or more, with a low-index crystal plane closest to a main surface being (0001), and in which Ge concentration in the substrate is 3×1018 cm−3 or more; and among peaks appearing in a histogram of diameters of etch pits during etching applied to the main surface with an alkaline etching solution, a first peak having a smallest diameter is a single peak having no shoulder.

The invention discloses a method for preparing a silicon epitaxial wafer from a heavily-doped silicon single crystal substrate and a formed epitaxial wafer, and the method comprises the steps: taking a carbon-oxygen co-doped boron or phosphorus heavily-doped czochralski silicon wafer as a substrate, carrying out epitaxial high-temperature hydrogen pretreatment, heating to an epitaxial temperature, and further growing an epitaxial layer to prepare a high-quality silicon epitaxial wafer. In the high-temperature hydrogen pretreatment step, the temperature is increased to 1200-1250 DEG C at the speed of 40-60 DEG C / s, the temperature is kept for 150-300 s, then the temperature is reduced to 600-800 DEG C at the speed of 20-50 DEG C / s, and the temperature is kept for 30-120 s. The silicon epitaxial wafer prepared by the invention can form a certain width of high-density carbon-promoted carbon-oxygen co-precipitation induced stacking fault in a clean area on the surface layer of the substrate after being subjected to a device hot working process, has the characteristic of absorbing from gaps to inhibit boron or phosphorus from diffusing outwards, and can obtain a device with stable pressure resistance and strong gettering capability.

The invention provides a P-type beta-Ga2O3 single crystal film as well as a preparation method and application thereof, and belongs to the technical field of gallium oxide materials. Vapor phase epitaxial film growth is carried out on the surface of a beta-Ga2O3 single crystal substrate to obtain the P-type beta-Ga2O3 single crystal film, and nitrogen is used as carrier gas and nitrogen oxide is used as an oxidizing agent in the vapor phase epitaxial film growth process. In the growth process of the vapor phase epitaxial thin film, an N element is in a thermodynamic unstable state in a gallium oxide crystal and is easy to volatilize from the gallium oxide crystal, so that after the carrier gas is changed into nitrogen, the concentration of the N element in the environment is increased, the volatilization of the N element in the gallium oxide thin film is inhibited, the N doping efficiency is improved, and the yield of the gallium oxide thin film is improved. According to the method, nitrogen oxide is used as an oxidizing agent, nitrogen is used as carrier gas, and the nitrogen doping concentration of the P-type beta-Ga2O3 single crystal thin film is improved under the combined action.

The embodiment of the invention discloses a ferroelectric domain wall neuronal synaptic device, a regulation and control method thereof and a neural network device. The ferroelectric domain wall nerve synapse device comprises a ferroelectric domain wall unit and an electric field forming unit; each ferroelectric domain wall unit comprises a single crystal substrate layer, a bottom electrode layer and a ferroelectric material layer which are stacked in sequence; and the electric field forming unit is used for forming an equivalent electric field according to the received pulse signal and loading the equivalent electric field on the ferroelectric domain wall unit so as to regulate and control the conductivity value of the ferroelectric domain wall unit. According to the embodiment, the electric field forming unit in the ferroelectric domain wall neural synapse device receives the pulse signal to form the equivalent electric field, and the equivalent electric field is loaded on the ferroelectric domain wall unit to regulate and control the conductivity value of the ferroelectric domain wall unit, so that integration of information storage and neural morphology calculation can be realized; the method has the advantages of being low in environmental influence degree, stable in resistance state, low in energy consumption, high in calculation speed and the like, and has wide application prospects.

The invention discloses a preparation method of a gallium oxide semi-insulating substrate and the gallium oxide semi-insulating substrate, which comprises the following steps: performing proton irradiation treatment on a gallium oxide single-crystal substrate to introduce lattice defects into the gallium oxide single-crystal substrate, and performing annealing treatment on the gallium oxide single-crystal substrate into which the lattice defects are introduced to obtain the gallium oxide semi-insulating substrate. According to the technical scheme, lattice defects are introduced into the gallium oxide single crystal substrate by adopting a proton irradiation process to form a deep energy level trap to effectively capture free carriers, so that the carrier concentration of the material is remarkably reduced, and the resistivity of the material is increased, thereby realizing stable conversion from a conductive state to a semi-insulating state; therefore, the conditions of poor doping uniformity, insufficient thermal stability and local resistivity fluctuation existing in a traditional element doping method are overcome, meanwhile, the defects of lattice mismatch, insufficient thermal conductivity and the like caused by a heterogeneous substrate are avoided, and the electrical property uniformity and the material structure integrity of the gallium oxide substrate are effectively improved. The method has the advantages of non-contact, low cost, easy regulation and control and the like.

The utility model discloses a rotary device and epitaxial reaction furnace for epitaxial reaction, the rotary device includes the rotary base for supporting wafer tray, rotating mechanism and drive mechanism, rotating mechanism is connected with rotary base through a transmission mechanism and drives rotary base rotation, and drive mechanism is used for driving rotating mechanism rotation. Based on the rotary device, can avoid the graphite particle adhesion monocrystal substrate in epitaxial reaction process, reduces the defect quantity of monocrystal substrate, improves epitaxial layer growth quality.

The present invention provides a single-phase multiferroic material, a single-phase multiferroic thin film, and their preparation methods and applications. The chemical formula of the single-phase multiferroic material is Dy 0.5 Ba 0.5 TiO3. A single-phase multiferroic thin film, the components of the thin film include Dy 0.5 Ba 0.5 TiO3, and the preparation method is as follows: preparing a Dy 0.5 Ba 0.5 TiO3 target by a solid-phase reaction method; using the Dy 0.5 Ba 0.5 TiO3 target as the target, using argon as the sputtering gas, and using a radio frequency power supply to perform magnetron sputtering on a single crystal substrate to obtain a single-phase multiferroic thin film. In the single-phase multiferroic material Dy 0.5 Ba 0.5 TiO3 of the present invention, the ferroelectric polarization and magnetism in the material are homologous and are both induced by magnetism, enhancing the magnetoelectric coupling effect in the material.

The invention discloses a silicon-based high-mobility wide-band-gap tin-based oxide film, a preparation method thereof and a transistor, and belongs to the technical field of low-power-consumption electronic devices. The preparation method of the tin-based oxide thin film provided by the invention comprises the following steps: firstly, sequentially preparing a sacrificial layer and a single crystal tin-based oxide thin film on a temporary growth substrate to obtain an oxide heterostructure; then preparing a supporting layer, and adhering the single crystal tin-based oxide thin film by using the supporting layer to realize stripping of the single crystal tin-based oxide thin film from the single crystal substrate; and finally, transferring the single crystal tin-based oxide thin film to the silicon substrate to realize compatible integration of the single crystal tin-based oxide thin film and the silicon substrate. The single crystal tin-based oxide thin film is transferred to the silicon substrate through a substrate-free transfer technology, dependence on a high-cost specific substrate is eliminated, a mature silicon-based process is compatible, and a foundation is laid for large-scale integrated circuit application; and finally, the thin film transistor with low power consumption, high performance and low cost is prepared, the cost advantage is remarkable, and the application prospect is wide.

The invention provides a polarization signal amplification photoelectric detector based on gallium oxide and a preparation method thereof. The polarization signal amplification photoelectric detector based on gallium oxide comprises a gallium oxide single crystal substrate; the gallium oxide photoelectric detector is arranged on the gallium oxide single crystal substrate, and the gallium oxide photoelectric detector is configured to generate different photoelectric responses to the solar-blind ultraviolet light in different polarization directions by using the in-plane anisotropy of a gallium oxide material and output electric signals changing along with the polarization directions; the gallium oxide transistor is arranged on the gallium oxide single crystal substrate, a grid electrode of the gallium oxide transistor is electrically connected with the signal output end of the gallium oxide photoelectric detector so as to receive an electric signal changing along with the polarization direction to serve as input of the grid electrode, the gallium oxide transistor works in a sub-threshold region, and the change of the polarization direction causes the change of grid electrode voltage; and an electric signal with enhanced amplitude is output from the drain electrode of the gallium oxide transistor, so that on-chip amplification of the polarization signal is realized.

Provided are a composite silicon carbide substrate and a preparation method therefor. The composite silicon carbide substrate comprises a single crystal layer, a bonding layer and a support layer which are stacked in sequence; a surface of the single crystal layer is provided with a periodic atomic step structure; the atomic step structure comprises any one of a four-width step structure, a two-width step structure or a single-width step structure. The preparation method comprises: (1) bonding a support layer with an ion-implanted single crystal substrate, and performing a heat treatment and detaching to obtain an intermediate product of the composite silicon carbide substrate; and (2) subjecting a surface of a single crystal layer of the intermediate product of the composite silicon carbide substrate obtained in step (1) to oxidation modification and polish removal alternately, that is, forming a periodic atomic step structure on the surface of the single crystal layer, to obtain the composite silicon carbide substrate. The composite silicon carbide substrate meets the needs of high-voltage power devices for silicon carbide epitaxial layers with a large thickness and high quality, and the preparation method is simple and efficient, and has good controllability.

A Schottky barrier diode, including a first n-type semiconductor layer including a β-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a β-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The β-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.

The application provides a yttrium barium copper oxide photonic crystal and a preparation method thereof. 7‑x The photonic crystal structure is composed of periodic yttrium barium copper oxide (YBa2Cu3O 7‑x ) superconducting material circular crystal columns, the lattice constant is 2630nm, and the radius of the circular crystal column is 500nm. The photonic crystal can change the position and width of the band gap by changing the light incidence angle, so that the middle infrared band gap is realized. The photonic crystal is prepared by adopting a magnetron sputtering method to prepare a yttrium barium copper oxide film on a strontium titanate single crystal substrate, and then adopting a focused ion beam method to process the yttrium barium copper oxide film into a periodic nanostructure composed of yttrium barium copper oxide circular crystal columns, so that the yttrium barium copper oxide photonic crystal is obtained. The preparation method of the yttrium barium copper oxide photonic crystal is simple and easy to control.

The invention belongs to the field of film sensors, and discloses a preparation method of a lanthanum aluminate / strontium titanate nanostructure for hydrogen detection, which comprises the following steps: preparing a strontium titanate single crystal substrate, depositing a single crystal epitaxial lanthanum aluminate film on the strontium titanate single crystal substrate by pulse laser to obtain a single crystal epitaxial lanthanum aluminate / strontium titanate material; then, a stripe-shaped periodic surface nanostructure is formed on the surface of the single crystal epitaxial lanthanum aluminate thin film through femtosecond laser induction, a lanthanum aluminate / strontium titanate nanostructure is obtained, and then precious metal nanoparticles are deposited on the surface of the lanthanum aluminate / strontium titanate nanostructure. According to the preparation method, the highly-ordered single-crystal lanthanum aluminate / strontium titanate heterogeneous film is obtained by accurately controlling pulse laser deposition process parameters, and a nano stripe periodic structure is prepared on the surface of lanthanum aluminate by accurately controlling pulse femtosecond laser processing parameters, so that the specific surface area is effectively increased, gas adsorption sites are increased, and the specific surface area of the lanthanum aluminate / strontium titanate heterogeneous film is increased. And the gas charge transmission capability of the lanthanum aluminate / strontium titanate interface two-dimensional electron gas is improved.

The present invention discloses a highly robust anti-static surge substrate-type ESD / TVS diode structure and method. This ESD / TVS diode structure comprises an emitter junction optimization filling slot disposed beneath the surface metal and contacts, in contact with and electrically connected to the semiconductor single crystal substrate. Below the emitter junction optimization filling slot is an emitter junction optimization diffusion disposed within the semiconductor single crystal substrate and in contact with the emitter junction optimization filling slot. A collector junction optimization filling slot extends from the surface of the semiconductor single crystal substrate, and a collector junction optimization diffusion is disposed within the semiconductor single crystal substrate below the collector junction optimization filling slot. A lateral suppression filling slot extends from the surface of the semiconductor single crystal substrate, and a lateral suppression diffusion is disposed within the semiconductor single crystal substrate below the lateral suppression filling slot. Using this invention, a punch-through TVS / ESD product that meets high-end requirements can be fabricated on a semiconductor substrate without an epitaxial substrate.

The invention aims to provide a method for dividing a single crystal substrate that suppresses the occurrence of chipping. According to one embodiment of the invention, the method relates to a single-crystal substrate with a cleavage plane (7) inclined with respect to a scoring surface and a fracture surface (2), and includes steps to form a scoring line (L2) on the scoring surface (3), to apply an adhesive separating strip (9) to the scoring surface (3), to turn over a single-crystal substrate (1) and place it on a crushing table 11 such that the scoring surface (3) faces the crushing table (11), to bring a crushing plate (13) into contact with the fracture surface (2) along a fracture line (B) which is separated from a reference line (R) by a transverse line (C) at which a vertical plane extending from the scoring line (L2) in a direction orthogonal to the scoring surface (3) and the fracture surface (2) intersects the fracture surface (2).where the cleavage plane (7), extending from the scribe line (L2), crosses the fracture surface (2), is positioned at a distance, and an external force is applied from the fracture plate (13) to the fracture surface (2) to split the single crystal substrate (1) along the cleavage planes (7).

A semiconductor substrate (1) includes: an SiC single crystal substrate (10SB), a first graphene layer (11GR1) disposed on an Si plane of the SiC single crystal substrate 10SB; an SiC epitaxial growth layer (12RE) formed above the SiC single crystal substrate via the first graphene layer; and a second graphene layer (11GR2) disposed on an Si plane of the SiC epitaxial growth layer. There is also included an SiC polycrystalline substrate (16P) provisionally bonded onto the SiC epitaxial growth layer via the second graphene layer. The SiC single crystal substrate is able to be reused by being separated from the SiC epitaxial growth layer. This semiconductor substrate further includes an SiC polycrystalline growth layer (18PC) CVD grown on the C plane of the SiC epitaxial growth layer; and the SiC epitaxial growth layer is transferred to the SiC polycrystalline growth layer.

A SiC epitaxial wafer of the present invention includes a SiC single crystal substrate, and a high concentration layer that is provided on the SiC single crystal substrate and has an average value of an n-type doping concentration of 1×1018 / cm3 or more and 1×1019 / cm3 or less, and in-plane uniformity of the doping concentration of 30% or less.

The invention discloses a preparation method of an extremely-low-activation neutron irradiation micro-nano sample, which comprises the following steps: S1, according to activation characteristics of a selected material, calculating a micro-nano sample volume critical value which can be reduced to a low level without surface radioactivity of the selected material; s2, selecting a low-activation single crystal material as a single crystal substrate; s3, performing pit digging treatment on the single crystal substrate by using a focused ion beam technology to form one or more pits of which the volume is smaller than the volume critical value of the micro-nano sample; and S4, preparing one or more micro-nano samples matched with the pits by using a focused ion beam technology, and welding the micro-nano samples into the pits. The preparation method has the advantages that the activation level is reduced, the efficiency is high, the experiment safety is enhanced, and the application range is wide.

The present invention provides a semiconductor device that uses a high-quality semiconductor film. The present invention provides a high-performance semiconductor device. The semiconductor device comprises first and second transistors, first and second insulation layers, and first and second single crystal substrates. In the first transistor, a channel is formed in a first single crystal semiconductor of the first single crystal substrate. The second transistor is positioned above the first transistor. In the second transistor, a channel is formed in a second single crystal semiconductor that contacts the first single crystal substrate. The second single crystal substrate is positioned above the second transistor. The first insulation layer is positioned between the first transistor and the second transistor. The second insulation layer is positioned between the first insulation layer and the second transistor and has a first joining surface that contacts the first insulation layer. The first single crystal semiconductor contains silicon, and the second single crystal semiconductor contains a metal oxide.

This method for manufacturing a SiC composite substrate includes: a step of providing a single crystal SiC substrate having a graphene film formed on a main surface; a step of epitaxially growing a single crystal SiC layer on the main surface of the single crystal SiC substrate via the graphene film; a step of peeling the single crystal SiC layer from the graphene film; and a step of laminating the single crystal SiC layer by interposing an adhesive layer containing a metal compound on a main surface of a polycrystalline SiC substrate.

Provided is a high-resistance gallium nitride single crystal substrate which is uniformly doped with Mn. The gallium nitride single crystal substrate has a diameter of 50 mm or more, the low-index crystal plane closest to the principal surface is a (0001) plane, the concentration of Mn in the substrate is 5 * 1017 cm-3 or more, and the variation in Mn concentration when a plurality of arbitrary points on the principal surface are subjected to secondary ion mass spectrometry is within an average value of + / -20%.