687 results about "Lithography process" patented technology

The invention provides an optical proximity correction method and system based on mask error model optimization, and a terminal, and the method comprises the steps: building a data sample set containing a plurality of process conditions through obtaining a large amount of mask manufacturing data under a specific photoetching process; and based on the sample set, constructing a physical optical sub-model and a machine learning sub-model to form a mask error model for outputting a final mask key size value. And then, according to a plurality of preset alternative weight coefficient combinations, reconstructing an objective function which introduces a mask error term, calculating corresponding objective function values, and correcting the photoetching pattern by using an OPC algorithm corresponding to each objective function value to obtain performance index data so as to determine an optimal weight coefficient combination. And finally, optimizing the OPC algorithm by using the target function of the optimal combination, thereby realizing the accurate correction of the photoetching pattern, and improving the precision and yield of semiconductor manufacturing. According to the method, the mask error model comprehensively considering physical optics and machine learning is established, and the OPC process is introduced, so that the influence of the mask error can be predicted and compensated more accurately, the critical dimension deviation and the like are reduced, and the device performance and the yield are improved. The method can adapt to different process conditions, and parameters and weight coefficients can be dynamically adjusted. And moreover, rework can be reduced, automatic adjustment is realized through closed-loop feedback control, the production stability and efficiency are improved, and the cost is reduced.

The invention relates to a piezoelectric resonator, which belongs to the technical field of micro electro mechanical systems, and comprises a resonant body on which micropore structures are periodically arranged; the resonant body is fixed on the substrate, and a cavity or an acoustic reflecting layer is arranged between the substrate and the resonant body; wherein the micropore structure and part of the resonance body around the micropore structure form an in-plane coupling unit which is used for exciting the coupling mode of the resonator. Compared with the prior art, the in-plane coupling units arranged in the x-y plane of the resonator can excite transverse modes in the x-axis direction and the y-axis direction at the same time, an in-plane two-dimensional transverse coupling mode is formed, and the transverse coupling mode is the basis for achieving the photoetching tuning characteristic of the resonator. Appropriate sizes and in-plane arrangement of the in-plane coupling units are defined through a photoetching process, and the resonant frequency of the resonator can be adjusted in a wide frequency band range.

An MEMS wafer corrosion thickness monitoring and corrosion process evaluation method comprises the steps that a plurality of monitoring points are designed in a preset area of a silicon wafer pattern surface, the monitoring points are of structures with different shapes and different depths, structures with different heights are formed on photoresist through a multi-depth photoetching process, and the monitoring points are used for monitoring the corrosion thickness of the silicon wafer. The structure is integrally transferred to the surface of a silicon wafer through one-time dry etching, multiple depth monitoring points are formed, an anti-corrosion protection layer is deposited on the pattern face of the wafer, wet etching is carried out on the back face of the wafer, the light-transmitting state of the monitoring points is recognized through chemical corrosive liquid and an optical detection system, and the light-transmitting area proportion is quantified; according to the light transmission sequence and time, the corrosion depth and uniformity of each area of the wafer are calculated, the process result and the wafer quality are evaluated, the wet method corrosion depth can be accurately controlled, the corrosion uniformity in the wafer is greatly improved, and the manufacturing process of the monitoring structure is simplified.

The invention provides a method for determining an optimal focus. The method comprises the following steps of: providing a wafer which is subjected to photoetching treatment under different focus settings; performing optical critical dimension measurement on the photoresist pattern on the wafer to obtain a plurality of side wall angle values respectively corresponding to different focus settings; based on the plurality of side wall angle values and different focus settings, establishing a relationship between the side wall angles and the focuses; and according to the relationship, determining a focus when the side wall angle is the preset target angle as an optimal focus. According to the method, by directly utilizing the side wall angle parameter strongly related to the focusing quality, the measurement interference of a traditional method is avoided, and the optimal focus of the photoetching process can be determined more accurately and reliably, so that the process window is widened, and the process stability and the product yield are improved.

The invention relates to the technical field of semiconductor photoetching, and discloses a super-resolution photoetching and guided self-assembly-based graphic structure preparation method, which comprises the following steps of: S1, forming a guide layer, a reflective metal layer and a photosensitive film layer which are sequentially stacked on a substrate; s2, exposing and developing the photosensitive film layer by adopting super-resolution photoetching equipment, and forming a photoetching pattern on the photosensitive film layer; s3, the reflective metal layer and the guide layer are sequentially etched to the upper surface of the substrate, and the photoetching pattern is transmitted to the guide layer; s4, taking the photoetching pattern as a guide structure, and coating a molecular brush material in a groove of the guide structure to form an affinity polymer layer; s5, the groove of the guide structure is internally coated with a block copolymer, and after annealing, guide self-assembly is conducted to form a block copolymer layer; and S6, selectively removing part of the polymer block region to obtain a graphic structure. According to the method, a super-resolution photoetching process is combined with guided self-assembly of the block copolymer, so that higher process expansion is realized, and a graphic structure with the resolution within 20nm is obtained.

Method for producing an optical test element (19) for determining a fit defect of an optical surface (20). The method comprises the following steps: - Determining a CGH design (24) suitable for measuring the optical surface (20), - Generating a CGH auxiliary structure (25) corresponding to the CGH design (24) on an auxiliary substrate (30) using a direct-write lithography process, - Generating an image of the CGH auxiliary structure (25) on a final substrate (40) using a transfer lithography process, - Generating a CGH structure (50) corresponding to the CGH design (24) based on the generated image. The method offers the advantage that the auxiliary substrate can be produced with high precision using a standardized direct-write lithography system, regardless of the size of the optical test element.

The invention discloses a parameter optimization method for photoresist, which comprises the following steps: collecting process multi-source data, preprocessing to construct a data set, and generating environment and equipment disturbance vectors; photoresist material data are extracted, multiple features are fused in a dimensionality reduction mode, and photoresist dynamic vectors are generated; acquiring process time sequence data, inputting the process time sequence data into the improved CycleNet network, and extracting process dynamic characteristics; constructing a tensor input solving unit, calculating the acid concentration and the developing thickness, and predicting the imaging quality; the photoresist dynamic vector is evolved, and a complete disturbance set is generated in combination with the multiple disturbance vectors; and constructing a robust optimization target, evaluating a parameter imaging effect, and obtaining optimal process parameter output. According to the method, robust optimization and stable control of key parameters of the photoetching process are realized by constructing a parameter optimization process fusing photoresist dynamic evolution, process time sequence disturbance and multi-source disturbance perception.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

The embodiment of the invention provides a method, a system and equipment for establishing an optical proximity correction model and a storage medium, and the method comprises the steps: providing a test layout which is provided with a first test pattern; performing correction operation on the first test pattern by using a first optical proximity correction model to generate mask pattern data of the first test pattern; obtaining a physical contour of a first type semiconductor structure formed on a physical wafer by the first test pattern when exposure operation is executed according to the mask pattern data; the physical contour is the contour of the first type semiconductor structure corresponding to the repeated region; performing photoetching process simulation on the mask pattern data by using the first optical proximity correction model to generate a prediction contour; and correcting the first optical proximity correction model according to the physical contour and the predicted contour to obtain a second optical proximity correction model. By adopting the technical scheme, the correction precision of the OPC model can be improved, and the photoetching quality is improved.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

The invention discloses a photoresist removing method and device and a reworking method of a photoetching process, and the photoresist removing method comprises the steps: providing a substrate, and enabling the surface of the substrate to be provided with photoresist; etching the photoresist by using etching gas with concentration difference in different directions to form an irregular glue layer structure; performing wet stripping treatment on the irregular adhesive layer structure; and carrying out surface hydrophobicity treatment on the substrate after the irregular adhesive layer structure is stripped. According to the invention, the defect that the photoresist on the silicon-based substrate collapses after reworking of the photoetching process can be eliminated.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

The invention relates to the field of integrated circuit manufacturing, in particular to a mask process correction method, device and equipment and a storage medium. Inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; determining a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge section in the simulation electron beam exposure pattern to obtain a corresponding side wall included angle; according to the size of the simulation pattern at the bottom of the mask layer, determining a size-included angle comparison data set corresponding to each edge section to obtain an included angle offset; further determining a target size offset; and adjusting the position of a corresponding edge section in the simulation pattern at the bottom of the mask layer according to the target size offset. The similarity between a wafer pattern obtained by carrying out a photoetching process on the mask layer corrected by the method and a photoetching target pattern is greatly improved.

The invention provides a front-side-bonded heterogeneous integrated chip and a preparation method thereof. A silicon nitride waveguide layer of the heterogeneous integrated chip is arranged on a silicon waveguide layer and is coupled with the silicon waveguide layer; the lithium niobate waveguide layer is arranged on one side, deviating from the silicon waveguide layer, of the silicon nitride waveguide layer and is coupled with the silicon nitride waveguide layer; the lithium niobate waveguide layer comprises a first sub-waveguide layer and a second sub-waveguide layer which are connected with each other, the second sub-waveguide layer is arranged on one side of the silicon nitride waveguide layer, orthographic projections of the second sub-waveguide layer and the silicon nitride waveguide layer on the silicon waveguide layer are mutually overlapped, and the first sub-waveguide layer is arranged on one side, deviating from the silicon nitride waveguide layer, of the second sub-waveguide layer; the silicon nitride waveguide layer is used as an intermediate coupling layer, and the silicon waveguide layer and the lithium niobate waveguide layer are integrated on the same chip, so that the chip has the advantages of a silicon optical chip and lithium niobate; and moreover, the lithium niobate waveguide can be allowed to adopt a contact type photoetching process with a larger line width, so that the etching difficulty and the equipment cost can be reduced.

The invention discloses a photoetching hot spot detection method and device based on dynamic subgraph feature fusion, and relates to the technical field of integrated circuits, and the method comprises the following steps: orthogonally cutting a polygon in a to-be-detected photoetching layout slice sample into rectangles, taking the central point of each rectangle as a node, and constructing to-be-detected graph structure data in combination with embedded features associated with each node; determining the radius of a sub-graph according to the photoacid diffusion length and the local graph density associated with the to-be-measured photoetching layout slice sample; and through the trained dynamic sub-graph aggregation graph kernel convolutional network model, according to the sub-graph radius, constructing a sub-graph of each node by using the to-be-detected graph structure data, extracting features based on each sub-graph to carry out hot spot detection, and outputting a photoetching hot spot detection result. Based on the scheme, the radiuses of the sub-graphs are dynamically divided by adopting photoetching process parameters to reduce empirical static hypothesis errors, visual decomposition and complex structures of the analysis graphs are carried out in a sub-graph feature extraction and fusion mode to enhance the interpretability of hot spot detection, and the reliability of hot spot detection is improved.

The invention provides a deep learning photoetching hot spot detection method and system combined with a physical model, and relates to the technical field of photoetching processes, and the deep learning photoetching hot spot detection method comprises the following steps: obtaining data of a design layout and a mask layout, calculating light intensity gradient and surface stress distribution by using a double-physical field model, and forming a physical sensitive characteristic pattern; inputting the feature map into a physical constraint neural network for reconstruction and mapping; and constructing a state transition matrix based on the compensation state sequence, calculating a transition cost, determining an optimal compensation path, and generating layout compensation data. According to the invention, high-precision hot spot detection and effective layout compensation are realized.

The invention relates to a wafer bearing platform lifting system and a method for lifting a wafer bearing platform, in particular to a system and a method for realizing accurate alignment of a wafer and a photomask in a semiconductor lithography process. The system comprises a wafer bearing table, a photomask bearing table, a plurality of linear actuators, a plurality of range finders and a controller. The wafer bearing table is used for bearing a wafer, and the photomask bearing table is used for bearing a photomask. In addition, the linear actuator is used for adjusting the wafer bearing table, and the distance measuring instrument is used for measuring the height of the surface of the wafer. The controller is configured to measure the height of multiple points on the surface of the wafer, adjust the level of the wafer, calculate the distance between the wafer and the photomask, and lift the wafer bearing table to make the wafer contact with the photomask. The invention provides a semiconductor manufacturing method which improves accuracy, efficiency and user control.

The invention provides a silicon-based adapter plate with TSV holes with different depths and a preparation method thereof, and the method comprises the steps: carrying out the first photoetching technology to form a graphical first mask layer, carrying out the etching under the assistance of the first mask layer to form a first TSV hole, and carrying out the electroplating to form a first TSV copper column; and then carrying out a second photoetching process to form a patterned second mask layer, etching to form a second TSV hole with the depth different from that of the first TSV hole under the assistance of the second mask layer, and electroplating to form a second TSV copper column. The etching and electroplating problems of the TSV holes with different depths are effectively solved through the method of two-time patterning, two-time etching and two-time electroplating; the silicon-based adapter plate is prepared from a silicon wafer and is used for embedding a silicon bridge, so that the problem of thermal stress caused by mismatching of thermal expansion coefficients between the silicon bridge and a substrate for embedding the silicon bridge can be effectively solved.

The invention belongs to the technical field of photoetching process and equipment, and particularly relates to a glass substrate positioning method for a movable exposure mechanism of edge exposure equipment, which comprises the following steps of: accurately identifying a real edge point on the upper surface of a glass substrate by calculating an asymmetric index of an image gray gradient and a local standard deviation; establishing an elastic physical model to calculate the vertical sinkage of the edge points due to suspension, and correcting the observation coordinates in combination with a perspective geometry principle to restore the real physical position of the observation coordinates in an ideal plane; and carrying out weighted fitting on the real coordinate point set, and accurately calculating the rotation and translation deviations of the glass substrate, thereby realizing high-precision and high-robustness alignment control.

The invention provides an etching method, and the method comprises the steps: providing a semiconductor structure which is provided with an etching stop layer, an interlayer dielectric layer and a graphical hard mask layer from bottom to top, employing a photoetching technology, combining with the graphical hard mask layer to etch the interlayer dielectric layer, and forming a through hole which penetrates through the interlayer dielectric layer and exposes the etching stop layer, and subsequently, through a two-step ashing process, impurities in the hard mask layer, the structure surface and the etching cavity are removed under the condition that bias power is not applied, and then the bias power is applied to remove residual impurities in the through hole, so that the bombardment time and the damage to the etching stop layer are remarkably reduced, the damage to a lower layer contact material in the subsequent step is avoided, and the production efficiency is improved. According to the method, the process development window is expanded, the stability and reliability of the etching process are improved, and the requirement for manufacturing a high-performance semiconductor device is met.

Systems and methods for forming an antimony containing film on a substrate. Related structures and films are also disclosed. The antimony films are be formed by a plasma enhanced atomic layer deposition process. The antimony films can be utilized as underlayers in EUV lithography processes.

The application discloses a kind of hollow mask electrode deposition sample holder and method, including connecting tray, movable sample table and mask plate clamp;The bottom of slide rail connector is slidably connected with X linear slide rail in X direction, and the top of slide rail connector is slidably connected with the bottom of sample table in Y direction;Slide rail connector is provided with X through screw hole, and the threaded one end of X adjusting screw rod is installed in the X through screw hole of slide rail connector, and the other end is arranged in X clamping device;Sample table is provided with Y through screw hole, and the threaded one end of Y adjusting screw rod is installed in the Y through screw hole of sample table, and the other end is arranged in Y clamping device;Mask plate clamp fixing stud is higher than sample table, and mask plate clamp is connected with the top of mask plate clamp fixing stud.Carry out the precision requirement when using photolithography process to transfer single-crystal island two-dimensional material and grow single-crystal island two-dimensional material deposition electrode.

The present application relates to the technical field of photolithography process, and more particularly to a kind of periodical scanning half-period optical waveguide grating preparation method, adopts multi-dimensional defect feature extraction and dynamic compensation algorithm, combined with the space-time synchronous modulation technology of light intensity distribution, significantly improves the defect masking efficiency;Through the multi-parameter collaborative optimization strategy under the closed-loop control architecture, the self-adaptive evolution mechanism of process parameters is formed, and the performance stability of grating structure under complex working conditions is guaranteed.The technical scheme innovates the whole process from light field modeling, motion control to defect repair, solves the common technical problems of grating period distortion and defect residue in the existing process, and provides a mass production solution for high-reliability grating devices for dense wavelength division multiplexing systems.

The invention belongs to the technical field of semiconductor manufacturing, and discloses a method for manufacturing double shallow trench isolation and a semiconductor structure. The method comprises the following steps: sequentially depositing a substrate oxide layer, a substrate silicon nitride layer, a sacrificial layer, a bottom anti-reflection coating and photoresist on a selected semiconductor substrate, and forming a patterned sacrificial layer through a photoetching process; sequentially depositing a grinding barrier layer with a preset thickness and a first dielectric layer on the patterned sacrificial layer, processing the first dielectric layer through a chemical mechanical grinding process, removing the grinding barrier layer through an etching process, and sequentially forming a channel of a logic region and a channel of a pixel region; and depositing a second dielectric layer and carrying out chemical mechanical grinding to finally obtain the double-shallow-trench isolation structure. According to the technical scheme, the technical problems that in the prior art, silicon nitride residues are generated, and the heights of silicon oxide in the logic area and the pixel area are different are solved.

The invention discloses a preparation method of a luminescent material for an epoxy negative photoresist, and belongs to the technical field of photoresists. The preparation method comprises the following steps: mixing Yb / Er / Tm doped rare earth chloride with oleic acid, 1-octadecene and oleylamine, dehydrating to form a homogeneous complex, injecting NaOH and NH4F solutions, and synthesizing an up-conversion nano core dispersion liquid at high temperature; heating the gold nanoparticles, adding HAuCl4, sodium citrate and PEI, and performing in-situ reduction to form a gold nanoparticle modification layer; successively adding GPTMS, APTES, PTMS, deionized water and ammonia water, and carrying out a hydrothermal reaction to prepare a functionalized siloxane shell layer; adding dopamine hydrochloride, and performing oxidative polymerization in a Tris buffer solution to form a polydopamine layer; adding thiolated polyethylene glycol to passivate, and centrifugally drying to obtain a nano luminescent material; and adding bisphenol A epoxy resin and other photoresist systems, and carrying out high-speed shearing and ultrasonic dispersion to obtain the uniform luminous composition. According to the method, plasmon enhancement and surface collaborative optimization are realized, the luminous intensity, heat and moisture resistance, resolution and adhesive force are improved, and the method is suitable for a high-performance photoetching process.

The application provides a phase shift mask and a manufacturing method thereof. In the application, a second key pattern size corresponding to a second photoetching process is obtained, and a second photoetching machine is obtained according to the second key pattern size. The resolution identification ability of the obtained second photoetching machine is matched with the second key pattern size, so that the problem that the resolution ability of the photoetching machine used in the second photoetching process is not enough and the formed phase shift mask is defective is avoided, and the quality of the phase shift mask is improved.

A three-dimensional source contact structure and fabrication process method thereof are provided. A lithography process and shallow trench process are sequentially performed to form a metal contact window in a power device. A source heavily doped area is divided by the metal contact window into a first and second heavily doped region. A lateral etching process is applied to an inter-layer dielectric to form a first and a second dielectric layer, each of which is in a trapezoid shape. Meanwhile, a first and a second metal-source surface contact regions are exposed. A longitudinal surface exposed by the shallow trench process is beneficial to increase vertical contact when depositing a source contact metal, thereby a step-like three-dimensional source contact structure can be formed. The present invention achieves in reducing cell pitch effectively and can be widely applied to various power devices having MOSFET structure thereof.

To form a dual damascene structure in a photoresist.SOLUTION: Embodiments of the present disclosure include apparatuses and methods for fabricating dual damascene structures. A first portion in the first region of the photoresist is exposed to a first dose of electromagnetic radiation from a radiation source. The first portion has a first depth and a first surface area. A second portion of the photoresist in the first region is exposed to a second dose of electromagnetic radiation from the radiation source. The second portions have a second depth and a second surface area, and each of the first surface areas of the first portions is disposed within one of the second surface areas of the second portions. A third portion in the second region of the photoresist is exposed to a first dose of electromagnetic radiation from a radiation source. The third portion has a first depth and a first surface area.SELECTED DRAWING: Figure 5

A method for manufacturing an organic light emitting display device can form an anode electrode on each of a plurality of sub-pixels, form a plurality of banks between the plurality of sub-pixels, and form a plurality of protrusions on the plurality of banks. Further, a method for manufacturing an organic light emitting display device can form a first connection structure on a first side portion of a first protrusion adjacent to a red sub-pixel, and form a first organic light emitting element on the red sub-pixel using a first photolithography process. Further, a method for manufacturing an organic light emitting display device can form a second connection structure on a second side portion of the first protrusion adjacent to a green sub-pixel and a first side portion of a second protrusion, and form a second organic light emitting element on the green sub-pixel using a second photolithography process. In addition, a method for manufacturing an organic light emitting display device can form a third connection structure on a second side portion of the second protrusion adjacent to a blue sub-pixel, and form a third organic light emitting element on the blue sub-pixel using a third photolithography process.

A through silicon via interconnection structure and a method of forming same, and a quantum computing device are provided. The method includes: providing a silicon wafer, having a first surface and a second surface opposite to each other; forming, in the silicon wafer, a through silicon via penetrating through the silicon wafer in a direction from the first surface to the second surface of the silicon wafer; forming a groove communicating with the through silicon via in a target surface of the first surface and the second surface of the silicon wafer using a photolithography process; and forming a superconducting thin film in the groove and the through silicon via to obtain the through silicon via interconnection structure.