120 results about "Lithography process" patented technology

The present application relates to the technical field of photolithography process, and more particularly to a kind of periodical scanning half-period optical waveguide grating preparation method, adopts multi-dimensional defect feature extraction and dynamic compensation algorithm, combined with the space-time synchronous modulation technology of light intensity distribution, significantly improves the defect masking efficiency;Through the multi-parameter collaborative optimization strategy under the closed-loop control architecture, the self-adaptive evolution mechanism of process parameters is formed, and the performance stability of grating structure under complex working conditions is guaranteed.The technical scheme innovates the whole process from light field modeling, motion control to defect repair, solves the common technical problems of grating period distortion and defect residue in the existing process, and provides a mass production solution for high-reliability grating devices for dense wavelength division multiplexing systems.

The application provides a phase shift mask and a manufacturing method thereof. In the application, a second key pattern size corresponding to a second photoetching process is obtained, and a second photoetching machine is obtained according to the second key pattern size. The resolution identification ability of the obtained second photoetching machine is matched with the second key pattern size, so that the problem that the resolution ability of the photoetching machine used in the second photoetching process is not enough and the formed phase shift mask is defective is avoided, and the quality of the phase shift mask is improved.

A method for manufacturing an organic light emitting display device can form an anode electrode on each of a plurality of sub-pixels, form a plurality of banks between the plurality of sub-pixels, and form a plurality of protrusions on the plurality of banks. Further, a method for manufacturing an organic light emitting display device can form a first connection structure on a first side portion of a first protrusion adjacent to a red sub-pixel, and form a first organic light emitting element on the red sub-pixel using a first photolithography process. Further, a method for manufacturing an organic light emitting display device can form a second connection structure on a second side portion of the first protrusion adjacent to a green sub-pixel and a first side portion of a second protrusion, and form a second organic light emitting element on the green sub-pixel using a second photolithography process. In addition, a method for manufacturing an organic light emitting display device can form a third connection structure on a second side portion of the second protrusion adjacent to a blue sub-pixel, and form a third organic light emitting element on the blue sub-pixel using a third photolithography process.

According to embodiments of this disclosure, a method, apparatus, and medium for pattern processing are provided. In the method, parameter information related to a lithography machine and a wafer in a lithography process is acquired. The lithography machine is used to form a wafer pattern on the wafer based on a target pattern. Based on the parameter information, a target state representation corresponding to the target pattern is determined from a plurality of candidate state representations indicating the electron beam scattering state. Based on the target state representation, a correction result for the target pattern is determined. In this manner, the state representation of the electron beam scattering state corresponding to the target pattern can be determined based on the parameter information of the lithography machine used and the parameter information of the wafer used for lithography, thereby simulating the lithography process more accurately. This ensures that the state representation used for lithography process simulation can more accurately describe the scattering state of the electron beam used by the lithography machine, improving the reliability of the simulation process and thus more accurately determining the correction result for the target pattern.

The invention provides a semiconductor inclined structure and a forming method thereof, which are used for forming a helical tooth structure with a preset inclination angle, and comprises the following steps: forming a grating glue layer on a substrate; patterning the grating adhesive layer by adopting a Talbot photoetching process to form a grating layer, in the exposure process of patterning the grating adhesive layer by adopting the Talbot photoetching process, the scanning distance of the Talbot photoetching process is obtained based on a preset inclination angle, and the incident angle of incident light is an acute angle, so that the grating layer comprises a plurality of mutually separated helical tooth mask structures or a plurality of inclined grooves; the included angle between the tooth side wall of the helical tooth mask structure and the surface of the substrate is an acute angle, and the included angle between the groove side wall of the inclined groove and the surface of the substrate is an acute angle; based on the grating layer, a plurality of mutually separated helical tooth structures are formed on the substrate, and the included angle between the side wall surface of each helical tooth structure and the surface of the substrate is an acute angle. Therefore, manufacturing of the helical tooth structure is met, and the helical tooth structure which meets the expectation and is good in stability is formed.

Photosensitive polymers and their use in photoresists for photolithographic processes are disclosed. The polymers are copolymers, with at least one monomer that includes pendant polycyclic aromatic groups and a second monomer that includes an acidic leaving group (ALG). The polymers have high resistance to etching and high development contrast.

This invention discloses a photolithographically patternable lithium-ion electrolyte, its preparation method, and its applications. The electrolyte is a photolithographically curable lithium-ion electrolyte composition, comprising, by mass percentage, LiTFSI, polyethylene glycol methyl ether methacrylate, bisphenol A ethyl oxide dimethacrylate, fluoroethylene carbonate, succinic acid, 2-hydroxy-2-methyl-1-phenyl-1-propanone (HMPP), 3-(isobutyryloxy)propyltrimethoxysilane, and 2-methyl-2-acrylate-2-hydroxyethyl. This invention also discloses a stepwise preparation method for this composition and its applications in micro-energy storage and ion-electronic devices such as micro solid-state batteries, ion-controlled transistors, and neuromorphic devices. This electrolyte can be patterned at the micro-nano scale using standard photolithography processes, exhibiting excellent lithium-ion conductivity, electrochemical stability, mechanical flexibility, and optical transparency. It also shows good interface compatibility with gold electrodes / silicon wafers, requiring no additional etching or transfer processes. This solves the technical problems of existing solid-state electrolytes being difficult to fabricate at the micro-nano scale and incompatible with microelectronic processes, and has broad application prospects in the fields of micro-nano fabrication and micro-devices.

A non-transitory computer-readable medium stores a set of instructions that is executable by at least one processor of an apparatus to cause the apparatus to perform operations for optimizing an illumination source and mask used in a lithography process. The operations include obtaining a pupil profile. The operations also include simulating the lithography process using the pupil profile to generate predictions resulting from the lithography process. The operations also include calculating a cost function based on the predictions. The cost function includes a linear fading effect term that is indicative of a linear fading effect on the predictions. The operations also include adjusting the pupil profile based on the linear fading effect term.

The application provides a uniform glue system and relates to the technical field of photoetching processes. The uniform glue system comprises a light source, a projection fixture and a base. The light source is used for projecting light. The projection fixture is located below the light source. The base is located directly below the projection fixture and is used for fixing and rotating the substrate with the central straight line as the axis. The projection of the light source after the projection fixture is projected on the upper surface of the base, and the shape and size of the projection profile correspond to the substrate respectively, and are used for positioning the substrate. The central straight line passes through the center of the base and is perpendicular to the upper surface of the base. The technical scheme can realize non-contact and rapid centering operation of the substrate, and can solve the technical problem that the substrate needs to use a clamp when being centered and is easy to scratch.

This application provides a method for measuring the cross-sectional shape of photoresist. The method includes: Step S1: forming a photoresist layer on a substrate and performing a photolithography process; Step S2: measuring the patterned photoresist layer, determining whether the photolithography process was successful based on the measurement results; if not, removing the patterned photoresist layer and returning to Step S1; if yes, proceeding to Step S3: selecting a measurement area on the patterned photoresist layer, the measurement area having a repeating pattern to serve as a grating; Step S4: measuring the diffraction intensity of zero-order and first-order light at multiple wavelengths λ using a diffraction-based overlay error measurement method; Step S5: calculating the equivalent slit width a of the grating; Step S6: obtaining the cross-sectional shape of the patterned photoresist layer. This application utilizes the principle of grating diffraction, the diffraction-based overlay measurement technology, and mathematical calculations of diffraction intensity to obtain the cross-sectional shape information of the photoresist, thus eliminating the need for slicing and saving time and manpower resources.

This invention belongs to the field of supramolecular chemistry and materials technology, and discloses a class of organometallic cages based on polythiol ligands, their preparation methods, and applications; the general chemical formula of the organometallic cages based on polythiol ligands is: [(R n M) x L y (IL) z In this invention, M is a metal center; R is an organic group attached to the metal center M; n is the number of R groups attached to each metal center M; L is an aromatic polythiol ligand; IL is an ionic liquid; x, y, and z are all integers ≥1. This invention uses an ionic liquid as a reaction medium and combines it with a competitive coordination control strategy of organic amines to achieve controllable self-assembly of organometallic cages. These organometallic cages have unique melting and glass transition characteristics, can be used to prepare high-quality thin films through hot pressing film deposition technology, and can also be used as photoresist film deposition materials in various photolithography processes. They have broad application prospects in flexible electronics, packaging materials, micro-nano fabrication, and other fields.

The application discloses a cavity-column combined shape memory polymer stamp and a microchip proximity transfer method thereof. The stamp takes shape memory epoxy resin as a matrix, and a cavity-column combined structure is directly formed through laser microprocessing. The stamp realizes an adhesion switching ratio of up to 1200 by utilizing the change of the elastic modulus of the cavity-column combined shape memory polymer stamp before and after the glass transition temperature, and realizes the low-cost microchip high-precision proximity transfer of high-adhesion pickup and low-adhesion release by combining negative pressure auxiliary adsorption and micro-column directional pushing. The stamp has simple preparation process, does not need complex photoetching process, and can be flexibly regulated and controlled according to the performance requirements of the stamp. The stamp can be adapted to silicon, polyimide, copper, glass, acrylic and other material chips with roughness of 1nm-500nm. The maximum strain of the stamp is only 0.27 during the transfer process, the interface temperature is controllable, the residual adhesion strength is small, and the problems of the existing transfer technology, such as complex preparation, narrow application range and low transfer reliability, are solved.

The application relates to an etching method of a contact hole and a manufacturing method of a DRAM, and belongs to the technical field of semiconductors. The application solves the problems that the existing HARC etching formula only has a time etching step and does not have an EPD etching step, and the wavelength signal emitted during etching of the contact hole is too small to cause the EPD etching to be ineffective. The etching method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is formed with a conductive component; sequentially forming, from bottom to top, an etching stop layer, a layer to be etched, a first mask layer and a second mask layer above the semiconductor substrate; performing a photoetching process on the second mask layer to form a second mask layer pattern; transferring the second mask layer pattern to the first mask layer to form a first mask layer pattern; and taking the first mask layer pattern as a mask, etching the layer to be etched and the etching stop layer to form a contact hole and expose the conductive component, wherein endpoint detection EPD is adopted in etching of the layer to be etched. The HARC etching menu is realized by improving the EPD etching, and technical prejudice is overcome.

This invention discloses a sub-resolution auxiliary feature generation method based on a large inference model. It first generates a seed set from the input target layout, then expands it to obtain a candidate SRAF set, ultimately outputting high-quality SRAF results. By explicitly generating a chain to learn the intrinsic logic of the SRAF, it improves the ability to comply with constraints and the robustness of generation. The output full-process trajectory can trace any final SRAF back to its corresponding seed and candidate, facilitating the location of violations and parameter tuning. Furthermore, seed de-clustering simplifies and reduces sequence length and inference overhead. Combined with reinforcement learning imaging rewards, it further reduces EPE and PVB under compliance conditions. This invention can be used to enhance mask resolution for different layout layers, such as metal layers and via layers, improving imaging quality and expanding the lithography process window.

This invention relates to a microfluidic chip driven by acoustically excited droplet-shaped microbubbles and its fabrication process. A droplet-shaped microbubble array is obtained through microfluidic chip structure design. Under acoustic excitation, the microbubbles oscillate, generating asymmetric acoustic-flow vortices, which in turn directionally drive the microfluidic fluid within the microchannels. The flow rate can be linearly controlled by adjusting the driving voltage, offering advantages such as non-contact, pollution-free, and highly efficient directional driving. The fabrication process is based on MEMS technology, employing nitrogen plasma bonding and soft lithography, resulting in low cost and suitability for mass production. This invention solves the problem of the lack of directionality in traditional symmetrical acoustic-flow vortices and can be widely applied in fields such as biomedicine, drug delivery, and chemical analysis.

A system comprising a memory and at least one processing device operatively coupled to the memory to perform operations comprising initiating a digital lithography process to pattern a substrate using a digital lithography system, controlling an area ratio in a first direction with respect to a first pair of adjacent exposure cells of the digital lithography system, and controlling a dose ratio in a second direction perpendicular to the first direction with respect to a second pair of adjacent exposure cells of the digital lithography system.

This invention provides a metal mask for silicon-based liquid crystal light valve chips, relating to the field of semiconductor optoelectronic device manufacturing technology. It includes a metal substrate and a pixel aperture array, alignment mark area, stress buffer, and reinforced border disposed on the metal substrate, adaptable to mass production evaporation and photolithography processes for LCoS light valve chips. The metal substrate consists of four layers stacked sequentially from bottom to top: a substrate layer, a molybdenum transition layer, a Mo-Ta-N functional pattern layer, and an Al2O3-SiO2 composite passivation layer. The molybdenum transition layer is deposited on the substrate surface using magnetron sputtering, with a surface roughness Ra < 0.15 nm. The Mo-Ta-N functional pattern layer is deposited on the surface of the molybdenum transition layer using reactive magnetron sputtering. The near-vertical, low-roughness aperture sidewalls of this invention result in shadow-free evaporation, uniform electrodes, and clear edges, improving the light utilization and contrast of the LCoS chip. It also increases the utilization rate of the evaporation material and reduces material loss during mass production.

This utility model discloses a photolithography principle demonstration device, comprising: an outer frame including a frame and multiple baffles; a lighting system including an ultraviolet lamp group and a lens group, the lens group being disposed below the ultraviolet lamp group; an imaging system including an optical lens and a photomask, the photomask being disposed between the optical lens and the lens group; a focusing system including a power module, a moving module, and a support platform, the support platform being connected to the moving module and located below the optical lens, the power module being connected to the moving module and capable of driving it to move up and down, thereby causing the support platform to move along the optical axis of the optical lens; a power supply module connected to the lighting system and the power module; and a control module connected to the lighting system, the power module, and the power supply module. This utility model is applicable to teaching demonstrations of photolithography processes.

A bridge leg photolithography process includes the following steps: S1, providing a product wafer of the bridge leg before photolithography, the product wafer having a SIN film layer grown on its surface; S2, using O2 plasma to perform plasma surface etching on the surface of the SIN film layer for SIN film layer surface pretreatment; S3, coating a resist onto the pretreated SIN film layer surface to obtain a coated wafer; S4, exposing the coated wafer to obtain an exposed wafer; S5, developing the exposed wafer to obtain a developed film; S6, observing the morphology of the bridge leg lines in the developed film. Through the SIN film layer surface pretreatment in step S2, the angle between the sidewall and the bottom surface of the bridge leg in the developed film can be close to perpendicular, thereby obtaining an excellent bridge leg morphology, which is more conducive to ensuring the subsequent etching of the SIN film layer below the bottom surface of the bridge leg.

This invention discloses a physical world model-driven multi-stage computational lithography evolution reasoning method, which can unfold the lithography state in the potential state space of each stage and, combined with process intervention strategies, achieve high-precision modeling and optimization of the lithography pattern evolution process. The method includes the following steps: Step 1, constructing a complete dataset by collecting lithography data under different layout and process parameter combinations; Step 2, mapping the physical state of each stage of the lithography process to the potential space, and modeling the potential state of each stage using a spatial embedding method; Step 3, establishing a process intervention strategy model in the potential space, and planning process adjustment schemes for different stages; Step 4, establishing a state transition model to simulate the continuous evolution of the potential state between stages, predicting the potential state of the next stage through the current stage potential state and intervention strategy, and achieving continuous deduction of the lithography state by iteratively updating the intervention scheme.

The present disclosure discloses a method for manufacturing a semi-floating gate transistor. Self-aligned etching is performed by using an SIN protection layer of a control gate structure to form a vertical contact window, instead of the photolithography and etching of conventional lateral contact window, thus omitting one contact window photolithography process, avoiding the formation of an asymmetric semi-floating gate device due to the deterioration of the photolithography pattern overlay of the lateral contact window, and greatly improving the uniformity and the process window of the semi-floating gate transistor. In addition, since the physical distance between the vertical contact window and the gate of the tunnel field-effect transistor of the semi-floating gate transistor is significantly shortened, the tunneling efficiency is high, thus improving the charging speed of the semi-floating gate polysilicon.

This invention relates to a patterning method for two-dimensional materials based on micro-gap anodic oxidation, comprising: (1) preparing a mask wafer with a surface conductive protective layer and a micron-depth pattern; (2) aligning the prepared mask wafer with the wafer to be processed using a tooling chuck; and (3) performing localized etching. This invention achieves wafer-level patterning of two-dimensional materials through surface protection and localized etching. This method avoids contamination and damage associated with traditional photolithography processes and improves production efficiency, providing key technical support for the large-scale application of two-dimensional materials in the field of electronic devices.

The application provides a preparation method of a semiconductor device, wherein in the preparation method, after a patterned first photoresist layer used for ion implantation on a gate structure is removed, an acid washing process and an alkali washing process are used to clean a semiconductor structure to remove a natural oxide layer on a surface of the semiconductor structure, wherein in the acid washing process, a front surface of the semiconductor structure is cleaned by using a hydrofluoric acid solution and a back surface of the semiconductor structure is cleaned by using deionized water, by cleaning the back surface of the semiconductor structure by using the deionized water, the back medium layer of the back surface of the substrate is prevented from contacting the hydrofluoric acid solution, so that the condition that the wafer is formed with more exposure bad points in the following photoetch process is avoided, the overlay accuracy of subsequent metal zero layer via etching is improved, the yield and reliability of the device are improved, and the condition that the back medium layer of the back surface of the substrate is peeled off and then falls down to pollute and / or damage the wafer front surface of the lower layer is avoided.

The invention relates to a method carried out by at least one device, the method comprising: - Obtaining measurement data that yields the value of a Zernike coefficient Z i Specify the path length y along a scan direction of a photolithography process for different distances; - Defining an approximation function a(y) that reproduces the obtained measurement data. The task of specifying a method with which a Zernike coefficient function can be approximated with increased accuracy is solved by making the approximation function a(y) at least piecewise a spline interpolation s(y) of the measurement data.

A method for optimizing a source profile and wavefront profile to simulate a lithography process is disclosed. More particularly, a method for minimizing a phase offset between diffraction orders in a source profile to generate an optimized source profile and an optimized wavefront profile, using a cost function with a phase cost term is disclosed. The disclosed method may further include a diffraction overlap penalty term in the cost function.

Title: Improved Precision Grayscale Photolithography Process The invention relates to a grayscale lithography process comprising supplying a substrate (10) coated with a first layer of photosensitive resin (20), exposing this layer to a first exposure (R1) through a first mask (100), and developing the image. The first mask is configured to form in the resin a set of first structures (25), each having a height within a first range of heights (Δ1). The process includes forming a second layer of photosensitive resin (30), exposing this layer to a second exposure (R2) through a second mask (200), and developing the image.The masks are configured to allow the formation of a set of second structures (35), each having a height within a second range of heights (Δ2) disjoint from the first range of heights (Δ1). Figure for the abbreviation: Fig.3E.

In the current technology, as the wafer size is reduced, how to more accurately evaluate the variation of the critical dimension and accordingly reduce the deviation of the critical dimension is an important issue in the field. Therefore, the present disclosure provides a measurement method and a photolithography process control system. The photolithography process system is used to perform the following steps. Calculate the deviation value between the peripheral critical dimension and the central critical dimension of each exposure area of a portion. Determine whether the deviation value of each exposure area of the portion is within a deviation interval. If the deviation value of each exposure area is within the deviation interval, evaluate the variation amount of the deviation in the main deviation direction of one of the exposure areas, and adjust the parameters of the mask according to the variation amount of the deviation in the main deviation direction of the exposure area, so as to reduce the deviation of the critical dimension.

Embodiments of the present application disclose a display panel, a manufacturing method thereof and a display device. The display panel comprises: an array substrate, the array substrate comprising at least two dams arranged in a non-display area; an insulating layer arranged on the array substrate; and a plurality of touch wires arranged on a side of the insulating layer away from the array substrate. A plurality of grooves are arranged on the insulating layer between the two adjacent dams, and the touch wires in the region between the two adjacent dams are arranged in the corresponding grooves. In this way, in the touch wire patterning process, the photoresist between the two adjacent touch wires in the region between the two adjacent dams can flow into the grooves, so that the thickness of the photoresist between the two adjacent touch wires is small, that is, the effect of effectively reducing the thickness of the photoresist between the two adjacent touch wires is achieved, thereby reducing the energy required for exposure in the touch wire patterning process, shortening the time of the photo-lithography process, and effectively improving the manufacturing capacity of the touch display panel.

This invention proposes a feed network and its design method for a multi-band common-aperture satellite communication antenna, relating to the field of satellite communication technology. This invention employs a three-dimensional heterogeneous layout, placing the low-frequency and high-frequency feed networks on the bottom and top layers of a multilayer dielectric substrate, with a shared ground layer in between. This effectively solves the problem of large space occupation in traditional discrete layouts. For the low-frequency network, characteristic mode theory guides the microstrip feeder design, and a stepped impedance transformer is loaded at the terminal, enabling good impedance matching for low-frequency signals across a wide bandwidth. For the high-frequency network, substrate-integrated waveguide technology is used to construct the signal transmission trunk and coupler gaps are set. Finally, a defective ground structure and a frequency-selective surface are simultaneously integrated on the shared ground layer through a single photolithography process. This allows the design to simultaneously achieve the dual functions of suppressing low-frequency leakage and transmitting high-frequency signals on the same physical layer.