1409 results about "Lithography process" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The invention provides a superlattice infrared detector chip manufacturing method, and belongs to the technical field of infrared detector manufacturing. The problem that the product performance or the product yield is low due to the fact that the precision fluctuation of the photoetching technology when the hard mask is removed is not considered in the current hard mask removing scheme is solved; comprising the following steps: forming a hard mask: growing the hard mask with a certain thickness on the surface of a wafer made of a superlattice material; photoetching an upper electrode table top; etching a hard mask: taking the photoresist as a mask, and etching the hard mask by adopting an ICP (Inductively Coupled Plasma) technology to obtain an upper electrode mesa mask pattern; degumming and cleaning an upper electrode table board; photoetching a lower electrode table board: adopting photoresist as a mask of a lower electrode table board area, and manufacturing the lower electrode table board area through a photoetching technology; carrying out ICP etching on the table board; performing wet etching on the table board; degumming and cleaning a lower electrode table board; forming a passivation layer film; opening holes in the passivation layer; manufacturing a gold electrode; the method is applied to preparation of the superlattice infrared detector chip.

The invention provides an optical proximity correction method and system based on mask error model optimization, and a terminal, and the method comprises the steps: building a data sample set containing a plurality of process conditions through obtaining a large amount of mask manufacturing data under a specific photoetching process; and based on the sample set, constructing a physical optical sub-model and a machine learning sub-model to form a mask error model for outputting a final mask key size value. And then, according to a plurality of preset alternative weight coefficient combinations, reconstructing an objective function which introduces a mask error term, calculating corresponding objective function values, and correcting the photoetching pattern by using an OPC algorithm corresponding to each objective function value to obtain performance index data so as to determine an optimal weight coefficient combination. And finally, optimizing the OPC algorithm by using the target function of the optimal combination, thereby realizing the accurate correction of the photoetching pattern, and improving the precision and yield of semiconductor manufacturing. According to the method, the mask error model comprehensively considering physical optics and machine learning is established, and the OPC process is introduced, so that the influence of the mask error can be predicted and compensated more accurately, the critical dimension deviation and the like are reduced, and the device performance and the yield are improved. The method can adapt to different process conditions, and parameters and weight coefficients can be dynamically adjusted. And moreover, rework can be reduced, automatic adjustment is realized through closed-loop feedback control, the production stability and efficiency are improved, and the cost is reduced.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: removing the second pseudo gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and at least removing the gate isolation layer in the second semiconductor unit through a photoetching process; sequentially removing the first pseudo gate structure and the photoresist to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit and the first active structure and the second active structure in the second semiconductor unit; and forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

The resist composition exhibits a high contrast, improved maximum resolution, and satisfactory sensitivity and line width roughness (LWR) when processed by lithography using high-energy radiation, especially electron beam (EB) and EUV, and a pattern forming process using the resist composition. The resist composition comprising (A) a base polymer containing a polymer comprising repeat units having an acid labile group and repeat units having a carboxy group, (B) an organic solvent, and (C) a hypervalent iodine compound having formula (1):

The invention discloses a DLD chip and method based on high-flow-speed composite flow channel multi-target sorting. The chip comprises a sample inlet, a sheath fluid inlet, a rectification module and a two-stage deterministic lateral displacement DLD sorting module, the rectification module adopts a circular microcolumn array to optimize fluid distribution, and the first-stage module realizes primary sorting through a microfluid channel and is connected with the second-stage module; and the second-stage module is communicated with three sample outlets after being accurately sorted through a microfluid channel II. The chip is made of a PDMS material through a soft photoetching process, and the two stages of sorting modules are designed to be of a rectangular structure connected end to end and are respectively composed of elliptical micro-columns with opposite deflection angles. Under the high-flow-rate working condition, stable separation of cells can be kept, blockage is not prone to occurring, the good sorting effect on various cells of different sizes is achieved, the flow channel layout is compact, the chip manufacturing process is simplified, and the chip is suitable for the sorting scene with the high-flux requirement.

The invention relates to the technical field of semiconductors, in particular to a columnar array enhanced photoelectric detector and a preparation method thereof, and the method comprises the following steps: depositing a continuous GaN layer on a substrate through an epitaxial growth method; forming a columnar array structure pattern and an electrode region on the GaN layer through a photoetching process, and removing a part of the GaN layer through an etching process to form an exposed columnar GaN array; depositing a metal electrode layer on two sides of the GaN array, and forming ohmic contact or Schottky contact with the GaN layer to obtain a photoelectric detector; the photoelectric detector is connected with a peripheral circuit to form a complete columnar array enhanced photoelectric detector system, the GaN layer of the columnar array structure is adopted, multiple times of reflection and interference on incident light are achieved, and therefore the detection efficiency and the response speed of the photoelectric detector are improved.

The invention discloses stepping type repeated nanoimprinting equipment, a control method and a control system, and relates to the technical field of semiconductor preparation. An imprinting substrate of the nanoimprinting device comprises a plurality of areas to be imprinted which are arranged in an array mode, the nanoimprinting device comprises a displacement module, a glue dripping module and an imprinting module, the glue dripping module and the imprinting module are arranged in the first horizontal direction in a spaced mode, and the top of the displacement module is used for containing the imprinting substrate. The coining module comprises a coining template matched with the to-be-coined area, the coining template is a photoetching template, and the displacement module is controlled to reciprocate between the glue dripping module and the coining module along a first horizontal direction or move along a second horizontal direction; each reciprocating motion is used for realizing glue dripping and imprinting of an area to be imprinted, and the displacement rate of the displacement module in the first horizontal direction is calculated according to a formula (1). According to the control method disclosed by the invention, the distribution uniformity of the dripping glue and the compatibility of the nano-imprinting equipment and the traditional projection type photoetching process can be improved at the same time.

According to the OPC result correction method and the result verification device thereof provided by the invention, the NILS value is introduced as an index for measuring correction quality on the basis of the existing OPC correction method, so that the absolute value of the EPE value of the target graph after OPC correction is ensured to meet the requirement of the preset EPE standard value, and the NILS value of the target graph can be improved; according to the method, the target graph after OPC correction has better spatial graph contrast, and better imaging quality is obtained in the actual exposure process, so that the problem of disconnection or bridging caused by size deviation of the target graph is effectively avoided, and further, the image quality is improved. The better spatial pattern contrast can bring better photoresist morphology and a larger photoetching process window, so that the generation of pattern defects is reduced, and the improvement of the yield of products is more facilitated.

The present application relates to a method, apparatus, and device for analyzing a lithography process window based on stepwise regression. The method comprises: obtaining photoresist pattern image data and determining the constraints required for the lithography process window; determining a lithography process model that satisfies the relationship between the photoresist pattern features, exposure energy, and focal length, and a stepwise regression direction for the lithography process model; performing stepwise regression on the lithography process model based on the photoresist pattern image data in the direction indicated by the stepwise regression direction to obtain multiple candidate lithography process models and model selection index values ​​for each candidate lithography process model; determining a target lithography process model from the multiple candidate lithography process models based on the model selection index values; and determining the lithography process window based on the constraints and the target lithography process model. This method can improve the accuracy of the analysis results of focal length energy matrix data.

The invention relates to the technical field of image processing, and particularly discloses a photoresist defect detection method and system based on image recognition and a cloud platform, and the method comprises the steps: S1, obtaining target image data of a plurality of target images based on photoetching in a specified time period, and obtaining photoresist image data of all target images; s2, determining a plurality of types of photoetching data and a type label of each type of photoetching data; s3, determining a first defect fitting matrix of each target image in the category photoetching data, and determining a second defect fitting matrix of each category label; s4, constructing a defect detection model of each category label; and S5, acquiring a real-time photoetching image to be detected, and determining defect data. By combining artificial intelligence and computer vision technologies and utilizing an automatic defect fitting and classifying method, the accuracy and efficiency of defect identification in the photoetching process are improved, the automation degree of defect detection is improved, and the production efficiency and the product quality are improved.

The invention relates to a piezoelectric resonator, which belongs to the technical field of micro electro mechanical systems, and comprises a resonant body on which micropore structures are periodically arranged; the resonant body is fixed on the substrate, and a cavity or an acoustic reflecting layer is arranged between the substrate and the resonant body; wherein the micropore structure and part of the resonance body around the micropore structure form an in-plane coupling unit which is used for exciting the coupling mode of the resonator. Compared with the prior art, the in-plane coupling units arranged in the x-y plane of the resonator can excite transverse modes in the x-axis direction and the y-axis direction at the same time, an in-plane two-dimensional transverse coupling mode is formed, and the transverse coupling mode is the basis for achieving the photoetching tuning characteristic of the resonator. Appropriate sizes and in-plane arrangement of the in-plane coupling units are defined through a photoetching process, and the resonant frequency of the resonator can be adjusted in a wide frequency band range.

The embodiment of the invention relates to a method, equipment and medium for photoetching simulation. The method proposed herein comprises: determining, from an initial optical signal, a plurality of optical signal components corresponding to a plurality of photolithography in a lithographic process; adjusting each optical signal component in the plurality of optical signal components based on the process parameters corresponding to the multiple exposures, so as to determine a target optical signal related to the photoetching process; and at least based on the target optical signal, determining the simulated morphology of the photoresist after the photoetching process.

The invention relates to the technical field of mobile phone rear cover manufacturing, and particularly provides a pyramid-shaped structure glass mobile phone rear cover manufacturing process which comprises the following steps: coating a layer of photosensitive material with uniform thickness on the surface of glass by using a mask, and forming a high-precision texture pattern on the surface of a glass substrate through exposure and development; the used etching liquid is acid liquid containing fluorine ions, and the parts which do not need to be etched are protected through the mask, so that the glass with fine textures is obtained; according to the characteristics of the photosensitive material, acid, alkali or other organic solvents are used for removing the residual photosensitive material on the surface of a product after the glass substrate is etched; and performing post-processing to obtain the mobile phone rear cover of which the surface is provided with a plurality of concave-convex texture structures. According to the manufacturing method, the mobile phone rear cover with the adjustable texture height and the pyramid-shaped microstructure is manufactured through the high-precision yellow light photoetching technology and the acid etching technology, the texture effect is guaranteed, and meanwhile the smooth hand feeling effect similar to AG products is achieved.

The invention discloses a method for preparing an upper electrode of a gallium arsenide solar cell for a low-cost space, which comprises the following steps of: corroding a gallium arsenide epitaxial wafer taking germanium as a substrate in a mixed acid corrosion solution, removing an oxide layer and pollutants on the surface of the epitaxial wafer, taking out the epitaxial wafer, and cleaning the epitaxial wafer in deionized water; the surface of the active layer of the epitaxial wafer is tightly attached to the metal grid mesh, the epitaxial wafer is put into vacuum evaporation equipment, electrode metal is evaporated layer by layer in an electron beam evaporation mode, and after evaporation is completed, the epitaxial wafer is taken out from the vacuum evaporation equipment when the epitaxial wafer is cooled to 100 DEG C or below; and placing in a vacuum sintering furnace, heating at a constant temperature for a period of time, cooling to below 100 DEG C, and taking out to obtain the space gallium arsenide solar cell top electrode. A traditional photoetching process is replaced by a metal grid mesh, the surface of an active layer of an epitaxial wafer is tightly attached to the metal grid mesh, and then the epitaxial wafer is put into a vacuum coating machine to be subjected to metal evaporation. And the evaporated metal is deposited on the surface of the epitaxial wafer through gaps of the grid mesh to prepare a conductive upper electrode.

The invention discloses a photoetching process overlay error compensation method, a photoetching process overlay error compensation device and a photoetching machine, which can be used in the field of semiconductor manufacturing. The overlay error distribution data is the sum of the average number of absolute values of overlay errors and triple standard deviation; in the polynomial formula of the overlay error distribution data, all coefficients are compensation parameters; based on the overlay error distribution data, obtaining a target stress compensation scheme through a pre-established stress compensation model; the stress compensation model comprises an association relationship between compensation stress and compensation parameters corresponding to each stress actuator group; and driving a stress actuator to apply compensation stress to the mask plate based on the target stress compensation scheme. Therefore, the compensation stress executed by the stress actuator required for compensating the overlay error is obtained through the overlay error distribution data, and then the compensation stress is applied to the mask plate to cause deformation of the mask plate, so that the compensation of the overlay error in the photoetching process is realized, and the overlay error of the photoetching process can be reduced.

Systems, methods, and media for determining a processing parameter associated with a lithography process. In some embodiments, image data of features on a substrate may be obtained, and the image data may be analyzed in Fourier space. Based on the analysis, an amplitude and a phase may be determined, and an overlay of the features may be determined based on the amplitude and the phase.

The invention provides a photoetching method based on a full-transparent substrate, and relates to the technical field of semiconductors. When the method is executed, firstly, an aluminum layer is deposited on the surface of a full-transparent substrate, then, photoresist is uniformly distributed on the surface of the aluminum layer, then, the position of the surface of the full-transparent substrate is determined according to the aluminum layer, then, the photoresist is exposed according to the position of the surface of the full-transparent substrate, and finally, the exposed photoresist is developed. Therefore, by depositing the aluminum layer on the surface of the full-transparent substrate, the light intensity of the reflected signal can be enhanced when the surface of the full-transparent substrate is subjected to a photoetching process, so that a sensor for receiving light rays can smoothly and accurately distinguish the reflected signal and accurately determine the position of the surface of the full-transparent substrate; and thus, automatic photoetching based on the full-transparent substrate is realized.

The invention discloses a mask manufacturing method and a mask, and relates to the technical field of silicon-based OLEDs (Organic Light Emitting Diodes), the mask manufacturing method comprises the following steps: providing a silicon-based substrate, forming a metal seed layer on the surface of the silicon-based substrate, forming a first photoresist layer on the surface of the metal seed layer, and forming a second photoresist layer on the surface of the first photoresist layer; and forming a plurality of first windows for exposing part of the metal seed layer on the surface of the first photoresist layer, forming mask layers for filling the first windows on the surface, facing the first windows, of the metal seed layer by an electroforming process, and removing the first photoresist layer, the silicon-based substrate and the metal seed layer to obtain the mask. According to the manufacturing method, the mask plate is manufactured in a mode of combining the photoetching process and the electroforming process, the opening width of the mask plate depends on the exposure, development and photoresist removal precision in the photoetching process, and compared with existing calendering and etching processes, the manufacturing method can reduce the minimum opening size of the mask plate and improve the manufacturing efficiency of the mask plate. Therefore, the mask plate can be applied to manufacturing of a silicon-based OLED display device with higher PPI.

Aspects of the present disclosure provide methods for determining wafer flatness and for manufacturing semiconductor devices. The method includes: storing a first wafer expansion of a first wafer collected during a lithography process along a first direction parallel to a working surface of the first wafer. The lithography process is used to pattern a structure on the working surface of the first wafer. Prior to a manufacturing step with a wafer flatness requirement, a wafer flatness of the first wafer is determined using a flatness prediction model configured to predict wafer flatness and based on the first wafer expansion collected during the lithography process. In an example, a layer having a thickness based on the determined wafer flatness of the first wafer is deposited on a back side of the first wafer.

The invention relates to an edge photoresist removing method for a negative photoresist photoetching process, which comprises the following steps of: (1) spin-coating negative photoresist on a substrate, and stacking the edge of the substrate to form edge photoresist higher than a middle area; carrying out first soft baking on the substrate; (2) spin-coating positive photoresist, and carrying out secondary soft baking on the substrate; (3) exposing the substrate by using an edge-removing mask plate and edge-removing ultraviolet light; (4) developing the substrate by using a developing solution, and removing edge glue; (5) exposing the substrate by using a patterned mask plate and patterned ultraviolet light, and performing post-baking after exposure; (6) exposing the substrate by using the universal exposure ultraviolet light; and (7) developing the substrate by using a developing solution, and removing all the positive photoresist and the negative photoresist corresponding to the shading region of the patterned mask plate in the step (5) to obtain the patterned photoresist. The method for removing the negative glue and the edge glue is simple to operate, does not need additional process equipment, is high in compatibility of a photoetching process, and is accurate and controllable in an edge removal area.

The invention provides a main junction modulation fast recovery diode chip and a preparation method thereof, and relates to the technical field of semiconductors. The preparation method of the main junction modulation fast recovery diode chip comprises the following steps: providing an epitaxial wafer, and forming a main junction window and a cut-off ring window on a first surface of the epitaxial wafer by adopting a photoetching process; first nonmetal is injected into the main junction window and the cut-off ring window respectively, and diffusion junction pushing is carried out; forming a field limiting ring window on the first surface of the epitaxial wafer by adopting a photoetching process; and second nonmetal is injected into the main junction window and the field limiting ring window respectively and diffusion junction pushing is carried out so as to realize junction depth distribution of the main junction shallow ring junction depth. According to the preparation method of the main junction modulation fast recovery diode chip, the junction depth distribution of the main junction shallow ring junction depth can be generated on the premise of saving one-time photoetching, the withstand voltage, the through-current capability, the surge level and the preparation efficiency of the main junction modulation fast recovery diode chip can be improved, and the manufacturing cost of the main junction modulation fast recovery diode chip is reduced.

An MEMS wafer corrosion thickness monitoring and corrosion process evaluation method comprises the steps that a plurality of monitoring points are designed in a preset area of a silicon wafer pattern surface, the monitoring points are of structures with different shapes and different depths, structures with different heights are formed on photoresist through a multi-depth photoetching process, and the monitoring points are used for monitoring the corrosion thickness of the silicon wafer. The structure is integrally transferred to the surface of a silicon wafer through one-time dry etching, multiple depth monitoring points are formed, an anti-corrosion protection layer is deposited on the pattern face of the wafer, wet etching is carried out on the back face of the wafer, the light-transmitting state of the monitoring points is recognized through chemical corrosive liquid and an optical detection system, and the light-transmitting area proportion is quantified; according to the light transmission sequence and time, the corrosion depth and uniformity of each area of the wafer are calculated, the process result and the wafer quality are evaluated, the wet method corrosion depth can be accurately controlled, the corrosion uniformity in the wafer is greatly improved, and the manufacturing process of the monitoring structure is simplified.

The invention provides a method for determining an optimal focus. The method comprises the following steps of: providing a wafer which is subjected to photoetching treatment under different focus settings; performing optical critical dimension measurement on the photoresist pattern on the wafer to obtain a plurality of side wall angle values respectively corresponding to different focus settings; based on the plurality of side wall angle values and different focus settings, establishing a relationship between the side wall angles and the focuses; and according to the relationship, determining a focus when the side wall angle is the preset target angle as an optimal focus. According to the method, by directly utilizing the side wall angle parameter strongly related to the focusing quality, the measurement interference of a traditional method is avoided, and the optimal focus of the photoetching process can be determined more accurately and reliably, so that the process window is widened, and the process stability and the product yield are improved.

The invention belongs to the technical field of semiconductor manufacturing, and provides a semiconductor light development evolution determination method and device, equipment and a storage medium. The method comprises the following steps: determining a calculation region for simulation light development according to input parameters of a photoresist region and a mask region of a 3D semiconductor device structure, and determining an initial value # imgabs0 # of a level set equation; determining the evolution speed of the photoresist surface based on the input parameters; obtaining a discrete format of the level set equation; solving the discrete format of the level set equation based on the initial value # imgabs1 # of the level set equation and the evolution speed, and obtaining a three-dimensional discrete data field in the calculation area; the light-developed surface area is extracted when the emulation time is reached using a traveling standing method. The level set equation is introduced to simulate and determine the evolution surface after the light development reaches the simulation time, so that the problem that the development condition can only be determined by putting into actual production at present is solved, and the development of a subsequent photoetching process is facilitated.

A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further includes modifying the layout of the lithographic mask based on differences between the estimated printed pattern and a target printed pattern. All of the forward models are implemented on the tensor-based computing platform.

The invention belongs to the field of accelerometers, and particularly relates to a nanometer optical accelerometer and a preparation method thereof.The preparation method comprises the steps that silicon nitride films are deposited on the two faces of a silicon wafer, and a target pattern is formed on the top silicon nitride film on one face through the photoetching technology; etching the silicon nitride film at the target pattern by adopting an etching method to form a hole of the target pattern, then etching the silicon wafer by adopting the etching method, and releasing the silicon nitride film to obtain a suspended surface with a mass block; a suspended surface with a mass block is used as a top chip of the nano accelerometer; a quartz plate of which the two surfaces are respectively plated with a high-reflective film and an antireflection film and the middle is provided with a groove is used as a bottom chip, and the top chip and the bottom chip are integrated to prepare the nano optical accelerometer; only one photoetching process is needed, the micro-nano machining process is simple and compatible with the CMOS process, the cost is lower, and the yield of device preparation is improved.

The invention relates to the technical field of semiconductor photoetching, and discloses a super-resolution photoetching and guided self-assembly-based graphic structure preparation method, which comprises the following steps of: S1, forming a guide layer, a reflective metal layer and a photosensitive film layer which are sequentially stacked on a substrate; s2, exposing and developing the photosensitive film layer by adopting super-resolution photoetching equipment, and forming a photoetching pattern on the photosensitive film layer; s3, the reflective metal layer and the guide layer are sequentially etched to the upper surface of the substrate, and the photoetching pattern is transmitted to the guide layer; s4, taking the photoetching pattern as a guide structure, and coating a molecular brush material in a groove of the guide structure to form an affinity polymer layer; s5, the groove of the guide structure is internally coated with a block copolymer, and after annealing, guide self-assembly is conducted to form a block copolymer layer; and S6, selectively removing part of the polymer block region to obtain a graphic structure. According to the method, a super-resolution photoetching process is combined with guided self-assembly of the block copolymer, so that higher process expansion is realized, and a graphic structure with the resolution within 20nm is obtained.