1001 results about "Lithography process" patented technology

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

The invention provides an optical proximity correction method and system based on mask error model optimization, and a terminal, and the method comprises the steps: building a data sample set containing a plurality of process conditions through obtaining a large amount of mask manufacturing data under a specific photoetching process; and based on the sample set, constructing a physical optical sub-model and a machine learning sub-model to form a mask error model for outputting a final mask key size value. And then, according to a plurality of preset alternative weight coefficient combinations, reconstructing an objective function which introduces a mask error term, calculating corresponding objective function values, and correcting the photoetching pattern by using an OPC algorithm corresponding to each objective function value to obtain performance index data so as to determine an optimal weight coefficient combination. And finally, optimizing the OPC algorithm by using the target function of the optimal combination, thereby realizing the accurate correction of the photoetching pattern, and improving the precision and yield of semiconductor manufacturing. According to the method, the mask error model comprehensively considering physical optics and machine learning is established, and the OPC process is introduced, so that the influence of the mask error can be predicted and compensated more accurately, the critical dimension deviation and the like are reduced, and the device performance and the yield are improved. The method can adapt to different process conditions, and parameters and weight coefficients can be dynamically adjusted. And moreover, rework can be reduced, automatic adjustment is realized through closed-loop feedback control, the production stability and efficiency are improved, and the cost is reduced.

The invention relates to the technical field of piezoelectric single-crystal filters, in particular to a filter based on a heterogeneous integrated piezoelectric single-crystal thin film and a preparation method, the filter comprises a Si substrate, a dry film, the piezoelectric single-crystal thin film, a SiO2 layer and a Si wafer are sequentially arranged on the Si substrate, metal balls are arranged on the Si wafer, the metal balls are connected with electrodes, and the electrodes are connected with the piezoelectric single-crystal thin film. And the electrode passes through the Si wafer and the SiO2 layer and is connected with the piezoelectric single crystal film. When the filter is prepared, bonding packaging can be performed after a cavity area is etched on a dry film, a resonance area is directly defined through a photoetching process, the influence of etching on the strength of the piezoelectric single crystal film is avoided, a silicon wafer bonding technology can be combined, double-sided packaging can be realized, and batch production is supported; in the process, only the electrode patterning step needs to be adjusted according to the type of the filter, and then the existing MEMS process integration is utilized, so that the preparation of the FBAR and the XBAR on the same production line is realized, the process compatibility is good, and the problems that the existing preparation method is poor in compatibility and is difficult to realize large-scale production are solved.

The resist composition exhibits a high contrast, improved maximum resolution, and satisfactory sensitivity and line width roughness (LWR) when processed by lithography using high-energy radiation, especially electron beam (EB) and EUV, and a pattern forming process using the resist composition. The resist composition comprising (A) a base polymer containing a polymer comprising repeat units having an acid labile group and repeat units having a carboxy group, (B) an organic solvent, and (C) a hypervalent iodine compound having formula (1):

The invention discloses a DLD chip and method based on high-flow-speed composite flow channel multi-target sorting. The chip comprises a sample inlet, a sheath fluid inlet, a rectification module and a two-stage deterministic lateral displacement DLD sorting module, the rectification module adopts a circular microcolumn array to optimize fluid distribution, and the first-stage module realizes primary sorting through a microfluid channel and is connected with the second-stage module; and the second-stage module is communicated with three sample outlets after being accurately sorted through a microfluid channel II. The chip is made of a PDMS material through a soft photoetching process, and the two stages of sorting modules are designed to be of a rectangular structure connected end to end and are respectively composed of elliptical micro-columns with opposite deflection angles. Under the high-flow-rate working condition, stable separation of cells can be kept, blockage is not prone to occurring, the good sorting effect on various cells of different sizes is achieved, the flow channel layout is compact, the chip manufacturing process is simplified, and the chip is suitable for the sorting scene with the high-flux requirement.

The invention relates to the technical field of semiconductors, in particular to a columnar array enhanced photoelectric detector and a preparation method thereof, and the method comprises the following steps: depositing a continuous GaN layer on a substrate through an epitaxial growth method; forming a columnar array structure pattern and an electrode region on the GaN layer through a photoetching process, and removing a part of the GaN layer through an etching process to form an exposed columnar GaN array; depositing a metal electrode layer on two sides of the GaN array, and forming ohmic contact or Schottky contact with the GaN layer to obtain a photoelectric detector; the photoelectric detector is connected with a peripheral circuit to form a complete columnar array enhanced photoelectric detector system, the GaN layer of the columnar array structure is adopted, multiple times of reflection and interference on incident light are achieved, and therefore the detection efficiency and the response speed of the photoelectric detector are improved.

The invention discloses stepping type repeated nanoimprinting equipment, a control method and a control system, and relates to the technical field of semiconductor preparation. An imprinting substrate of the nanoimprinting device comprises a plurality of areas to be imprinted which are arranged in an array mode, the nanoimprinting device comprises a displacement module, a glue dripping module and an imprinting module, the glue dripping module and the imprinting module are arranged in the first horizontal direction in a spaced mode, and the top of the displacement module is used for containing the imprinting substrate. The coining module comprises a coining template matched with the to-be-coined area, the coining template is a photoetching template, and the displacement module is controlled to reciprocate between the glue dripping module and the coining module along a first horizontal direction or move along a second horizontal direction; each reciprocating motion is used for realizing glue dripping and imprinting of an area to be imprinted, and the displacement rate of the displacement module in the first horizontal direction is calculated according to a formula (1). According to the control method disclosed by the invention, the distribution uniformity of the dripping glue and the compatibility of the nano-imprinting equipment and the traditional projection type photoetching process can be improved at the same time.

According to the OPC result correction method and the result verification device thereof provided by the invention, the NILS value is introduced as an index for measuring correction quality on the basis of the existing OPC correction method, so that the absolute value of the EPE value of the target graph after OPC correction is ensured to meet the requirement of the preset EPE standard value, and the NILS value of the target graph can be improved; according to the method, the target graph after OPC correction has better spatial graph contrast, and better imaging quality is obtained in the actual exposure process, so that the problem of disconnection or bridging caused by size deviation of the target graph is effectively avoided, and further, the image quality is improved. The better spatial pattern contrast can bring better photoresist morphology and a larger photoetching process window, so that the generation of pattern defects is reduced, and the improvement of the yield of products is more facilitated.

The present application relates to a method, apparatus, and device for analyzing a lithography process window based on stepwise regression. The method comprises: obtaining photoresist pattern image data and determining the constraints required for the lithography process window; determining a lithography process model that satisfies the relationship between the photoresist pattern features, exposure energy, and focal length, and a stepwise regression direction for the lithography process model; performing stepwise regression on the lithography process model based on the photoresist pattern image data in the direction indicated by the stepwise regression direction to obtain multiple candidate lithography process models and model selection index values ​​for each candidate lithography process model; determining a target lithography process model from the multiple candidate lithography process models based on the model selection index values; and determining the lithography process window based on the constraints and the target lithography process model. This method can improve the accuracy of the analysis results of focal length energy matrix data.

The invention relates to the technical field of image processing, and particularly discloses a photoresist defect detection method and system based on image recognition and a cloud platform, and the method comprises the steps: S1, obtaining target image data of a plurality of target images based on photoetching in a specified time period, and obtaining photoresist image data of all target images; s2, determining a plurality of types of photoetching data and a type label of each type of photoetching data; s3, determining a first defect fitting matrix of each target image in the category photoetching data, and determining a second defect fitting matrix of each category label; s4, constructing a defect detection model of each category label; and S5, acquiring a real-time photoetching image to be detected, and determining defect data. By combining artificial intelligence and computer vision technologies and utilizing an automatic defect fitting and classifying method, the accuracy and efficiency of defect identification in the photoetching process are improved, the automation degree of defect detection is improved, and the production efficiency and the product quality are improved.

The invention relates to a piezoelectric resonator, which belongs to the technical field of micro electro mechanical systems, and comprises a resonant body on which micropore structures are periodically arranged; the resonant body is fixed on the substrate, and a cavity or an acoustic reflecting layer is arranged between the substrate and the resonant body; wherein the micropore structure and part of the resonance body around the micropore structure form an in-plane coupling unit which is used for exciting the coupling mode of the resonator. Compared with the prior art, the in-plane coupling units arranged in the x-y plane of the resonator can excite transverse modes in the x-axis direction and the y-axis direction at the same time, an in-plane two-dimensional transverse coupling mode is formed, and the transverse coupling mode is the basis for achieving the photoetching tuning characteristic of the resonator. Appropriate sizes and in-plane arrangement of the in-plane coupling units are defined through a photoetching process, and the resonant frequency of the resonator can be adjusted in a wide frequency band range.

The invention provides a photoetching method based on a full-transparent substrate, and relates to the technical field of semiconductors. When the method is executed, firstly, an aluminum layer is deposited on the surface of a full-transparent substrate, then, photoresist is uniformly distributed on the surface of the aluminum layer, then, the position of the surface of the full-transparent substrate is determined according to the aluminum layer, then, the photoresist is exposed according to the position of the surface of the full-transparent substrate, and finally, the exposed photoresist is developed. Therefore, by depositing the aluminum layer on the surface of the full-transparent substrate, the light intensity of the reflected signal can be enhanced when the surface of the full-transparent substrate is subjected to a photoetching process, so that a sensor for receiving light rays can smoothly and accurately distinguish the reflected signal and accurately determine the position of the surface of the full-transparent substrate; and thus, automatic photoetching based on the full-transparent substrate is realized.

An MEMS wafer corrosion thickness monitoring and corrosion process evaluation method comprises the steps that a plurality of monitoring points are designed in a preset area of a silicon wafer pattern surface, the monitoring points are of structures with different shapes and different depths, structures with different heights are formed on photoresist through a multi-depth photoetching process, and the monitoring points are used for monitoring the corrosion thickness of the silicon wafer. The structure is integrally transferred to the surface of a silicon wafer through one-time dry etching, multiple depth monitoring points are formed, an anti-corrosion protection layer is deposited on the pattern face of the wafer, wet etching is carried out on the back face of the wafer, the light-transmitting state of the monitoring points is recognized through chemical corrosive liquid and an optical detection system, and the light-transmitting area proportion is quantified; according to the light transmission sequence and time, the corrosion depth and uniformity of each area of the wafer are calculated, the process result and the wafer quality are evaluated, the wet method corrosion depth can be accurately controlled, the corrosion uniformity in the wafer is greatly improved, and the manufacturing process of the monitoring structure is simplified.

The invention provides a method for determining an optimal focus. The method comprises the following steps of: providing a wafer which is subjected to photoetching treatment under different focus settings; performing optical critical dimension measurement on the photoresist pattern on the wafer to obtain a plurality of side wall angle values respectively corresponding to different focus settings; based on the plurality of side wall angle values and different focus settings, establishing a relationship between the side wall angles and the focuses; and according to the relationship, determining a focus when the side wall angle is the preset target angle as an optimal focus. According to the method, by directly utilizing the side wall angle parameter strongly related to the focusing quality, the measurement interference of a traditional method is avoided, and the optimal focus of the photoetching process can be determined more accurately and reliably, so that the process window is widened, and the process stability and the product yield are improved.

The invention belongs to the field of accelerometers, and particularly relates to a nanometer optical accelerometer and a preparation method thereof.The preparation method comprises the steps that silicon nitride films are deposited on the two faces of a silicon wafer, and a target pattern is formed on the top silicon nitride film on one face through the photoetching technology; etching the silicon nitride film at the target pattern by adopting an etching method to form a hole of the target pattern, then etching the silicon wafer by adopting the etching method, and releasing the silicon nitride film to obtain a suspended surface with a mass block; a suspended surface with a mass block is used as a top chip of the nano accelerometer; a quartz plate of which the two surfaces are respectively plated with a high-reflective film and an antireflection film and the middle is provided with a groove is used as a bottom chip, and the top chip and the bottom chip are integrated to prepare the nano optical accelerometer; only one photoetching process is needed, the micro-nano machining process is simple and compatible with the CMOS process, the cost is lower, and the yield of device preparation is improved.

The invention relates to the technical field of semiconductor photoetching, and discloses a super-resolution photoetching and guided self-assembly-based graphic structure preparation method, which comprises the following steps of: S1, forming a guide layer, a reflective metal layer and a photosensitive film layer which are sequentially stacked on a substrate; s2, exposing and developing the photosensitive film layer by adopting super-resolution photoetching equipment, and forming a photoetching pattern on the photosensitive film layer; s3, the reflective metal layer and the guide layer are sequentially etched to the upper surface of the substrate, and the photoetching pattern is transmitted to the guide layer; s4, taking the photoetching pattern as a guide structure, and coating a molecular brush material in a groove of the guide structure to form an affinity polymer layer; s5, the groove of the guide structure is internally coated with a block copolymer, and after annealing, guide self-assembly is conducted to form a block copolymer layer; and S6, selectively removing part of the polymer block region to obtain a graphic structure. According to the method, a super-resolution photoetching process is combined with guided self-assembly of the block copolymer, so that higher process expansion is realized, and a graphic structure with the resolution within 20nm is obtained.

Method for producing an optical test element (19) for determining a fit defect of an optical surface (20). The method comprises the following steps: - Determining a CGH design (24) suitable for measuring the optical surface (20), - Generating a CGH auxiliary structure (25) corresponding to the CGH design (24) on an auxiliary substrate (30) using a direct-write lithography process, - Generating an image of the CGH auxiliary structure (25) on a final substrate (40) using a transfer lithography process, - Generating a CGH structure (50) corresponding to the CGH design (24) based on the generated image. The method offers the advantage that the auxiliary substrate can be produced with high precision using a standardized direct-write lithography system, regardless of the size of the optical test element.

The invention discloses a parameter optimization method for photoresist, which comprises the following steps: collecting process multi-source data, preprocessing to construct a data set, and generating environment and equipment disturbance vectors; photoresist material data are extracted, multiple features are fused in a dimensionality reduction mode, and photoresist dynamic vectors are generated; acquiring process time sequence data, inputting the process time sequence data into the improved CycleNet network, and extracting process dynamic characteristics; constructing a tensor input solving unit, calculating the acid concentration and the developing thickness, and predicting the imaging quality; the photoresist dynamic vector is evolved, and a complete disturbance set is generated in combination with the multiple disturbance vectors; and constructing a robust optimization target, evaluating a parameter imaging effect, and obtaining optimal process parameter output. According to the method, robust optimization and stable control of key parameters of the photoetching process are realized by constructing a parameter optimization process fusing photoresist dynamic evolution, process time sequence disturbance and multi-source disturbance perception.

The invention relates to the related technical field of semiconductors, in particular to a chip processing production line monitoring method and system, and the method comprises the steps: collecting photoetching process monitoring data; setting a feature matrix; determining a focusing window boundary; configuring a focal length offset compensation amount based on the feature matrix in combination with a focusing window boundary and photolithographic process monitoring data; and determining a deviation amplitude score by using an edge placement error model to perform graded reminding. The technical problems that window boundary definition monitored by a chip processing production line depends on experience to set a fixed standard, focal length offset cannot be effectively compensated, and the risk that edge placement errors exceed the standard exists are solved, and coupling analysis of an optical proximity effect and a process window is carried out in a mask layer, a lens layer and a photoresist layer and a feature matrix is constructed, so that the edge placement error is accurately determined. And the compensation parameters and the error trend are dynamically matched, the focal length offset compensation precision is improved, an edge placement error model is used for determining a deviation amplitude score and carrying out graded reminding, and the technical effect of abnormity processing timeliness is enhanced.

The embodiment of the invention provides a method, a system and equipment for establishing an optical proximity correction model and a storage medium, and the method comprises the steps: providing a test layout which is provided with a first test pattern; performing correction operation on the first test pattern by using a first optical proximity correction model to generate mask pattern data of the first test pattern; obtaining a physical contour of a first type semiconductor structure formed on a physical wafer by the first test pattern when exposure operation is executed according to the mask pattern data; the physical contour is the contour of the first type semiconductor structure corresponding to the repeated region; performing photoetching process simulation on the mask pattern data by using the first optical proximity correction model to generate a prediction contour; and correcting the first optical proximity correction model according to the physical contour and the predicted contour to obtain a second optical proximity correction model. By adopting the technical scheme, the correction precision of the OPC model can be improved, and the photoetching quality is improved.

The invention provides a compact photoetching simulation system based on a physical model, which relates to the technical field of photoetching simulation tools and physical modeling and comprises a model construction module, a kernel visualization module, a simulation calculation module, a result evaluation and optimization module, a model library management module, a real-time simulation module, an error compensation module and a simulation result verification module. The model building module is used for building a three-dimensional photoetching model according to the light source wavelength, the coherence factor, the numerical aperture and the aberration coefficient of a photoetching machine in the photoetching equipment as well as the photoresist type, the photoetching resolution requirement and the photoetching pattern feature size of the photoetching process. Diffraction of light in a projection objective, interference of light on the surface and inside of photoresist and physical and chemical processes of a photoresist molecule microscopic level are comprehensively considered, and compared with a basic physical model, the complex propagation path of light in photoetching equipment can be accurately simulated.

A single integrated circuit is provided, comprising a memory region and a non-memory region. The memory region comprises a first conductive structure, a memory element disposed upon the first conductive structure, and a first via disposed upon the memory element. The non-memory region comprises a second conductive structure, and a second via disposed upon the second conductive structure. The first conductive structure and the second conductive structure are formed by a first photolithography process comprising a first photomask, and the first conductive structure is configured to be a first bottom electrode in the memory region. The first via and the second via are formed by a third photolithography process comprising a third photomask. The first photomask and the third photomask comprise a same pattern.

Disclosed is a three-stage alignment system and alignment method for semiconductor lithography, which significantly improves the accuracy of wafer alignment in semiconductor manufacturing. The alignment system includes a first alignment module for coarse alignment with a relatively large tolerance range; a second alignment module equipped with a dual-camera system for intermediate refinement of alignment based on wafer marks; and a third alignment module for fine alignment within a submicron tolerance range using mask marks on a photomask. A robotic arm transfers the wafer between stages, maintaining the integrity of the alignment. The wafer alignment marks are cross-shaped, while the photomask marks are square, thereby ensuring precise alignment in the third alignment module. This innovative method increases both the efficiency and accuracy of semiconductor device manufacturing.

The invention provides a photoresist process parameter compensation method and a compensation control system, and the method comprises the steps: building a Lasso regression model through collected process parameters in a plurality of batches of photoresist processes, and carrying out the data training, the method comprises the following steps: reversely analyzing a nonlinear influence mechanism of an external environment temperature on the photoresist thickness through a model, then obtaining a compensation rule of a real-time environment temperature through a Lasso regression model, and dynamically adjusting a photoresist spin-coating rotating speed in a current batch photoresist process so as to maintain the thickness of the current batch photoresist to be constant; according to the method, the stability of the critical dimension (CD) of the photoetching process is improved, a photoetching process window is expanded (the exposure dose fluctuation range of a photoetching machine is widened and the debugging cost of the photoetching process is reduced), accurate temperature compensation of the photoetching process is realized, so that the no-load energy consumption of the photoetching machine is reduced, and the product yield and the reliability are improved.

The invention discloses a photoresist removing method and device and a reworking method of a photoetching process, and the photoresist removing method comprises the steps: providing a substrate, and enabling the surface of the substrate to be provided with photoresist; etching the photoresist by using etching gas with concentration difference in different directions to form an irregular glue layer structure; performing wet stripping treatment on the irregular adhesive layer structure; and carrying out surface hydrophobicity treatment on the substrate after the irregular adhesive layer structure is stripped. According to the invention, the defect that the photoresist on the silicon-based substrate collapses after reworking of the photoetching process can be eliminated.

The invention discloses an oxide semiconductor plane p / n superstructure and a preparation method thereof. According to the method, a latticed mask is formed on the surface of an oxide thin film based on a photoetching process, O2 atmosphere annealing (100-300 DEG C, 15-40 min) is combined, the local oxygen vacancy concentration of a mask covering area and an exposed area is precisely regulated and controlled, and precise in-situ conversion of a p type (oxygen-rich area) and an n type (oxygen-poor area) in a homogeneous material is achieved. The planar p / n superstructure breaks through the strict limitation of a traditional vertical multi-junction structure on material doping and interface quality, the width of a depletion region is expanded to the micron order through the p / n homojunction arrays alternately distributed in the plane, and the bulk recombination effect of photon-generated carriers is remarkably inhibited. According to the method, an innovative technical route of photoetching-assisted in-situ construction of the planar multi-junction photoelectrode is created, the method has the advantages of interface atomic-scale lattice matching, simple process, high compatibility, accurate and controllable space charge distribution and the like, and a technical foundation is laid for non-assisted solar water decomposition, research and development of self-driven optoelectronic devices and the like.

The invention provides an infrared detector deep mesa etching process based on three layers of masks and an infrared detector, and belongs to the field of infrared detector mesa etching. The process comprises the following steps: spin-coating a stress buffer layer on the surface of a superlattice epitaxial layer, and curing and forming; depositing a hard mask serving as an etching barrier layer; depositing an inorganic oxide; spin-coating photoresist to form a composite patterned top layer, and then forming a mesa pattern through a photoetching process; taking the mesa pattern as a mask, and transferring the mesa pattern to the hard mask through reactive ion etching; etching the stress buffer layer by adopting plasma until the surface of the superlattice epitaxial layer is exposed; the three layers of masks are used as blocking, deep etching is carried out through inductively coupled plasma, and the etching depth is 5.6-6 microns; a post-processing step; according to the process provided by the invention, high-quality and high-aspect-ratio mesa etching can be realized on the premise of not introducing extra pollution and remarkably increasing the cost, and the process is suitable for preparing a deep-mesa and high-aspect-ratio device.

A first location within a mask pattern of a semiconductor circuit layout is determined, based on a feature of the mask pattern that is within a threshold distance of a boundary in the mask pattern. The mask pattern is based on a first mask exposure and a second mask exposure that meet at the boundary. The first location defines where to place a first assistive feature that reduces a sensitivity to lithographic process variations of the feature of the mask pattern. A second location of the mask pattern is also determined. The second location defines where to place a second assistive feature that reduces stray light at the boundary during the first mask exposure and the second mask exposure. The mask pattern is then modified to place the first assistive feature in the first location and the second assistive feature in the second location.

The invention relates to the field of integrated circuit manufacturing, in particular to a mask process correction method, device and equipment and a storage medium. Inputting the target mask pattern as an initial electron beam exposure pattern into a pre-trained mask top and bottom surface process correction model; determining a mask layer bottom simulation pattern size and a mask layer top simulation pattern size corresponding to each edge section in the simulation electron beam exposure pattern to obtain a corresponding side wall included angle; according to the size of the simulation pattern at the bottom of the mask layer, determining a size-included angle comparison data set corresponding to each edge section to obtain an included angle offset; further determining a target size offset; and adjusting the position of a corresponding edge section in the simulation pattern at the bottom of the mask layer according to the target size offset. The similarity between a wafer pattern obtained by carrying out a photoetching process on the mask layer corrected by the method and a photoetching target pattern is greatly improved.