71253results about "Electrical testing" patented technology

A plasma reactor for processing a workpiece such as a semiconductor wafer has a housing defining a process chamber, a workpiece support configured to support a workpiece within the chamber during processing and comprising a plasma bias power electrode. The reactor further includes plural gas sources containing different gas species, plural process gas inlets and an array of valves capable of coupling any of said plural gas sources to any of said plural process gas inlets. The reactor also includes a controller governing said array of valves and is programmed to change the flow rates of gases through said inlets over time. A ceiling plasma source power electrode of the reactor has plural gas injection zones coupled to the respective process gas inlets. In a preferred embodiment, the plural gas sources comprise supplies containing, respectively, fluorocarbon or fluorohydrocarbon species with respectively different ratios of carbon and fluorine chemistries. They further include an oxygen or nitrogen supply and a diluent gas supply. The controller is programmed to produce flow of different process gas species or mixtures thereof through different ones of said plural gas injection zones. The controller is further programmed to change over time the species content of the gases flowing through different ones of said plural gas injection zones.

A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.

Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics. A variety of techniques for configuring, severing, and overcoating the wire stem are disclosed. In an exemplary embodiment, a free end of a wire stem is bonded to a contact area on a substrate, the wire stem is configured to have a springable shape, the wire stem is severed to be free-standing by an electrical discharge, and the free-standing wire stem is overcoated by plating. A variety of materials for the wire stem (which serves as a falsework) and for the overcoat (which serves as a superstructure over the falsework) are disclosed. Various techniques are described for mounting the contact structures to a variety of electronic components (e.g., semiconductor wafers and dies, semiconductor packages, interposers, interconnect substrates, etc.), and various process sequences are described. The resilient contact structures described herein are ideal for making a "temporary" (probe) connections to an electronic component such as a semiconductor die, for burn-in and functional testing. The self-same resilient contact structures can be used for subsequent permanent mounting of the electronic component, such as by soldering to a printed circuit board (PCB). An irregular topography can be created on or imparted to the tip of the contact structure to enhance its ability to interconnect resiliently with another electronic component. Among the numerous advantages of the present invention is the great facility with which the tips of a plurality of contact structures can be made to be coplanar with one another. Other techniques and embodiments, such as wherein the falsework wirestem protrudes beyond an end of the superstructure, or is melted down, and wherein multiple free-standing resilient contact structures can be fabricated from loops, are described.