56results about How to "Data retention time is long" patented technology

To provide a power storage device, an operation condition of which is easily analyzed. A secondary battery includes a sensor that is a measurement unit, a microcontroller unit that is a determination unit, and a memory that is a memory unit. With the sensor, conditions of the secondary battery such as the remaining battery power, the voltage, the current, and the temperature are measured. The microcontroller unit performs arithmetic processing of the measurement results and determines the operation condition of the secondary battery. Further, the microcontroller unit stores the measurement result in the memory in accordance with the operation condition of the secondary battery.

The invention relates to a tube-like phase-change memory single structure and making method, the phase-change memory single structure comprises a top electrode, a bottom electrode and a memory part. The single structure has basic characters that: phase-change material distributes at lateral wall of a hole, the phase-change is implemented in the hole in reading and writing operation through heating own by using small sectional area and big resistance of the phase-change material, and tubular is formed at two ends of ring phase-change material through adding phase-change material insulating layer as closure, thus improving use efficiency of heat in the reading and writing operation, the memory part is a tubular structure enclosed by the phase-change material up and down, and is filled with metal, insulation materials or high resistivity material. The memory structure of the invention can reduce operating current, and has small-power, high heat utilization ratio and good data retention performance, and the invention can improve the consistency of resistance value of device of chip.

A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme.

The invention belongs to the technical field of dynamic random access memories and in particular relates to an EDRAM (Enhanced Dynamic Random Access Memory) unit of a gain unit, a memory and an operating method thereof. Based on a writing MOS (Metal Oxide Semiconductor) transistor, a reading MOS transistor, a writing word line, a writing bit line, a reading word line, a reading bit line and an equivalent parasitic capacitor, the EDRAM unit of the gain unit provided by the invention is obtained by increasing a coupling complementary MOS transistor and a shared bit line which is connected to a fixed voltage such that the EDRAM unit of the gain unit has the characteristics of long data retention time and low refreshing frequency; and the memory formed by the EDRAM unit of the gain unit has the characteristics of high reading speed and low power consumption.

Flags are formed to respectively correspond to memory cell groups each including volatile memory cells. Each flag indicates as a set state that the memory cells store data in a second memory mode. In a changing operation of changing from a first memory mode in which data is independently retained by each memory cell to a second memory mode in which same data are retained in the memory cells of each memory cell group, each flag is reset in response to the first access to the corresponding memory cell group. Therefore, only the first access is made in the second memory mode in each memory cell group. The memory cells are accessed in a mode according to the flag in the changing operation, thereby allowing a system managing the semiconductor memory to freely access the memory cells even during the changing operation. Consequently, a practical changing time can be eliminated.

A resistive random access memory device includes a bottom electrode, a plurality of memory stacks separately formed over the bottom electrode, a third oxygen diffusion barrier layer formed between the memory stacks, and a top electrode formed over the plurality of memory stacks and the third oxygen diffusion barrier layer. Each of the plurality of memory stacks includes a resistive switching layer formed over the bottom electrode, a first oxygen diffusion barrier layer formed over the resistive switching layer, a conductive oxygen reservoir layer formed over the first oxygen diffusion barrier layer, and a second oxygen diffusion barrier layer formed over the conductive oxygen reservoir layer.

The invention relates to a resistance random memory based on a columbium oxide film and a preparation method thereof, belonging to the technical field of memories. The memory unit comprises a substrate and a metal-insulation layer-metal (MIM) structure unit, wherein a top electrode of the MIM structure unit is metal films, such as titanium nitride and the like, the insulation layer is a columbiumoxide film, and a lower electrode adopts Pt or Au. The MIM structure in the invention represents excellent transformation and memory properties between high and low resistance states under the continuous scanning excitation of direct-current voltage. Further, the invention also provides the preparation method of the memory unit. The method comprises the preparation of a substrate material, the lower electrode, a dielectric film and an upper electrode and the like.

The embodiment of the invention discloses an AND logic circuit and a chip. The circuit comprises a resistance change memristor array and comparators; the non-inverting input ends of the same line of resistance change memristors in the resistance change memristor array are connected with one another, so that the non-inverting input ends of the same line of the resistance change memristors serve as a signal input end or an auxiliary signal input end of the AND logic circuit; the auxiliary signal input end is connected to a low level when working; inverting input ends of the same row of resistance change memristors in the resistance change memristor array are connected with the input end of a comparator, so that the output end of the comparator serves as a signal output end of the AND logic circuit; when the voltage received by the input end of the comparator is greater than a threshold voltage, the output end of the comparator outputs a high level; and when the voltage received by the input end of the comparator is lower than the threshold voltage, the output end of the comparator outputs the low level. By the embodiment of the invention, the area occupied by the AND logic circuit is saved and simultaneously the programmable performance of the AND logic circuit is realized.

A resistive random access memory device is provided, which includes a bottom electrode, a resistive switching layer disposed on the bottom electrode, an oxidizable layer disposed on the resistive switching layer, a first oxygen diffusion barrier layer disposed between the oxidizable layer and the resistive switching layer, and a second oxygen diffusion barrier layer disposed on the oxidizable layer.

The invention belongs to the technical field of semiconductor memories, and particularly relates to a semi-floating gate memory based on a two-dimensional material and a preparation method thereof. The semi-floating gate memory comprises an L-shaped bottom gate, a barrier layer covering the surface of the bottom gate, and an L-shaped semi-floating gate layer which is a first type of two-dimensional material, and the top of the L-shaped semi-floating gate layer is flush with the top of the bottom gate; the semi-floating gate memory further comprises a semi-closed tunneling layer at the bottom of the semi-floating gate, wherein the semi-closed tunneling layer is a second type of two-dimensional material, and the upper surface of the semi-closed tunneling layer is flush with the top of the semi-floating gate; the semi-floating gate memory further comprises a channel layer which covers the semi-floating gate and the semi-closed tunneling layer and is made of a third type two-dimensional material, and the upper surface of the channel layer is flush with the top of the barrier layer; the semi-floating gate memory further comprises a source electrode and a drain electrode which are on thesurface of the channel and are a fourth type of two-dimensional material. The first type of two-dimensional material and the third type of two-dimensional material form a diode, and the first type oftwo-dimensional material, the third type of two-dimensional material, the barrier layer and the bottom gate form a grid-control diode. The device is good in reliability and high in data erasing and writing speed, and the data retention time can be prolonged; in addition, the device is small in size and suitable for being used in ultrathin electronic equipment.

The invention provides a method and system for reducing eDRAM (Embedded Dynamic Random Access Memory) refreshing energy consumption in a neural network chip. The method comprises the steps of trainingan original neural network model, and determining a target neural network model with the maximum fault-tolerant capability, and data hold time of an eDRAM corresponding to the target neural network model; scheduling each layer of the target neural network model, and determining a computing mode of each layer and data survival time of each layer under the lowest computing energy consumption; and setting the target neural network model to be performed on the neural network chip according to the computing model of each layer, for storage subareas of each layer, if effective data is not stored inthe storage subareas or the data survival time of each layer is shorter than the data holder time, not refreshing the storage subareas. According to the method, the unnecessary refreshing operation can be removed to the greatest extent, and the eDRAM refreshing energy consumption in the neural network chip is greatly reduced.

The invention relates to a dynamic storage based on an open bit line structure. The dynamic storage comprises a decoder circuit, a sense amplifier and a plurality of dual-storage units, wherein the decoder circuit comprises a first decoding unit and a second decoding unit which have the same structure, an input end of a first XOR gate circuit is connected with an external address signal RA<0>, the other input end of the first XOR gate circuit is connected with a cfg_dualcell signal, and an output end of a first phase inverter controls a bit line Wl of one dual-storage unit in a storage unit array module to be opened; and an input end of a second XOR gate circuit is connected with an inverted signal/RAI<0> of the external address signal RA<0>, the other input end of the second XOR gate circuit is connected with the cfg_dualcell signal, and an output end of a second phase inverter controls the other bit line Wl of one dual-storage unit in the storage unit array module to be opened. According to the dynamic storage, the technical problems of high energy consumption and low reliability are overcome, and the data hold time of the dynamic storage is remarkably improved.

The embodiment of the invention provides an error correction method and device for a memory. The method comprises the steps of: determining initial voltage positions of threshold voltage distribution states, and determining left-shift voltage positions of the threshold voltage distribution states; and deleting at least one distribution state of the threshold voltage distribution states according to the initial voltage positions and the left-shift voltage positions of the threshold voltage distribution states so as to increase the voltage interval between the threshold voltage distribution states. Therefore, in the embodiment of the invention, by determining the initial voltage positions and the left-shift voltage positions of the threshold voltage distribution states, whether data retention error occurs in a memory can be determined; and after data retention error occurs, at least one distribution state of the threshold voltage distribution states is deleted, and the voltage interval between the threshold voltage distribution states is increased, so that the data retention error is reduced, and the data retention time of a storage unit is prolonged.

The present invention provides an indium phosphide resistance variable material-based resistive random access memory and a preparation method thereof. The resistive random access memory comprises a platinum bottom electrode, an indium phosphide resistance variable material doped with S and Fe and a silver top electrode, and the preparation method comprises the steps of taking an insulating inorganic material of which the surface is deposited with platinum metal as a substrate, adopting a pulse laser technology to deposit an indium phosphide thin film on the surface of the substrate to form the indium phosphide resistance variable material, and then covering a hard mask on the surface of the indium phosphide resistance variable material, adopting a magnetron sputtering technology to deposit a silver electrode layer, and removing the mask to obtain the indium phosphide resistance variable material-based resistive random access memory. According to the present invention, an indium phosphide single crystal wafer and a preparation method of the indium phosphide single crystal wafer of utilizing the pulse laser technology to deposit the indium phosphide thin film, are limited, so that the consistency and stability of the indium phosphide resistance variable material in the resistive random access memory are guaranteed, and the resistive random access memory has the characteristics of being wide in storage window, long in data hold time and high in durability.

A non-volatile memory is provided. The non-volatile memory comprises at least a silicon-on-insulator transistor including a substrate; an insulating layer disposed on the substrate; an active region disposed on the insulating layer; and an energy barrier device disposed in the active region and outputting a relatively small current when the non-volatile memory is read.

The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate, The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.