6713 results about "Band gap" patented technology

A water soluble semiconductor nanocrystal capable of light emission is provided, including a quantum dot having a selected band gap energy, a layer overcoating the quantum dot, the overcoating layer comprised of a material having a band gap energy greater than that of the quantum dot, and an organic outer layer, the organic layer comprising a compound having a least one linking group for attachment of the compound to the overcoating layer and at least one hydrophilic group space apart from the linking group by a hydrophobic region sufficient to prevent electron charge transfer across the hydrophobic region. The particle size of the nanocrystal core is in the range of about 12.ANG. to about 150.ANG., with a deviation of less than 10% in the core. The coated nanocrystal exhibits photoluminescende having quantum yield of greater than 10% in water.

Described herein are semiconductor structures comprising (i) a Si substrate; (ii) a buffer region formed directly over the Si substrate, wherein the buffer region comprises (a) a Ge layer having a threading dislocation density below about 10⁵ cm⁻²; or (b) a Ge_1-xSn_x layer formed directly over the Si substrate and a Ge_1-x-ySi_xSn_y layer formed over the Ge_1-xSn_x layer; and (iii) a plurality of III-V active blocks formed over the buffer region, wherein the first III-V active block formed over the buffer region is lattice matched or pseudomorphically strained to the buffer region. Further, methods for forming the semiconductor structures are provided and novel Ge_1-x-ySi_xSn_y, alloys are provided that are lattice matched or pseudomorphically strained to Ge and have tunable band gaps ranging from about 0.80 eV to about 1.4O eV.

An organic electroluminescent device 1 comprising, an emitting layer (50) and an electron-transporting layer (60) between a cathode (80) and an anode (20), the electron-transporting layer (60) comprising a compound represented by formula (1), the emitting layer (50) comprising a host material which is a compound with an energy gap of 2.8 eV or less represented by formula (2) and a dopant which is an indenoperylene derivative,

A-B   (1)

wherein A is an aromatic hydrocarbon group with three or more carbocycles and B is a substituted or unsubstituted heterocyclic group,

X—(Y)_n   (2)

wherein X is a condensed aromatic ring group with three or more carbocycles, Y is a group selected from substituted or unsubstituted aryl, substituted or unsubstituted diarylamino, substituted or unsubstituted arylalkyl and substituted or unsubstituted alkyl groups, and n is an integer of 1 to 6, provided that Ys may be the same or different when n is 2 or more.

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells in NOR or NAND memory architectures that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Memory cells of the present invention also allow multiple bit storage. These characteristics allow memory device embodiments of the present invention to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

A method of manufacturing improved thin-film solar cells entirely by sputtering includes a high efficiency back contact/reflecting multi-layer containing at least one barrier layer consisting of a transition metal nitride. A copper indium gallium diselenide (Cu(In_XGa_1-x)Se₂) absorber layer (X ranging from 1 to approximately 0.7) is co-sputtered from specially prepared electrically conductive targets using dual cylindrical rotary magnetron technology. The band gap of the absorber layer can be graded by varying the gallium content, and by replacing the gallium partially or totally with aluminum. Alternately the absorber layer is reactively sputtered from metal alloy targets in the presence of hydrogen selenide gas. RF sputtering is used to deposit a non-cadmium containing window layer of ZnS. The top transparent electrode is reactively sputtered aluminum doped ZnO. A unique modular vacuum roll-to-roll sputtering machine is described. The machine is adapted to incorporate dual cylindrical rotary magnetron technology to manufacture the improved solar cell material in a single pass.

In one embodiment, a method of forming a multijunction solar cell having lattice mismatched layers and lattice-matched layers comprises growing a top subcell having a first band gap over a growth semiconductor substrate. A middle subcell having a second band gap is grown over the top subcell, and a lower subcell having a third band gap is grown over the middle subcell. The lower subcell is substantially lattice-mismatched with respect to the growth semiconductor substrate. The first band gap of the top subcell is larger than the second band gap of the middle subcell. The second band gap of the middle subcell is larger than the third band gap of the lower subcell. A support substrate is formed over the lower subcell, and the growth semiconductor substrate is removed. In various embodiments, the multijunction solar cell may further comprise additional lower subcells. A parting layer may also be provided between the growth substrate and the top subcell in certain embodiments. Embodiments of this reverse process permit the top and middle subcells to have high performance by having atomic lattice spacing closely matched to that of the growth substrate. Lower subcells can be included with appropriate band gap, but with lattice spacing mismatched to the other subcells. The reduced performance caused by strain resulting from mismatch can be mitigated without reducing the performance of the upper subcells.

Provided is a semiconductor opto-electronic device that may comprise an active layer including a quantum well and a barrier layer on a substrate, upper and lower waveguide layers on and underneath the active layer, respectively, and upper and lower clad layers on and underneath the upper and lower waveguide layers, respectively. The semiconductor opto-electronic device may further comprise an upper optical confinement layer (OCL) between the active layer and the upper waveguide layer and having an energy gap smaller than the energy gap of the upper waveguide layer and equal to or larger than the energy gap of the barrier layer, and a lower OCL between the active layer and the lower waveguide layer and having an energy gap smaller than the energy gap of the lower waveguide layer and equal to or smaller than the energy gap of the barrier layer. Also provided is a method of fabricating the semiconductor opto-electronic device.

A photonic crystal optical switch having a periodic dielectric structure including at least one input waveguide. First and second waveguide arms branch from the input waveguide in which the relative optical path lengths of electromagnetic radiation within the arms are controlled by stimuli. At least one output waveguide that combines the electromagnetic radiation propagating within the first and second waveguide arms.

Disclosed is a semiconductor light-emitting element, comprising an n-type-cladding layer; a light guide layer positioned on the n-type cladding layer; a multiple quantum well structure active layer positioned on the light guide layer; a p-type carrier overflow prevention layer positioned on the active layer and having an impurity concentration of 5×10¹⁸ cm⁻³ to not more than 3×10¹⁹ cm⁻³; a p-type light guide layer positioned on the p-type carrier overflow prevention layer and-having an impurity concentration of 1×10¹⁸ cm⁻³ or more and less-than that of the p-type carrier overflow prevention layer; and a p-type cladding layer positioned on the p-type light guide layer and having a band gap narrower than the p-type carrier overflow prevention layer, and a method of manufacturing the same.

Provided is a remote control system with which leakage current flowing in a switch can be reduced so that power consumption can be reduced. The remote control system includes a portable information terminal, a server, and an electric device. The on/off of the switch included in the electric device is controlled using information transmitted from the portable information terminal to the server. The switch includes a transistor formed using a semiconductor whose band gap is larger than that of single crystal silicon in a channel formation region.

A resonant tunneling diode, and other one dimensional electronic, photonic structures, and electromechanical MEMS devices, are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.

A substrate-fluorescent LED having a fluorescent-impurity doped substrate and an epitaxial emission structure including an active layer and being made on the substrate. The epitaxial emission structure emits blue or green light corresponding to the band gap of the active layer. The substrate absorbs a part of the blue or green light and makes fluorescence of a longer wavelength. Neutral color light or white light is emitted from the LED. The fluorescent substrate is n-AlGaAs(Si dope), GaP(Zn+O dope), ZnSe(Cu+I, Ag+I, Al+I dope), GaN(O.C.Va(N) dope) or so.

A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

It has a structure in which an active layer (5) that emits light by electric current injection is sandwiched between an n-type cladding layer (4) and a p-type cladding layer (6) made of materials having a larger band gap than the active layer (5), wherein the active layer (5) is made, for example, of Cd_xZn_1−xO (0≦x<1). It is further more preferable if the cladding layers (4), (6) are made, for example, of Mg_yZn_1−yO (0≦y<1). This narrows the band gap of the ZnO materials, and an oxide semiconductor capable of being wet-etched, easy to handle with, and excellent in crystallinity can be used as a material for an active layer or a cladding layer of a semiconductor light emitting device such as a blue light emitting diode or a blue laser diode in which an active layer is sandwiched between cladding layers, so that a blue semiconductor light emitting device being excellent in light emission characteristics can be obtained.

To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

A method of forming a multijunction solar cell comprising an upper subcell, a middle subcell, and a lower subcell comprising providing first substrate for the epitaxial growth of semiconductor material; forming a first solar subcell on said substrate having a first band gap; forming a second solar subcell over said first subcell having a second band gap smaller than said first band gap; and forming a grading interlayer over said second subcell having a third band gap larger than said second band gap forming a third solar subcell having a fourth band gap smaller than said second band gap such that said third subcell is lattice mismatched with respect to said second subcell.

Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.