4326 results about "Semiconductor materials" patented technology

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention discloses a self-isolation type image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the self-isolation type image sensing structure is characterized in that a shallow trench isolation structure is exposed after the back surface of a substrate is thinned, then a first semiconductor layer is extended on the back surface of the substrate, and a first isolation structure is prepared in the first semiconductor layer; sequentially depositing a second semiconductor material layer and a metal grating material layer on the first semiconductor layer; sequentially etching the metal grating material layer and the second semiconductor material layer to form a plurality of metal grating structures distributed at intervals and corresponding self-isolation structures; extending a plurality of photosensitive layers in the photosensitive region groove between the adjacent self-isolation structures to form a photosensitive region; and then activating, preparing a filter layer and the like are carried out to obtain a complete back-illuminated image sensor. The self-isolation photodiode is obtained by changing the structural distribution of the photodiode, unexpectedly, the problem that the substrate is damaged by doping is solved, meanwhile, the crosstalk effect is greatly reduced, and the performance of the image sensor is improved.

The invention discloses a chalcogenide phase change storage material potential model construction method, a material characteristic calculation method and electronic equipment, and belongs to the field of semiconductor materials. On the basis of a potential model trained by a first training set collected through molecular dynamics simulation based on a first principle calculation method, a current potential model is fully utilized, molecular dynamics simulation is carried out based on the current potential model, training samples are further collected, representative training samples are screened out, and a second training set is formed; according to the method, the training efficiency is high, the generalization ability is high, and a large amount of training data can be obtained with low cost. Meanwhile, verification of physical properties is introduced into convergence conditions of model training, so that the physical consistency and interpretability of the potential model are improved; on the basis, the training set which is good in diversity and sufficient in data volume can be obtained with low cost, and meanwhile the accuracy of the potential model in an actual application scene is further improved.

The invention relates to the technical field of crystal material preparation, in particular to a ternary layered selenide Ge3Sb4Se7 semiconductor material and a preparation method thereof. The preparation method of the ternary layered selenide Ge3Sb4Se7 semiconductor material comprises the following steps that S001, germanium powder, antimony powder and selenium powder with the molar ratio being 3: 4: 7 serve as raw materials, the temperature is increased to 900-950 DEG C under the vacuum condition, and heat preservation is conducted for 12-24 h at the temperature; s002, after heat preservation is finished, the temperature is reduced to 475-500 DEG C at the cooling rate of 1-5 DEG C / min, and heat preservation is conducted for 3-5 days at the temperature; and after heat preservation is finished, furnace cooling or quenching cooling is performed to reach the room temperature, and the layered ternary selenide single-phase material with the chemical formula being Ge3Sb4Se7 is obtained. The ternary layered selenide Ge3Sb4Se7 semiconductor material prepared by the invention is a single-phase material and has the characteristics of low thermal conductivity and low resistivity, so that the ternary layered selenide Ge3Sb4Se7 semiconductor material has application potential in the fields of thermoelectric devices, photoelectric detection and the like.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a layer stack of an undoped semiconductor material layer and a source semiconductor layer. The undoped semiconductor material layer contacts a bottom end of the vertical semiconductor channel.

The invention discloses an intelligent cutting method and system for a semiconductor machined part based on path reconstruction, and relates to the technical field of semiconductor manufacturing processes, and the method comprises the steps: monitoring a machined part image, and extracting the edge contour and internal feature point information; fitting and constructing a three-dimensional contour model; planning a cutting path based on the model and outputting initial parameters; and cutting according to the initial parameters and iteratively optimizing the path according to the feedback information until the cutting task is completed. The technical problems that in the semiconductor device manufacturing process, a traditional cutting mode is difficult to cope with dynamic interference of semiconductor materials, fine modeling and protection on the edges and the interiors of the machined parts are lacked, cutting precision is insufficient, and the machined parts are prone to being damaged and scrapped are solved, fine modeling on the edges and the interiors of the machined parts is achieved, and the cutting precision is improved. The cutting path is optimized by combining dynamic interference real-time feedback, the cutting precision is improved, the damage rejection rate of machined parts is reduced, and the technical effects of high precision and high reliability of semiconductor device manufacturing are met.

The present application relates to the technical field of tungsten alloy materials, and in particular to a tungsten alloy wire, a preparation method therefor, and a use thereof in cutting of a semiconductor material. The tungsten alloy is composed of the following elements in percentage by mass: 0.4-1.1 wt% of L, 0.001-0.25 wt% of Z, and the balance of tungsten and inevitable impurities, wherein L is one or more than two of lanthanum, cerium, praseodymium, neodymium, gadolinium and erbium, and Z comprises oxygen and carbon. The wire diameter of the wire is 20-60 μm, the wire contains linear L or a compound of L along the wire axis direction, and the radial average width D of L or the compound of L is smaller than or equal to 5 nm. According to the present application, the linear L element is doped between tungsten base bodies, and the radial average width of L is controlled to be smaller than or equal to 5 nm, so that the wire has the tensile strength of 5000 MPa or above under the wire diameter of 20-60 μm, and the machining performance of the tungsten alloy wire is enhanced.

An electrically inactive betavoltaic battery, an electrically active betavoltaic battery, and methods of making the same are provided. In implementations, a method of making an electrically active betavoltaic battery includes: providing an electrically inactive betavoltaic battery device having one or more diodes incorporating a semiconductor material layer having a stable non-radioactive isotope; and irradiating the electrically inactive betavoltaic battery device with thermal neutrons, thereby causing the conversion of at least a portion of the stable non-radioactive isotope to a radionuclide and creating the electrically active betavoltaic battery, wherein the semiconductor material layer acts as both an electron emitter and an electron absorber simultaneously.

The invention discloses a semiconductor film performance cooperative control method and system based on multi-parameter coupling, and belongs to the technical field of semiconductor material manufacturing, and the method specifically comprises the steps: determining a control parameter set containing plasma power density and other parameters, and building a multi-parameter coupling response model; generating sample points by using Latin hypercube sampling, quantifying a parameter interaction effect, and forming a dynamic weight matrix in combination with a graph model; monitoring data such as plasma emission spectrum intensity ratio in real time, comparing the data with a model predicted value, and correcting the model; a multi-objective optimization problem is constructed based on the correction model and the dynamic weight matrix, and optimal parameter configuration is solved by using a conjugate gradient method; alternately applying a high-frequency pulse and a relaxation stage according to the optimal configuration, and modulating the pulse frequency according to a Fibonacci sequence; and finally, based on the substrate temperature, planning a temperature rise path by using an S-shaped curve, superimposing cosine modulation, and introducing oscillation compensation gas to compensate the reactant concentration deviation, thereby realizing accurate optimization of the material preparation process.

The invention belongs to the technical field of semiconductor material processing equipment, and particularly relates to a bonding system, which comprises a film forming chamber used for preparing a film with active point locations on the surface of an original substrate to form an active substrate; the bonding chamber comprises a first carrier and a second carrier, and the first carrier and the second carrier are respectively used for keeping the active substrates and enabling the two kept active substrates to be opposite to each other; at least one of the first carrier and the second carrier is provided with a force output part, and the force output part is used for outputting force for crimping the active substrate held by the first carrier and the second carrier; and the transmission chamber comprises a substrate taking and placing module which is used for taking and placing the substrates on different stations. According to the bonding system provided by the invention, a very thin active film layer can be prepared on the to-be-bonded surface of the substrate to form the active substrate, bonding can be directly carried out at room temperature, the stress problem caused by mismatching of thermal expansion coefficients of heterogeneous materials can be solved, and the product quality of a bonding sheet is improved.

The invention relates to a magnetic field sensor based on a room-temperature two-dimensional magnetic semiconductor material and a preparation method and application thereof, and the preparation method comprises the steps: arranging two electrodes which are not communicated with each other on an insulating substrate, obtaining a layered iron gallium tellurium material, transferring the layered iron gallium tellurium material to the insulating substrate, enabling at least one layered iron gallium tellurium material to be separated from the insulating substrate, and enabling the layered iron gallium tellurium material to be separated from the insulating substrate. The first product covers the two electrodes at the same time, tetrabutylammonium cations or oxygen plasmas are used for carrying out an intercalation reaction on the layered iron gallium tellurium material of the first product, and the layered iron gallium tellurium material of the first product is converted into an intercalated layered iron gallium tellurium material; and performing vacuum annealing to obtain the magnetic field sensor. The sensor provided by the invention reflects the magnetic field intensity by using the polarized light current between the electrodes, and can realize wide-range and high-precision magnetic field detection.

The invention provides a preparation method of a gate-all-around transistor device and the gate-all-around transistor device. The method comprises the following steps: providing a preset substrate; the preset base comprises a substrate, a plurality of periodically distributed fins located on the substrate and a dummy gate structure located on the fins, and each fin comprises a laminated structure formed by a plurality of sacrificial layers and channel layers which grow alternately; etching the side walls of the two sides of the sacrificial layer to enable the two sides of each sacrificial layer of the laminated structure to be embedded grooves relative to the channel layer; performing epitaxy of a semiconductor material on the two sides of the laminated structure after the groove is formed, so that the groove is filled with the semiconductor material, and epitaxial layers are formed on the two sides of the laminated structure; and epitaxially growing a source electrode and a drain electrode, etching to remove the false gate structure to form a groove, etching to remove the sacrificial layer in the laminated structure to form a channel, and forming a gate structure in the groove and the channel. According to the invention, the two sides of the sacrificial layer can be wrapped with a thick epitaxial semiconductor material, thereby avoiding device failure caused by wrong etching through of the epitaxial silicon layer, and improving the overall yield of products.

A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

The invention provides a heterojunction memristor based on a two-dimensional material CrPS4 and a preparation method of the heterojunction memristor, and relates to the field of microelectronic semiconductor material photoelectric memristors. The heterojunction memristor comprises a substrate, a two-dimensional material CrPS4-based heterojunction and an active metal electrode which are stacked in sequence. According to the vertical heterojunction memristor disclosed by the invention, the prepared novel two-dimensional material CrPS4 is adopted as a resistive function layer material, and the vertical heterojunction memristor shows excellent non-volatile resistive property.

The invention relates to the technical field of semiconductors, in particular to a gallium oxide heteroepitaxial substrate and a preparation method thereof. The gallium oxide heteroepitaxial substrate comprises: a sapphire substrate; the sapphire substrate is provided with a beveled surface; a periodic pattern structure is arranged on the beveled surface of the sapphire substrate; the depth of a repetitive unit of the periodic pattern structure is 200 nm to 20 [mu] m, the maximum envelope size is 100 nm to 50 [mu] m, and the period interval is 200 nm to 100 [mu] m. The sapphire substrate is subjected to beveling processing and patterning processing, lattice mismatch is remarkably relieved, stress is released, accordingly, dislocation density is reduced, defects in the gallium oxide thin film are reduced, the gallium oxide single crystal thin film with better crystal quality is obtained, and the method has important application value in the field of gallium oxide thin film semiconductor material preparation.

The invention belongs to the technical field of semiconductor material manufacturing, and particularly relates to a preparation method of a piezoelectric single crystal composite film material, which comprises the following steps of: carrying out ion implantation on a piezoelectric functional material, carrying out wet oxidation treatment on the surface of a support substrate, and then cleaning and blow-drying to obtain the piezoelectric single crystal composite film material. Oxygen and nitrogen mixed plasma is used for activating the surfaces of a supporting substrate and a piezoelectric functional material, pre-bonding, standing, nitrogen annealing, thinning and stripping are carried out in a low-vacuum environment, the preparation method is simple in process and low in cost, and the composite film prepared through the method is high in bonding strength, free of damage to a stripping interface and good in bonding performance. And meanwhile, cracking and fragmentation are effectively avoided, the yield is effectively improved, and industrial production is facilitated.

The utility model relates to the technical field of semiconductor detection, and aims to provide a two-dimensional semiconductor material impurity online detection system which comprises a main analysis target chamber and a sample replacement target chamber, the sample injection system comprises a magnetic coupling transmission rod connected with the sample change target chamber and a manipulator connected with the main analysis target chamber; the sample processing system comprises a laser annealing device and a sample rack positioned in the main analysis target chamber; the Ar + ion gun system is connected with the main analysis target chamber; the flight time detector is connected with the main analysis target chamber; the data acquisition system comprises a nuclear electronics system and is used for converting detected signals into electric signals and transmitting the electric signals to a computer. Through the cooperation of the main analysis target chamber, the sample changing target chamber, the sample injection system, the sample processing system, the Ar + ion gun system, the flight time detector and the nuclear electronics system, the dynamic data acquisition and analysis are realized, and the problem that the impurity H element of the two-dimensional semiconductor material cannot be nondestructively detected by the conventional surface analysis method is solved.

The invention relates to the field of crystal detection, and discloses a multifunctional comprehensive scintillation crystal and semiconductor material energy spectrum test system, which comprises a crystal adaptation module for judging the type and size of a placed crystal through an optical identification and parameter matching mechanism, and a signal acquisition module for amplifying, filtering and digitally processing an acquired signal, the signal correction module is used for correcting waveform distortion and baseline drift through a dynamic gain adjustment algorithm of a low-noise pre-amplifier and a multi-channel pulse analyzer; the data analysis module is used for generating an energy spectrum curve according to input signals and calculating energy resolution, counting rate, light attenuation time or carrier mobility, and the environment calibration module is used for dynamically evaluating shading degree, environment light, temperature and electromagnetic interference through an optical sensor and a temperature and humidity detector in the camera obscura and outputting updated calibration parameters. The method has the advantages of improving the detection efficiency, precision and consistency.

The invention discloses a monatomic catalyst capable of retaining surface defects of a catalyst as well as a preparation method and application of the monatomic catalyst, and belongs to the field of catalysis. The monatomic catalyst comprises an active metal component, a doping element and a carrier, the carrier is a semiconductor material rich in surface defects. The preparation method adopts a light-induced migration-conversion strategy. The monatomic catalyst which is obtained by the preparation method and retains the surface defects of the semiconductor material is applied to the fields of photocatalysis, thermocatalysis and electrocatalysis, and shows excellent performance.

The invention relates to the technical field of crystal material preparation, in particular to a layered selenide Ge3Sb2Se5 semiconductor material and a preparation method thereof. The preparation method of the layered selenide Ge3Sb2Se5 semiconductor material comprises the following steps: grinding a Ge3Sb4Se7 material, putting the ground Ge3Sb4Se7 material into a quartz tube, adding iodine particles, performing vacuum packaging in the quartz tube, putting one end, with raw materials, of the quartz tube into a high-temperature region, and putting one end, without raw materials, of the quartz tube into a low-temperature region; raising the temperature to 400 + / -25 DEG C at the low-temperature region end and 500 + / -25 DEG C at the high-temperature region end, preserving heat for 7 days, and naturally cooling to room temperature to obtain the Ge3Sb2Se5 semiconductor material. The crystal structure of the Ge3Sb2Se5 semiconductor material belongs to an orthorhombic system, and the Ge3Sb2Se5 semiconductor material has the characteristics of low thermal conductivity and low resistivity. According to the preparation method disclosed by the invention, the Ge3Sb2Se5 semiconductor material can be stably prepared, and a material is provided for physical property research of the Ge3Sb2Se5 semiconductor material and preparation of semiconductor photoelectric devices and the like.

The invention discloses a ferroelectric semiconductor junction field effect transistor, a preparation method and application. The transistor can simultaneously realize optical sensor, storage, synapse and logic in a single device by utilizing the physical characteristics of the transistor. The structure comprises a source electrode, a drain electrode, a control grid electrode, a channel layer, a ferroelectric grid layer, an oxide layer and a substrate from top to bottom. The channel layer is made of a two-dimensional transition metal sulfide semiconductor material, the ferroelectric gate layer is made of a two-dimensional ferroelectric semiconductor material, the source electrode and the drain electrode are located on two layers of the two-dimensional semiconductor channel respectively, and the control gate is located over the ferroelectric gate layer. According to the preparation method and application of the ferroelectric semiconductor junction field effect transistor, the logic functions of optical signal sensing, data storage, synaptic calculation and self-switching can be integrated in a single transistor, the function discrete limitation of a traditional device is broken through, a new path is provided for a high-density integrated reconfigurable electronic device, and the field effect transistor is suitable for large-scale popularization and application. And the structure complexity and the function density are effectively balanced.

Heterogeneous photonic circuits comprise a gain section optically coupled to a photonics section. The gain section can include at least one gain waveguide which can be formed from a III-V semiconductor material to provide optical gain. The gain waveguide can be coupled to optical components in the photonics section to form an integrated pump module. The photonics section can include a light-generating photonic circuit, which can comprise at least one waveguide doped with a rare-earth ion or transition-metal ion. Output from the integrated pump module and / or the light-generating photonic circuit can be tunable. Tuning can be implemented with feedback control.

The invention discloses a method for measuring the intrinsic carrier mobility of a semiconductor material, and relates to the technical field of semiconductor material performance measurement. The method comprises the following steps: establishing a measurement system for the intrinsic carrier mobility of the semiconductor material; using an optical delay line to continuously change the relative time delay between the probe light and the pump light, obtaining the light intensity of the probe light under the action of the pump light and without the action of the pump light, testing to obtain a transient reflection dynamic spectrum of the semiconductor material, and extracting to obtain a Brillouin oscillation signal; calculating an electron deformation potential, a hole deformation potential and a semiconductor material elastic modulus based on the Brillouin oscillation signal; and calculating the intrinsic carrier (electron and hole) mobility of the semiconductor material based on the electron deformation potential, the hole deformation potential and the elastic modulus of the semiconductor material. Aiming at the lack of a method for experimentally measuring the intrinsic carrier mobility of a material at present, the measurement method disclosed by the invention fills the blank in the field.

The invention provides a semiconductor device, a preparation method thereof and electronic equipment. The preparation method of the semiconductor device comprises the steps that a substrate with a functional device is provided, a functional part of the functional device is exposed out of the substrate, and the functional part is made of a semiconductor material; then, a diffusion layer is formed, so that the diffusion layer covers the exposed function part, and the material of the diffusion layer is a doped semiconductor material; next, heat treatment is carried out, so that doped ions of the diffusion layer are diffused to the functional part, and a first conductive layer is formed; removing the heat-treated diffusion layer to expose the first conductive layer; and then, forming a second conductive layer, so that the second conductive layer covers the first conductive layer, and the second conductive layer is used for being connected with an external device. Contact resistance between the first conductive layer and the second conductive layer is reduced, and lattice damage is avoided.

The invention relates to the technical field of semiconductor material surface characteristic detection, and discloses a semiconductor surface character quality detection system based on machine vision, which comprises an image acquisition unit and a processor, and is characterized in that the processor operates a pre-verification module to verify the information fidelity of an input image by calculating the spectrum entropy value of the image; afterwards, after the image passes the verification, a stability evaluation module is operated, the module extracts a stroke skeleton of the character to generate a plurality of local pixel regions with consistent topologies, calculates a local information entropy value which is used as a material microscopic state non-uniformity representation in each region, and compares the local information entropy value with a preset threshold value to generate an anomaly judgment signal; according to the method, the physical basis of quality evaluation is transferred from a formed static state to the traceability of the stability of the manufacturing process, so that the judgment of potential risks such as process drift does not depend on the occurrence of defects such as line breakage or deformation any more.

The invention discloses a perovskite solar cell and a preparation method thereof, and belongs to the technical field of perovskite solar cells. SAM molecules are introduced between the hole transport layer and the perovskite active layer, the photoelectric conversion efficiency of the perovskite solar cell is improved, an interface modification layer comprising a sheet-shaped P-type semiconductor material is further introduced at the interface of the hole transport layer and the SAM layer, the interface of the hole transport layer / the SAM layer / the perovskite active layer is improved, and the photoelectric conversion efficiency of the perovskite solar cell is improved. The hole transport layer and the perovskite active layer are separated from each other, the energy level difference between the functional layers is reduced, the carrier extraction and transmission of an interface are enhanced, the sheet structure of the sheet P-type semiconductor material can cooperate with the compact SAM layer to block the direct contact between the hole transport layer and the perovskite active layer, and the hole transport efficiency is improved. And the reduction reaction of halide ions in an interinterface hole transport material and a perovskite material is effectively prevented.

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.

The invention provides a multiband photoresponse nerve synapse device based on a two-dimensional and organic heterostructure, an array and application, and belongs to the technical field of organic electric solid-state devices. The device provided by the invention adopts a three-end bottom gate top contact structure and comprises a gate substrate, an insulating layer, a channel layer and a source / drain electrode, and the channel layer forms an II-type heterojunction by a two-dimensional semiconductor material with a narrow-band gap characteristic and an organic semiconductor material. The heterostructure realizes ultraviolet to far infrared (365nm-10 [mu] m) multiband photoelectric response, and shows synaptic plasticity under light pulse modulation, including short-term enhancement, long-term enhancement and learning-forgetting-re-learning characteristics. Large-area array preparation of the device can be realized through methods such as chemical vapor deposition, solution spin coating, jet printing or layer-by-layer self-assembly. The technology not only can be used for brain-like learning and memory simulation, but also can be applied to the fields of sensing and memory integrated intelligent systems, optical neural networks, artificial vision, multi-mode intelligent sensing and the like.

A light-emitting device and an electronic apparatus including the same are provided. The light-emitting device includes: a first electrode; a second electrode facing the first electrode; m emission units stacked between the first electrode and the second electrode and including an emission layer; and m−1 charge generation layers each between two neighboring emission units from among the m emission units, wherein m is an integer of 2 or more, at least one of the m emission units includes an inorganic mixed layer between the first electrode and the emission layer, and the inorganic mixed layer includes an inorganic insulating material and an inorganic semiconductor material.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.