6716 results about "Semiconductor materials" patented technology

A device including a first integrated device die and a semiconductor device. The first integrated device die can include a die insulating layer and a die conductive feature at least partially embedded in the die insulating layer. The semiconductor device can include a first insulating layer on the first surface, a device conductive feature at least partially embedded in the first insulating layer, and a first heavily doped semiconductor material electrically connected to the device conductive feature. The die conductive feature can be connected to power or ground through at least the first heavily doped semiconductor material.

The invention discloses a green preparation process of a microwave-assisted synthesized perovskite semiconductor material, which aims at solving the problems of long reaction period, large reagent dosage, heavy pollution and the like of the traditional perovskite preparation process, adopts a novel organic-inorganic hybrid precursor and green solvent system, and accelerates the reaction by microwave radiation. The rapid and environment-friendly synthesis of the material is realized by accurately regulating and controlling microwave parameters and combining multiple processes such as intermittent and collaborative ultrasonic processes. Novel compounds such as nitrogen-containing heterocyclic borate and organic phosphonate are introduced to optimize the performance of the material. The process significantly shortens the preparation period, reduces reagent consumption, improves photoelectric properties, and enhances material stability.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with a high-mobility gate oxide layer and a preparation process of the SiC MOSFET device, and belongs to the technical field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; by optimizing the gate oxide layer preparation process and combining the design of the T-shaped P-layer, the semi-elliptical lightly doped N-type half layer and the like in the device, the interface quality of the gate oxide layer and a semiconductor material is effectively improved, the scattering of a carrier by an interface state is reduced, and meanwhile, due to the synergistic effect of the structures such as the quarter-circle-shaped side symmetric P-layer and the square heavily doped N layer, the performance of the device is improved. The internal electric field distribution and the carrier transmission path of the device are optimized, and the channel carrier mobility is remarkably improved.

The invention discloses a self-isolation type image sensing structure, a sensor and a preparation method, and belongs to the field of semiconductors, the self-isolation type image sensing structure is characterized in that a shallow trench isolation structure is exposed after the back surface of a substrate is thinned, then a first semiconductor layer is extended on the back surface of the substrate, and a first isolation structure is prepared in the first semiconductor layer; sequentially depositing a second semiconductor material layer and a metal grating material layer on the first semiconductor layer; sequentially etching the metal grating material layer and the second semiconductor material layer to form a plurality of metal grating structures distributed at intervals and corresponding self-isolation structures; extending a plurality of photosensitive layers in the photosensitive region groove between the adjacent self-isolation structures to form a photosensitive region; and then activating, preparing a filter layer and the like are carried out to obtain a complete back-illuminated image sensor. The self-isolation photodiode is obtained by changing the structural distribution of the photodiode, unexpectedly, the problem that the substrate is damaged by doping is solved, meanwhile, the crosstalk effect is greatly reduced, and the performance of the image sensor is improved.

A burst-mode optical receiver for an optical line terminal (OLT) of a passive optical network (PON) comprises a variable optical attenuator (VOA), a photodiode (PD) which may be a pin-PD or an APD, a transimpedance amplifier (TIA), and a feedback / control circuit for adjusting a bias voltage of the VOA in response to a burst-mode optical input signal level, to provide an attenuated optical output signal to the PD having a narrower dynamic range. Providing signal level adjustment in the optical domain mitigates the requirement for a burst-mode TIA with a large dynamic range and provides for fast switching. The burst-mode optical receiver may comprise a waveguide configuration, wherein a first electro-absorption modulator (EAM) is operable as the VOA and a second EAM is operable as the photodiode. A monolithically integrated electro-photonic circuit comprising the VOA, PD, TIA and feedback / control circuit may be provided using InP-based semiconductor materials.

Embodiments of a microelectronic assembly comprise: a first set comprising one or more of first integrated circuit (IC) dies; a second set comprising another one or more of the first IC dies; a plate between, and in direct contact with, the first set and the second set; and a second IC die coupled to the first set, the second set, and the plate. Each IC die comprises a substrate of semiconductor material and an interconnect region including metallization in interlayer dielectric (ILD), the substrate and the interconnect region share a planar interface, and the first IC dies and the second IC die are arranged with the planar interfaces of the first IC dies parallel to each other and orthogonal to the planar interface of the second IC die.

The invention relates to the technical field of semiconductor material preparation, and provides a method for controlling the resistivity of a fifth main group element doped crystal bar, crystal pulling time is distinguished in different crystal pulling stages, the volatilization coefficient of doped elements in different time periods is adjusted, the volatilization amount of the doped elements in each time interval is calculated more accurately, and the resistivity of the doped crystal bar is controlled. Therefore, the amount of doping elements required for controlling the resistance can be calculated more accurately, the resistance of the crystal bar can be adjusted more effectively and more accurately, the resistance difference between the head and the tail of the single-crystal crystal bar can be better reduced, meanwhile, through timely adjustment of the control process of the grade and the ending volatilization amount, the supplementary doping condition in the crystal pulling process is defined, and the crystal pulling efficiency is improved. And the resistance hit rate of the crystal bar is improved, and the head and tail resistance difference is reduced, so that the resistivity of each part of the crystal bar is accurately controlled, and the consistency of subsequent silicon wafer product quality is ensured.

The invention discloses a chalcogenide phase change storage material potential model construction method, a material characteristic calculation method and electronic equipment, and belongs to the field of semiconductor materials. On the basis of a potential model trained by a first training set collected through molecular dynamics simulation based on a first principle calculation method, a current potential model is fully utilized, molecular dynamics simulation is carried out based on the current potential model, training samples are further collected, representative training samples are screened out, and a second training set is formed; according to the method, the training efficiency is high, the generalization ability is high, and a large amount of training data can be obtained with low cost. Meanwhile, verification of physical properties is introduced into convergence conditions of model training, so that the physical consistency and interpretability of the potential model are improved; on the basis, the training set which is good in diversity and sufficient in data volume can be obtained with low cost, and meanwhile the accuracy of the potential model in an actual application scene is further improved.

Embodiments of the present application relate to the technical field of semiconductor lasers, and provide a semiconductor laser and a manufacturing method therefor, which are used to mitigate the problem of chirp in semiconductor lasers. The semiconductor laser comprises: a substrate; a ridge waveguide which is arranged on the substrate and extends in a first direction of the substrate; and a grating which is arranged at a top portion of the ridge waveguide. The grating comprises first regions and second regions periodically arranged in the first direction, each first region comprises a semiconductor material, each second region comprises an insulating dielectric material, and the refractive index of the insulating dielectric material is greater than the refractive index of the semiconductor material.

The embodiment of the invention relates to a method for ion implantation simulation, electronic equipment and a storage medium. The method comprises: determining an initial position of each ion in an exposed surface of a simulated semiconductor device; determining first collision data generated by collision between specified reference ions in the ions and material atoms of the semiconductor device in the implantation process; determining second collision data of each other ion based on comparison of surrounding material information of the other ions in each ion and surrounding material information of the reference ion; and determining the distribution condition of each ion in the simulated semiconductor material based on the first collision data and the second collision data. According to the technical scheme, the calculation amount in the simulation ion implantation process can be effectively reduced, the calculation time is remarkably shortened, and the simulation efficiency is improved.

Examples described herein relate to an optical device that entails phase shifting an optical signal. The optical device includes an optical waveguide having a first semiconductor material region and a second semiconductor material region formed adjacent to each other and defining a junction therebetween. Further, the optical device includes an insulating layer formed on top of the optical waveguide. Moreover, the optical device includes a III-V semiconductor layer formed on top of the insulating layer causing an optical mode of an optical signal passing through the optical waveguide to overlap with the first semiconductor material region, the second semiconductor material region, the insulating layer, and the III-V semiconductor layer thereby resulting in a phase shift in the optical signal passing through the optical waveguide.

The invention relates to the technical field of crystal material preparation, in particular to a ternary layered selenide Ge3Sb4Se7 semiconductor material and a preparation method thereof. The preparation method of the ternary layered selenide Ge3Sb4Se7 semiconductor material comprises the following steps that S001, germanium powder, antimony powder and selenium powder with the molar ratio being 3: 4: 7 serve as raw materials, the temperature is increased to 900-950 DEG C under the vacuum condition, and heat preservation is conducted for 12-24 h at the temperature; s002, after heat preservation is finished, the temperature is reduced to 475-500 DEG C at the cooling rate of 1-5 DEG C / min, and heat preservation is conducted for 3-5 days at the temperature; and after heat preservation is finished, furnace cooling or quenching cooling is performed to reach the room temperature, and the layered ternary selenide single-phase material with the chemical formula being Ge3Sb4Se7 is obtained. The ternary layered selenide Ge3Sb4Se7 semiconductor material prepared by the invention is a single-phase material and has the characteristics of low thermal conductivity and low resistivity, so that the ternary layered selenide Ge3Sb4Se7 semiconductor material has application potential in the fields of thermoelectric devices, photoelectric detection and the like.

The invention belongs to the technical field of semiconductor chemical plating equipment, and particularly relates to a semiconductor automatic nickel-palladium-gold chemical plating process and chemical plating cleaning device.The chemical plating cleaning equipment comprises a cleaning pool, an ultrasonic cleaning area, a high-pressure cleaning area and a rinsing area are sequentially arranged in the cleaning pool side by side, and the three areas are completely separated through vertical partition plates; the partition plate is fixedly connected with the inner wall of the cleaning pool. In the process of cleaning the semiconductor material, the filtering assembly can filter water, so that water resources are recycled, water is saved, meanwhile, the filtered water is pumped back into the ultrasonic cleaning area, and the cleaning efficiency is improved. The backflow cleaning water can bring oil stains and floatable impurities floating on the liquid level into the collecting tank, so that the oil stains and the floatable impurities are independently collected, and meanwhile, the oil stains and the floatable impurities can be prevented from being adhered to the surface of a semiconductor material which is subsequently cleaned in a subsequent cleaning link.

The invention provides a high-porosity ceramic bond diamond micro-powder grinding tool and a preparation method and application thereof. The preparation method comprises the following steps: preparing ceramic bond diamond micro-powder composite powder by adopting a sol-gel method; the preparation method comprises the following steps: preparing porous agglomerated diamond microspheres by taking ceramic bond diamond micro-powder composite powder and an organic pore-forming agent as raw materials and adopting an atomization granulation method; the preparation method comprises the following steps: taking sodium alginate and calcium salt as raw materials, and preparing a calcium alginate water ball solution by adopting a multiple emulsion method and an atomization granulation method; the porous agglomerated diamond microspheres and the calcium alginate water balls are used as main raw materials, and a gel casting method is adopted for preparing the ceramic bond diamond micro-powder grinding tool. According to the diamond micro-powder grinding tool, the organic pore forming agent and the sodium alginate water balls are used as the pore forming agents, so that the particle size and proportion of pores in the prepared diamond micro-powder grinding tool can be accurately controlled, and the diamond micro-powder grinding tool has the characteristics of high porosity, good self-sharpening performance, low grinding resistance and the like and can be used for efficient and high-quality machining of semiconductor materials.

The invention provides a heat dissipation optimization method and system for a graphene semiconductor, and relates to the technical field of graphene semiconductors, and the method comprises the steps: determining a honeycomb structure based on a graphene semiconductor material which has a heat radiation coefficient identifier and a heat conduction coefficient identifier; configuring a plurality of heat dissipation flow lines corresponding to different heat dissipation modes; configuring a plurality of heat dissipation distribution maps corresponding to different heat dissipation modes; analyzing the influence of the band gap on the thermal radiation characteristic, and determining a first semiconductor characteristic influence index; analyzing the influence of the band gap on the heat conduction characteristic, and determining a second semiconductor characteristic influence index; and establishing a heat dissipation performance evaluation model, and performing heat dissipation iterative optimization in combination with the plurality of heat dissipation flow lines and the plurality of heat dissipation distribution maps. The technical problem that stable heat dissipation performance cannot be provided in diversified application scenes due to the fact that the heat dissipation design in the prior art is difficult to flexibly adapt to the requirements of different heat dissipation modes is solved.

The invention belongs to the field of semiconductor materials, and particularly relates to a method for improving film thickness uniformity of a lithium tantalate bonding wafer, which comprises the following steps: thinning the lithium tantalate bonding wafer; and according to the film thickness distribution of the thinned lithium tantalate bonding wafer, pressurizing the polished bonding wafer in different areas step by step, fitting a polishing rate model according to the film thickness measured in real time, and adjusting a pressurizing formula for polishing. Whether the final shutdown thickness is reasonable or not is judged through a polishing rate model, compensation is obtained, and then secondary polishing is conducted. The consistency of supplied materials before polishing is guaranteed through thinning processing, and a foundation is provided for improving the thickness uniformity of a polishing film; the thickness uniformity of the film in the bonding sheet is ensured by pressurizing step by step in different regions; and the polishing rate model ensures the film thickness uniformity between the bonding sheets.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a layer stack of an undoped semiconductor material layer and a source semiconductor layer. The undoped semiconductor material layer contacts a bottom end of the vertical semiconductor channel.

The embodiment of the invention relates to the technical field of semiconductor material processing, in particular to a processing method of a period-adjustable micro-nano oxidation periodic structure, which comprises the following steps: sequentially preparing a substrate, a metal layer and a semiconductor layer from bottom to top by using a physical deposition method to form a substrate-metal layer-semiconductor layer structure film from bottom to top; a light path composed of a femtosecond laser, an optical half-wave plate, a polarization beam splitter prism and a cylindrical lens is built; a femtosecond laser device is used for emitting femtosecond laser in a pulse string mode, after the femtosecond laser sequentially passes through an optical half-wave plate, a polarization beam splitter prism and a cylindrical lens, linear light spots are formed and focused on the surface of a structural film, and a micro-nano oxidation periodic structure is obtained; by changing the number of sub-pulses of the femtosecond laser, regulation and control of the period of the processed micro-nano oxidation periodic structure are realized. According to the method, efficient, economical, batch and accurate preparation of the micro-nano oxidation periodic structure is realized, and the method has a wide industrial application prospect.

Disclosed is a multi-angle image semantic segmentation method for cadmium zinc telluride chips, belonging to the field of image quality augmentation. Firstly, construction of an n+1 dataset is performed by using acquire CZT images, and then pixel-level and latent-level knowledge representation is performed through a Pixel Aggregation Network PAN and a Latent Aggregation Network LAN in a Progressive Complementary Knowledge Aggregation network PCKA, which ultimately improves the quality and speed of CZT image segmentation. The method is suitable for applications that require multi-angle image acquisition and semantic segmentation, such as semiconductor material segmentation.

Provided is a semiconductor device including a two-dimensional semiconductor material. The semiconductor device includes a first channel including a first two-dimensional material layer, a second channel being apart from the first channel and including a second two-dimensional material layer, a common gate electrode between the first channel and the second channel, a first source electrode and a first drain electrode in contact with the first channel, and a second source electrode and a second drain electrode in contact with the second channel, wherein one of the first channel and the second channel is an N-type channel, and the other is a P-type channel, and the first channel and the second channel are U-shaped.

The invention relates to the technical field of photoelectricity, and discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and an LED, the light-emitting diode epitaxial wafer comprises a substrate, and the substrate is sequentially provided with a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer; the multi-quantum well layer comprises a high-barrier multi-quantum well layer, a middle-barrier multi-quantum well layer, a low-barrier multi-quantum well layer and a low-barrier end multi-quantum well layer which are stacked in sequence. According to the light-emitting diode epitaxial wafer provided by the invention, the hole injection efficiency of the P-type semiconductor material can be improved, the phenomenon of insufficient hole concentration in the multi-quantum well layer is improved, and the matching degree of electron hole concentration in the multi-quantum well layer is improved, so that the radiation recombination efficiency in the multi-quantum well layer is improved, and the brightness and the lighting effect of an LED device are finally improved.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located on a semiconductor layer, a memory opening vertically extending through the alternating stack and the semiconductor layer, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, and a backside semiconductor source structure including a doped semiconductor material. The backside semiconductor source structure may be polycrystalline or single crystalline.

The invention discloses an intelligent cutting method and system for a semiconductor machined part based on path reconstruction, and relates to the technical field of semiconductor manufacturing processes, and the method comprises the steps: monitoring a machined part image, and extracting the edge contour and internal feature point information; fitting and constructing a three-dimensional contour model; planning a cutting path based on the model and outputting initial parameters; and cutting according to the initial parameters and iteratively optimizing the path according to the feedback information until the cutting task is completed. The technical problems that in the semiconductor device manufacturing process, a traditional cutting mode is difficult to cope with dynamic interference of semiconductor materials, fine modeling and protection on the edges and the interiors of the machined parts are lacked, cutting precision is insufficient, and the machined parts are prone to being damaged and scrapped are solved, fine modeling on the edges and the interiors of the machined parts is achieved, and the cutting precision is improved. The cutting path is optimized by combining dynamic interference real-time feedback, the cutting precision is improved, the damage rejection rate of machined parts is reduced, and the technical effects of high precision and high reliability of semiconductor device manufacturing are met.

A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and a bottom side. Active regions are disposed on the bottom side including a leveled surface facing the top side and a faceted backside surface opposite the leveled surface. The leveled surface includes two different semiconductor materials. A backside contact in contact with the faceted backside surface forms a wraparound contact to reduce contact resistance.

The invention provides a P-type AgBi Se2 thermoelectric material and a preparation method thereof, and relates to the technical field of thermoelectric materials. According to the P-type AgBi Se2 thermoelectric material and the preparation method thereof, the chemical composition of a compound of the P-type AgBi Se2-based thermoelectric material is AgBi (1-x) MnxSe2, 0lt, xlt; and 0.7, the compound is a P-type thermoelectric material. The AgBi Se2-based thermoelectric material with P-type conductivity in a room temperature region is prepared by doping Mn element at the position of B element in a displacement manner and combining melting with a spark plasma sintering technology, and Mn atoms replace B lattice feeding points in a solid solution doping manner to cause mass and stress field changes, so that the lattice heat conductivity is further reduced, and the room temperature Seebeck coefficient of AgB Se2 can be changed from negative to positive. The increase of the doping amount of the manganese element can cause the improvement of the carrier concentration, and the power factor is remarkably improved, so that the ZT value of the P-type thermoelectric material in the room temperature region is remarkably improved, and the room temperature thermoelectric performance of the material is further improved. The invention is used for the P-type AgBi Se2 semiconductor material and the preparation method thereof.

The embodiment of the invention provides an adapter plate and a preparation method thereof, a chip packaging structure and electronic equipment, relates to the technical field of semiconductors, and is used for improving the signal transmission efficiency in the adapter plate. The adapter plate comprises a substrate, a conductive structure arranged in the substrate, a first redistribution layer arranged on the substrate and a second redistribution layer arranged on the side, away from the first redistribution layer, of the substrate. The second redistribution layer is coupled to the first redistribution layer through the conductive structure. Wherein the material of the substrate comprises a semiconductor material, the first redistribution layer comprises a first metal wire, the second redistribution layer comprises a second metal wire, and the thickness of the first metal wire and / or the second metal wire is greater than 1 [mu] m.

The present application relates to the technical field of tungsten alloy materials, and in particular to a tungsten alloy wire, a preparation method therefor, and a use thereof in cutting of a semiconductor material. The tungsten alloy is composed of the following elements in percentage by mass: 0.4-1.1 wt% of L, 0.001-0.25 wt% of Z, and the balance of tungsten and inevitable impurities, wherein L is one or more than two of lanthanum, cerium, praseodymium, neodymium, gadolinium and erbium, and Z comprises oxygen and carbon. The wire diameter of the wire is 20-60 μm, the wire contains linear L or a compound of L along the wire axis direction, and the radial average width D of L or the compound of L is smaller than or equal to 5 nm. According to the present application, the linear L element is doped between tungsten base bodies, and the radial average width of L is controlled to be smaller than or equal to 5 nm, so that the wire has the tensile strength of 5000 MPa or above under the wire diameter of 20-60 μm, and the machining performance of the tungsten alloy wire is enhanced.

The invention provides an AlGaN film growth method and an AlGaN film, relates to the technical field of semiconductor material epitaxy, and aims to solve the technical problem of high defect density of an AlGaN film grown based on a silicon carbide substrate in the prior art. The method comprises the following steps: preparing a substrate, and cleaning the substrate; putting the cleaned substrate into high-temperature MOCVD (Metal Organic Chemical Vapor Deposition) equipment, and introducing a metal organic source for appointed time, so that metal atoms are adsorbed on the growth surface of the substrate; carrying out metal atom desorption treatment on the substrate adsorbed with the metal atoms for a specified time to obtain a target substrate; and growing an AlGaN film on the growth surface of the target substrate. According to the method, the step density of the surface of the substrate is reduced through metal atom adsorption and desorption processes, and an oxide layer on the surface is effectively removed, so that the crystal quality and the surface smoothness of the AlGaN film are improved.

An electrically inactive betavoltaic battery, an electrically active betavoltaic battery, and methods of making the same are provided. In implementations, a method of making an electrically active betavoltaic battery includes: providing an electrically inactive betavoltaic battery device having one or more diodes incorporating a semiconductor material layer having a stable non-radioactive isotope; and irradiating the electrically inactive betavoltaic battery device with thermal neutrons, thereby causing the conversion of at least a portion of the stable non-radioactive isotope to a radionuclide and creating the electrically active betavoltaic battery, wherein the semiconductor material layer acts as both an electron emitter and an electron absorber simultaneously.

The invention discloses a semiconductor film performance cooperative control method and system based on multi-parameter coupling, and belongs to the technical field of semiconductor material manufacturing, and the method specifically comprises the steps: determining a control parameter set containing plasma power density and other parameters, and building a multi-parameter coupling response model; generating sample points by using Latin hypercube sampling, quantifying a parameter interaction effect, and forming a dynamic weight matrix in combination with a graph model; monitoring data such as plasma emission spectrum intensity ratio in real time, comparing the data with a model predicted value, and correcting the model; a multi-objective optimization problem is constructed based on the correction model and the dynamic weight matrix, and optimal parameter configuration is solved by using a conjugate gradient method; alternately applying a high-frequency pulse and a relaxation stage according to the optimal configuration, and modulating the pulse frequency according to a Fibonacci sequence; and finally, based on the substrate temperature, planning a temperature rise path by using an S-shaped curve, superimposing cosine modulation, and introducing oscillation compensation gas to compensate the reactant concentration deviation, thereby realizing accurate optimization of the material preparation process.