2815 results about "Contact layer" patented technology

The invention is suitable for the technical field of solar cells, and provides a back contact solar cell, a cell assembly and a photovoltaic system, and the solar cell comprises a silicon substrate, the backlight surface of which is provided with a first region and a second region; the first passivation layer is arranged in the first region; the first doping layer is arranged on one surface, deviating from the silicon substrate, of the first passivation layer; the second passivation layer is arranged in the second region; the second doping layer is arranged on one surface, deviating from the silicon substrate, of the second passivation layer; at a preset position, an electric leakage contact layer is arranged in at least partial region between the first doping layer and the second doping layer, the electric leakage contact layer is connected with the first doping layer and the second doping layer, the thickness of the electric leakage contact layer is greater than that of the second passivation layer, and the ratio of the thickness of the electric leakage contact layer to the thickness of the second passivation layer is less than 4. According to the back contact solar cell, hot spot effect management and control can be achieved, normal power generation under a certain weak light condition is not affected, and hot spot effect management and control and power generation capacity of the back contact solar cell can be well balanced.

The present application relates to a solar cell, a method for manufacturing the same, a photovoltaic module and a photovoltaic system. The solar cell includes: a substrate (110), including a first surface (S1) and a second surface (S2) being opposite to each other, wherein the first surface (S1) has a first region (A) and a second region (B) adjacent to each other in a first direction; a passivating contact layer (120), located in the first region (A) of the first surface (S1); a polysilicon layer (130) located on at least a part of a surface of the passivating contact layer (120) away from the substrate (110); the passivating contact layer (120) including a first tunneling layer (121) and a first doped layer (122), the first tunneling layer (121) and the first doped layer (122) being sequentially stacked on the first region (A) of the first surface (S1) of the substrate (110) in a direction away from the second surface (S2); and a first passivation layer (140), located on a surface of the polysilicon layer (130) away from the passivating contact layer (120) and on the second region (B) of the first surface (S1).

The invention relates to the technical field of back contact cells, and particularly discloses a back contact cell and a preparation method thereof, and a photovoltaic system, the back contact cell comprises a silicon substrate, and the backlight surface of the silicon substrate is provided with a plurality of first areas and second areas which are alternately arranged; the first semiconductor composite layer is arranged in the first region and comprises a tunneling passivation layer and a first doping layer which are sequentially arranged in the direction away from the silicon substrate; the second semiconductor composite layer is at least partially arranged in the second area and comprises a passivation contact layer and a second doping layer which are sequentially arranged in the direction away from the silicon substrate, and the polarity of the second doping layer is opposite to that of the first doping layer; the composite TCO layer is arranged in at least partial areas of the sides, back to the silicon substrate, of the first doping layer and the second doping layer, the composite TCO layer comprises a first TCO layer and a second TCO layer which are sequentially arranged in the direction away from the silicon substrate, a plurality of holes are distributed in the first TCO layer, and the holes are provided with openings at least in the side, away from the second TCO layer, of the first TCO layer. According to the back contact battery structure, the back reflection effect on light can be effectively improved, the light utilization rate is improved, and then the battery conversion efficiency is improved.

The invention discloses a method for improving the heat dissipation performance of an AlGaInP red light Micro LED chip. The method comprises the following steps: S1, preparing an epitaxial structure: processing a substrate and a buffer layer, growing an etching barrier layer and an ohmic contact layer, and carrying out stacking epitaxy on a functional layer; s2, patterning the silicon-based substrate: preparing a dielectric layer and a metal structure; s3, diamond ohmic contact layer integration: processing a p-type conductive diamond film layer, and carrying out metal reflection and bonding; s4, removing the substrate and forming an n-type structure: stripping the substrate to be in n-type contact; s5, back-end process integration: preparing an electrode and an optical structure; according to the invention, the heat dissipation performance of the chip is significantly improved; the series resistance is reduced by 30%-50%; the resistivity of the p / n type diamond ohmic contact layer is reduced by 1-2 orders of magnitude compared with ITO; gaAs material light absorption and metal shading are avoided, and the red light transmittance is improved from 75% to more than 90% by combining with the micro lens array; the method is compatible with existing MOCVD, CVD and photoetching processes, large-scale production of wafers of 2-12 inches can be achieved, and the manufacturing cost is reduced.

A photo-detecting apparatus is provided. The photo-detecting apparatus includes a carrier conducting layer having a first surface; an absorption region is doped with a first dopant having a first conductivity type and a first peak doping concentration, wherein the carrier conducting layer is doped with a second dopant having a second conductivity type and a second peak doping concentration, wherein the carrier conducting layer comprises a material different from a material of the absorption region, wherein the carrier conducting layer is in contact with the absorption region to form at least one heterointerface, wherein a ratio between the first peak doping concentration of the absorption region and the second peak doping concentration of the carrier conducting layer is equal to or greater than 10; and a first electrode and a second electrode both formed over the first surface of the carrier conducting layer.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

A visual tactile sensor, a manipulator and a control method thereof, the visual tactile sensor comprising: a contact layer, at least a portion of which is transparent; when the contact layer is subjected to external force, at least one part of a plurality of markers in the marker array generates displacement and / or deformation; and the image acquisition unit is used for performing image acquisition on the marker array and performing image acquisition on the outside through the transparent part of the contact layer. The visual tactile sensor provided by the invention not only can capture the external visual information before operation to identify the operation object, but also can provide the tactile information in the operation process, so that the perception capability of an operation system is enhanced, and the operation success rate is improved.

The invention relates to the technical field of chips, in particular to a red light LED chip and a manufacturing method thereof. The red light LED chip comprises a back electrode, a Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type limiting layer, a P-type waveguide layer, a light emitting layer, an N-type semiconductor layer, a roughened spherical island, a passivation layer and a front electrode from bottom to top. The Au filling barrier layer is positioned in a chip cutting channel projection area and is coated by the dielectric film layer; the surface, protruding towards the mirror surface layer, of the ohmic contact layer is an arc-shaped surface. Pyramid suede surfaces are uniformly distributed on the surfaces of the roughened spherical islands. The manufacturing method is optimized, and the obtained red light LED chip is high in luminous efficiency, good in reliability and stable in overall performance.

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises an N + substrate; the first N-buffer layer is positioned on the N + substrate and is in contact with the first N-buffer layer; the N-drift layer is positioned on one side, far away from the N + substrate, of the first N-buffer layer; the P-well layer is embedded into the N-drift layer at one side, far away from the N + substrate, of the N-drift layer; the P + cathode is in contact with the P-well layer on one side, far away from the N + substrate, of the P-well layer; and the P-layer is located between the N-drift layer and the first N-buffer layer, and the P-layer is in contact with the first N-buffer layer.

The invention discloses a distributed feedback laser and a preparation method thereof, and relates to the field of lasers. The preparation method of the distributed feedback laser comprises the following steps: forming a lower limiting layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper limiting layer, a grating layer, a grating buried layer, a corrosion stop layer, an InP cladding, a barrier gradient layer, a contact layer and a sacrificial layer on a substrate, wherein the sacrificial layer comprises an InP layer and an InGaAs layer which are stacked in sequence; etching to form a ridge waveguide structure; forming an insulating layer; removing the insulating layer in a preset area on the ridge waveguide structure to expose the sacrificial layer; wherein the side wall of the InGaAs layer is completely exposed, and the side wall of the InP layer is partially exposed; and etching to remove the InGaAs layer and the InP layer to form an upper electrode layer and a lower electrode layer. According to the invention, the reliability and the electro-optical conversion efficiency of the distributed feedback laser can be improved.

The invention provides a medium-wave infrared detection chip and system, the chip is composed of a plurality of detection units arranged in the same plane, each detection unit is composed of a substrate, a buffer layer, a lower contact layer, an absorption layer, a barrier layer and an upper contact layer in sequence, the chip is arranged based on an nBp type structure, the buffer layer, the lower contact layer, the absorption layer, the barrier layer and the upper contact layer are all of a multi-period stacked superlattice structure, the thickness, the number of layers and the doping concentration of the InAs doped layers and the GaSb doped layers which are stacked in each period are controlled, dark current suppression in the mid-infrared detection process is achieved, and the quantum efficiency is effectively improved.

A solar cell comprises a substrate, a first passivated contact layer and a second passivated contact layer, a first passivation film layer and a first dielectric layer, and a first electrode. The first passivation film layer is stacked on the first passivated contact layer, in an insulating isolation groove and on the second passivated contact layer; a first through groove is formed in an area, which corresponds to each first polycrystalline silicon doped conductive layer, of the first passivation film layer; one end of the first electrode passes through the first through groove to be in ohmic contact with the first passivated contact layer; and the first dielectric layer covers the first passivation film layer and covers first areas on the first passivated contact layer, wherein the first areas are areas that are located in a surface, which is exposed from the first through groove, of the first passivated contact layer, and are located between side walls of the first through groove and the first electrode.

The invention relates to the technical field of chips, in particular to a reversed-polarity red light emitting LED chip and a manufacturing method thereof. The reversed-polarity red light emitting LED chip comprises a graphite substrate, a graphene bonding layer, an Ag reflector, an AZO conductive thin film layer, an MgF dielectric film layer, a GaP window layer, a P-type semiconductor layer, a light emitting layer, an N-type epitaxial limiting layer, an N-type current expansion layer, a coarsening layer, a passivation layer, a GaAs contact layer and an N electrode from bottom to top. According to the LED chip and the manufacturing method thereof, reasonable design is carried out on the chip manufacturing process, a mirror surface layer, a bonding layer, back gold and other metals do not need to be evaporated for multiple times, the chip manufacturing process is shortened, the use of chip gold can be greatly reduced, and the obtained LED chip is high in brightness, good in reliability, long in service life and low in cost.

The invention relates to the technical field of semiconductors, and discloses an edge-emitting semiconductor laser and a preparation method thereof, and the preparation method comprises the steps: forming a current injection region and a passivation layer at the side part of the current injection region on the surface of one side, opposite to an upper limiting layer, of a P-surface contact layer of a laser wafer; the laser wafer is divided into a plurality of laser chips in the vertical direction through a plurality of first cleavage channels and a plurality of second cleavage channels; forming a first P-type metal layer on the surface of the laser chip, the surface of the first cleavage channel and the surface of the first region of the second cleavage channel; forming a second P-type metal layer on the surface of one side of the first P-type metal layer of the laser chip through an electroplating process; the first P-type metal layer in the first region is used for communicating the surfaces of the plurality of laser chips; the laser wafer is cleaved into a plurality of edge-emitting semiconductor lasers. Compared with the prior art, the reliability and the yield of the edge-emitting high-power laser can be improved, and the cost of a preparation process is reduced.

The embodiment of the invention relates to the photovoltaic field, and provides a back contact solar cell and a preparation method thereof, and a photovoltaic module, and the back contact solar cell comprises a substrate, and first doped regions and second doped regions which are arranged in a staggered manner; the first passivation contact layer is positioned in the first doped region; the second passivation contact layer is positioned in the second doped region; doped oxide layers, each doped oxide layer comprising a first portion and a second portion, the first portion being located on the surface of the first passivation contact layer; the second part is located on the second doped region; the connecting layer is located in a partial region of the first part, further surrounds a partial region of the second part and is electrically connected with the second passivation contact layer, and the connecting layer is located on the side face of the first passivation contact layer and is electrically connected with the first passivation contact layer. The back contact solar cell provided by the embodiment of the invention at least can improve the hot spot effect and increase the photoelectric conversion efficiency.

The invention relates to a deep ultraviolet light-emitting diode with a light scattering structure and a preparation method of the deep ultraviolet light-emitting diode. The light-emitting diode comprises a substrate layer, a buffer layer and an N-type semiconductor transmission layer which are sequentially arranged along the epitaxial growth direction of a chip, wherein the shape of the N-type semiconductor transmission layer is divided into an upper part and a lower part, and the multi-quantum well active layer, the P-type semiconductor transmission layer and the P-GaN contact layer sequentially cover the surface of the upper part of the N-type semiconductor transmission layer; a horizontal light scattering structure layer and a vertical light scattering structure are respectively distributed in the upper part and the lower part of the N-type semiconductor transmission layer. According to the invention, the scattering effect of light in the N-type semiconductor transmission layer is improved, the optical waveguide effect of the N-type semiconductor transmission layer is broken, the light is effectively prevented from spreading to the metal n electrode, meanwhile, the light can be scattered, the bottom light emitting efficiency of the deep ultraviolet LED is improved, and the light extraction efficiency is improved.

The invention relates to the technical field of laser chips, in particular to a wide-wavelength electro-absorption modulated laser chip and a preparation method and application thereof. According to the wide-wavelength electro-absorption modulated laser chip provided by the invention, a plurality of specific areas are divided on a substrate, a first modulator layer, a first front grating layer and a second modulator layer are sequentially arranged on the areas, and phosphorus ions are injected into the first modulator layer and the second modulator layer. The key sampling grating is arranged in the first front grating layer, the rear grating layer and the second front grating layer in an electron beam direct writing mode. A cladding layer and an electric contact layer are sequentially stacked above all the functional layers, an electric isolation trench is formed between the functional layers through etching, the uppermost layer is a P-surface electrode, and an N-surface electrode is arranged below the substrate. According to the chip, the same post-sampling grating reflection area is utilized, double-end modulation is integrated through the quantum well hybrid technology, the effects of double-end light emitting and rate and wavelength tuning performance doubling of the same integrated chip are achieved, and the power consumption of the integrated chip is greatly reduced.

The invention provides a patterned photonic crystal laser and a preparation method thereof, the laser comprises a substrate, and a first mask layer, a photonic crystal layer and a second mask layer which are sequentially deposited on the substrate, a light emitting area is etched in the central area of the second mask layer, and transparent conductive layers are deposited on the surface of the second mask layer and the light emitting area; a p-annular electrode is arranged on the surface of the transparent conductive layer on the second mask layer, and an n-annular electrode is arranged below the substrate; the photonic crystal layer is composed of a nanorod array and a polymer filled in gaps of nanorods; holes distributed in a patterned array are etched in the surface of the first mask layer, and nanorods are epitaxially grown in hole areas; the nanorod is formed by sequentially depositing a substrate contact layer, a first waveguide layer, a multi-quantum well layer, a second waveguide layer, a coating layer and a component gradient layer. According to the invention, through collaborative design optimization of all the layers, emission of laser with specific wavelength and preparation of a laser emitting laser with single longitudinal mode, narrow linewidth and stable wavelength are realized.

The present application discloses a cell contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The cell contact structure includes a contact layer positioned on a substrate and enclosed by a plurality of bit line structures and a plurality of partition layers; and a liner layer positioned between the contact layer and the substrate, between the contact layer and the plurality of bit line structures, and between the contact layer and the plurality of partition layers. A top surface of the contact layer and a top surface of the liner layer are substantially coplanar. The liner layer includes doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium. The contact layer includes tungsten, titanium, or titanium nitride.

Disclosed herein are embodiments of a wound treatment apparatus with electronic components integrated within a wound dressing. In some embodiments, a wound dressing apparatus can comprise a wound dressing. The wound dressing can comprise an absorbent material, an electronics unit comprising a negative pressure source, the electronics unit integrated within the wound dressing and at least partially encapsulated by a flexible film. The flexible film can comprise a window or aperture configured to permit fluid communication between the absorbent material and the negative pressure source. In some embodiments, a wound dressing apparatus can comprise a wound contact layer, an absorbent layer over the wound contact layer, the absorbent layer comprising one or more apertures, a cover layer configured to cover and form a seal over the wound contact layer and the absorbent layer, and an electronics assembly comprising a negative pressure source. A portion of the cover layer overlying the one or more apertures in the absorbent layer can be configured to be compressed within the aperture in the absorbent layer when negative pressure is applied to the wound dressing apparatus. The compressed cover layer can indicate a level of negative pressure below the cover layer. In some embodiments, the wound dressing apparatus can comprise an indicator material layer and a cover layer configured to cover and form a seal over the wound contact layer and the indicator material layer. The indicator material layer can be configured to protrude relative to a surrounding surface of an upper surface of the wound dressing apparatus when negative pressure is applied to the wound dressing apparatus and the protruding indicator material layer indicates a level of negative pressure below the cover layer.

The invention discloses a low-power-consumption photonic integrated device preparation method and a corresponding device, and relates to the technical field of semiconductor optoelectronic integrated devices.The device comprises a substrate, a cantilever beam type grating layer, two gain layers, two modulator layers, a wrapping layer and an electric contact layer, the two gain layers and the two modulator layers are symmetrically distributed, and the wrapping layer and the electric contact layer form a shallow ridge waveguide structure. The two symmetrically-distributed gain layers and the middle cantilever beam type grating layer jointly form a double-end resonant cavity structure, the structure shares a unified grating and a thermal tuning platform to achieve continuous, synchronous and high-precision control over cavity mode wavelengths, and balanced modulation and phase synchronization of double-end output are achieved in cooperation with the symmetrically-integrated high-speed modulator layers on the two sides. According to the technical scheme, the gain layer, the grating layer and the modulator layer are symmetrically integrated on the same substrate, the alignment error of a multi-cavity structure is reduced, synchronous scanning, low drift and strong anti-interference high-quality laser output can be obtained, meanwhile, efficient thermal tuning is conducted through the cantilever beam type grating layer, and power consumption is remarkably reduced.

The invention relates to a photoelectric detector, particularly provides a semiconductor photoelectric detector chip and a preparation method, and aims to solve the problem of high alignment difficulty of a readout circuit chip and a detector chip. The preparation method of the semiconductor photoelectric detector chip provided by the invention comprises the following steps: providing a detector wafer which comprises a detector substrate, a first contact layer and a second contact layer; providing a readout circuit wafer having a third electrode and a fourth electrode; forming a bonding layer to bond the detector wafer and the readout circuit wafer; pixel table boards arranged in an array are formed on the detector wafer, a first isolation groove is formed between every two adjacent pixel table boards in the same array, and the first isolation grooves penetrate through the detector wafer and the bonding layer; and forming an electrode, so that the first contact layer is electrically connected with the fourth electrode and / or the second contact layer is electrically connected with the third electrode. The detector wafer and the readout circuit wafer are bonded first and then form the pixel mesa array, so that the bonding difficulty of the detector wafer and the readout circuit wafer can be greatly reduced.

The invention discloses an annealing temperature control method based on a differentiated ohmic contact material, and aims to solve the problems that the annealing temperature of an N-surface Au / Ge ohmic contact layer of an existing AlGaInP-based red light Micro-LED is not accurately monitored, a temperature field is not uniform and is difficult to detect, and abnormal response lags, the method comprises seven steps of processes (two times of patterning, two times of metal coating, two times of photoresist removal, annealing and observation), and the annealing temperature of the N-surface Au / Ge ohmic contact layer of the existing AlGaInP-based red light Micro-LED is controlled. Preparing a first Au / Ge ohmic contact layer (for function) and a second Au / Ge / Ni ohmic contact layer (for detection) on the N surface of the wafer; by means of the characteristic that Ni inhibits Au / Ge agglomeration, the two-layer agglomeration state difference is observed through an optical microscope, and the temperature is judged (in the normal state, the former agglomerates, and the latter does not agglomerate); the method is convenient in detection, supports batch detection, can find temperature abnormity in real time, improves the process stability, and is suitable for industrial mass production.

The invention belongs to the technical field of micromachining, and discloses a flexible micro needle tip array electrode based on composite multi-layer metal and a preparation method of the flexible micro needle tip array electrode. The flexible micro needle tip array electrode comprises a flexible substrate and a silicon micro needle tip array structure arranged on the flexible substrate, each silicon micro needle tip in the silicon micro needle tip array structure is provided with composite multilayer metal capable of conducting electricity and conducting signals, and the composite multilayer metal sequentially comprises a seed layer, a structural layer, an adhesion layer and a contact layer from inside to outside; the material of the seed layer is Cr, Ti, Ni, Mo, Ta, W, Fe, Cu, Au, Ag or Pt, the material of the structural layer is Cu, Ag or Au, the material of the adhesion layer is Cr, Ni, Ti, Mo, Ta or W, and the material of the contact layer is Au, Ag or AgCl. According to the invention, the composite multi-layer metal is used as the conductive layer of the flexible micro-needle-point array electrode, so that the contact impedance of the flexible micro-needle-point array electrode is reduced.

The invention relates to the technical field of solar cells, in particular to a laminated solar cell and a photovoltaic module. In the embodiment of the invention, the area of the orthographic projection of a first passivation contact layer on a reference surface is configured to be smaller than the area of the overlapping projection of a top cell unit and a bottom cell unit, and a first passivation layer is arranged on a first sub-surface exposed by the first passivation contact layer and a first target surface of the first passivation contact layer. The opposite side surfaces of the composite layer and the first passivation layer are in contact with each other, so that the efficiency of the battery can be improved.

A memory device includes source-level material layers containing a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers located over the source-level material layers, a memory opening vertically extending through the alternating stack and into an upper portion of the source-level material layers, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel. The source contact layer includes a horizontally-extending portion and a vertically-extending portion having a greater vertical extent than the horizontally-extending portion, having an inner cylindrical sidewall contacting a bottom portion of the vertical semiconductor channel, and contacting a bottommost insulating layer within the alternating stack.

The invention relates to the technical field of chip preparation, and provides a chip based on an annular photonic crystal and a preparation method thereof. The preparation method comprises the following steps: growing a nucleating layer on a substrate; growing a superlattice structure on one side, away from the substrate, of the nucleating layer; sequentially growing an n-type coating layer, an n-type waveguide layer, a quantum well and a p-type electron blocking layer on one side, deviating from the nucleating layer, of the superlattice structure; etching a plurality of annular cavities on the p-type electron barrier layer to form an annular photonic crystal; growing a p-type extension contact layer on one side, deviating from the quantum well, of the p-type electron blocking layer; and carrying out in-situ annealing treatment. According to the preparation method, the directivity of the photonic band gap can be effectively adjusted, uniform light waves in all directions on the side face can be formed, so that leakage of laser from a non-light-emitting area on the side face is restrained, the light emitting efficiency is improved, the annular photonic crystals are periodically distributed, and the light beam quality is effectively guaranteed.

The invention provides an EML laser and a preparation method of an air bridge, belongs to the technical field of optical communication lasers, and is used for solving the problem that the stray capacitance of connecting metal between a waveguide electrode and a PAD electrode of the EML laser is too large. The preparation method of the air bridge process of the EML comprises the following steps: growing a mask layer on the surface of an epitaxial InP wafer, photoetching to form a ridge waveguide pattern, etching the mask layer by adopting ICP (Inductively Coupled Plasma), and removing photoresist; etching the ohmic contact layer by adopting ICP (Inductively Coupled Plasma) and removing the mask layer; gluing and photoetching the surface of the wafer to form a pier pattern; adopting ICPCVD to grow a dielectric film at low temperature; gluing and photoetching the surface of the wafer to form a dielectric film bridge pattern; carrying out ICP etching on the dielectric film and removing the bridge and pier photoresist to form a dielectric film bridge; and performing wet etching on the InP epitaxial layer to the etching stop layer. According to the method, the dielectric film bridge is built at the connecting metal between the waveguide electrode and the PAD electrode, the low dielectric constant characteristic of air is utilized, the distance between the metal and the quantum well is greatly increased, the stray capacitance of the EML is reduced, and the bandwidth is improved.

The invention provides a neck-hanging type water negative ion device convenient for negative ion absorption, which comprises a neck-hanging type shell, a negative ion water mist generating device, an ionization needle device, a positive voltage module and a conductive contact layer, and is characterized in that the negative ion water mist generating device, the ionization needle device and the positive voltage module are mounted in the neck-hanging type shell and are suitable for being matched to generate water negative ions; the conductive contact layer is arranged on the surface of the neck-hanging type shell and is suitable for being in contact with the neck of the human body, and the positive voltage module is electrically connected with the conductive contact layer and is suitable for forming a potential difference between the conductive contact layer and negative ion charges in air, so that the negative ion charges are attracted to flow to the human body, and the human body can absorb negative ions conveniently.

The invention relates to the technical field of semiconductors, in particular to a source heterojunction contact semiconductor structure and device and a manufacturing method, the semiconductor structure comprises a gate structure, a body region structure, a source structure and a drain structure, and the source structure comprises a polycrystalline silicon source contact layer; the semiconductor structure comprises a body region structure and a polycrystalline silicon source contact layer, the body region structure is surrounded by the gate structure, a source contact region is arranged in the body region structure, the polycrystalline silicon source contact layer is in contact with the source structure through the source contact region so as to form a heterojunction diode with the source structure, and the heterojunction diode is a freewheeling diode of the semiconductor structure. The drain electrode structure is located on one side, back to the gate electrode structure, of the body region structure; the semiconductor structure can be a SiC MOSFET structure, reverse conduction voltage drop during follow current of the SiC MOSFET can be greatly reduced, and conduction loss and loss caused during switching are reduced.