2049 results about "Ohmic contact" patented technology

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

Lateral III-N devices such as AlGaN / GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N buffer layer, a III-N channel layer and a III-N barrier layer where a compositional difference induces a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel and the second portion extends over a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage which is greater than the drain-to-substrate pinch-off voltage, and the 2DEG channel is fully depleted of charge below the second portion of the drain electrode when the III-N device is biased at or above the maximum rated drain-to-source operating voltage.

The invention provides a heterojunction solar cell and a preparation method thereof, and the method comprises the steps: sequentially arranging oxygen-containing crystalline silicon layers of a first conduction type on the surface, far away from a substrate, of a first passivation layer through employing a set deposition technology, wherein the oxygen atom doping concentration of the oxygen-containing crystalline silicon layers is gradually increased in the direction away from the substrate; on one hand, light oxygen doping is arranged at the interface of the first passivation layer, so that the dark attenuation phenomenon of a heterojunction cell is reduced, and the power off-shift problem of a photovoltaic module is further reduced; on the other hand, heavy oxygen doping is arranged on one side far away from the first passivation layer, so that the optical band gap and the short-circuit current of the crystalline silicon layer on the light receiving surface are effectively improved; and finally, oxygen-free doping is arranged at an interface adjacent to the transparent conducting layer, so that ohmic contact between the oxygen-containing crystal silicon layer and the transparent conducting layer is effectively reduced. Therefore, the comprehensive electrical performance of the heterojunction solar cell is effectively ensured and improved.

The invention discloses an enhanced HEMT (High Electron Mobility Transistor) device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a cap layer, wherein the buffer layer, the channel layer, the barrier layer and the cap layer are sequentially positioned on the substrate layer; the passivation layer is located on the side wall of the cap layer and located on the upper surface of the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the drain electrode and the source electrode respectively penetrate through the passivation layer and are positioned on the upper surface of the barrier layer; the grid electrode is located on the upper surface of the cap layer, and the contact interface of the grid electrode and the cap layer at least comprises ohmic contact and Schottky contact. Compared with the prior art, the hybrid gate HEMT device is formed by replacing a part of Schottky gate metal with ohmic gate metal in the gate structure of the HEMT device, so that the reliability and the stability of the threshold voltage of the gate of the p-GaN gate HEMT device can be effectively improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

The present invention relates to a solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises: an N-type substrate; a patterned first passivation contact structure, which is arranged on a light-receiving surface of the substrate, and comprises a first dielectric layer having a thickness less than or equal to 2 nm and an N-type first doped polysilicon layer; a second passivation contact structure, which is arranged on the entire backlight surface of the substrate, and comprises a second dielectric layer having a thickness greater than 2 nm and having a through hole and a P-type second doped polysilicon layer having a doping concentration of 5×1018 to 3×1020 atom / cm3; a first functional layer on the substrate and the first passivation contact structure; a second functional layer on the second doped polysilicon layer; a first electrode, which penetrates the first functional layer to make ohmic contact with the first doped polysilicon layer; and a second electrode, which penetrates the second functional layer to make ohmic contact with the second doped polysilicon layer.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with high heat dissipation performance, which comprises a plurality of MOS cells arranged in parallel, and is characterized in that each MOS cell comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate oxide layer covering the surface of the metal source electrode, performing ion implantation in the semiconductor epitaxial layer to form an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer and a P well layer; source electrode doping layers are arranged on the two sides of a single MOS cell, the source electrode doping layers are in ohmic contact with the metal source electrodes, and the source electrode doping layers are made of gallium arsenide or gallium nitride or nichrome. According to the invention, the source electrode doping layer with the sinking design is arranged above the MOS cell, so that the N well layer can be in direct contact with the metal source electrode, and the N well layer can be in indirect contact with the metal source electrode through the source electrode doping layer, thereby reducing the ohmic resistance of the N well layer and the metal source electrode, and reducing the heating at the contact position.

The invention discloses a solar cell, a photovoltaic module and a preparation method thereof. The solar cell may include: a silicon substrate having a textured first main surface; an emitter, a passivation layer and a front antireflection layer are laminated on the first main surface from inside to outside; a first silver-aluminum gate line arranged on the front antireflection layer, wherein the first silver-aluminum gate line is in ohmic contact with the emitter; in the textured structure, a metalized area and a non-metalized area corresponding to the first silver-aluminum gate line meet at least one of the following conditions: a first projection coefficient of the metalized area is greater than a second projection coefficient of the non-metalized area except the metalized area; the roughness of the metalized region is greater than that of the non-metalized region; the top of the suede area corresponding to the metalized area is of a plane structure or a cambered surface structure, and the top of the suede area corresponding to the non-metalized area is of a pointed structure; the metalized region is of a planar structure, and the non-metalized region is of a pyramid structure. The structure can improve the reliability of the solar cell.

The utility model relates to the technical field of solar cells, and discloses a solar cell which is provided with a grid line area and a non-grid line area. The solar cell includes: a silicon substrate; the backlight surface is provided with a first backlight area and a second backlight area, the first backlight area corresponds to the grid line area in position, and the second backlight area corresponds to the non-grid line area in position; the patterned passivation contact structure comprises a dielectric layer and a doped polycrystalline silicon layer, the doped polycrystalline silicon layer is provided with a first surface deviating from one side of the dielectric layer, and a patterned area of the passivation contact structure corresponds to the grid line area in position; the first functional layer is arranged on the surface of the silicon substrate and the doped polycrystalline silicon layer corresponding to the second backlight area; the first electrode penetrates through the first functional layer and is in ohmic contact with the doped polycrystalline silicon layer; the flatness of the first surface is higher than that of the second backlight area. The solar cell can reduce the problem of film explosion of the first passivation layer and reduce the contact resistance between the doped polycrystalline silicon layer and the first electrode.

The invention discloses a diamond MOSFET device compatible with a CMOS ohmic contact process and a preparation method of the diamond MOSFET device. The preparation method comprises the steps that S1, a diamond substrate is selected, and an intrinsic diamond layer is grown on the diamond substrate in a homoepitaxial mode; s2, preparing a mask, and forming a boron-doped diamond layer in a source region and a drain region on the intrinsic diamond layer through boron ion implantation; s3, depositing a layer of Si film and a layer of Ti film on the surface of the sample; s4, performing two-step annealing on the sample to obtain ohmic contact formed by the boron-doped diamond layer, the boron-doped silicon layer and the titanium silicide layer; s5, removing the mask and the thin film above the mask; s6, preparing a terminal diamond surface layer; s7, preparing a passivation layer and windowing to form a source window and a drain window; and S8, preparing a gate electrode. According to the method, high-quality ohmic contact can be formed on the diamond through the gold-free process, the gold ion pollution risk is thoroughly avoided, and CMOS process compatibility is achieved.

The invention discloses a microstructure silicon carbide ultraviolet photoelectric detector with high quantum efficiency and a preparation method thereof, and belongs to the technical field of ultraviolet photoelectric detection. The detector adopts a bottom-to-top structural design and comprises a silicon carbide highly-doped n + type substrate, an n type buffer layer, a low-doped n-type absorption layer, a low-doped p-type absorption layer (containing a microstructure), an annular highly-doped p + type ohmic contact layer and a passivation isolation layer. Reverse bias voltage is applied to the p + type ohmic contact electrode to form a depletion electric field, and the microstructure promotes the p-i-n structure electric fields to be mutually connected and coupled, so that the photon-generated carrier depletion efficiency is improved, and the responsivity of the device and the external quantum efficiency are enhanced. And meanwhile, the microstructure enables a short-wave ultraviolet signal to directly penetrate through the p-type absorption layer to enter the internal absorption layer, so that photon-generated carrier recombination caused by surface defects of the p + type ohmic contact layer is avoided, the collection efficiency of photon-generated carriers is improved, and ultraviolet full-band detection is realized.

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

The invention discloses an annealing temperature control method based on a differentiated ohmic contact material, and aims to solve the problems that the annealing temperature of an N-surface Au / Ge ohmic contact layer of an existing AlGaInP-based red light Micro-LED is not accurately monitored, a temperature field is not uniform and is difficult to detect, and abnormal response lags, the method comprises seven steps of processes (two times of patterning, two times of metal coating, two times of photoresist removal, annealing and observation), and the annealing temperature of the N-surface Au / Ge ohmic contact layer of the existing AlGaInP-based red light Micro-LED is controlled. Preparing a first Au / Ge ohmic contact layer (for function) and a second Au / Ge / Ni ohmic contact layer (for detection) on the N surface of the wafer; by means of the characteristic that Ni inhibits Au / Ge agglomeration, the two-layer agglomeration state difference is observed through an optical microscope, and the temperature is judged (in the normal state, the former agglomerates, and the latter does not agglomerate); the method is convenient in detection, supports batch detection, can find temperature abnormity in real time, improves the process stability, and is suitable for industrial mass production.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention provides stacked gate laser secondary injection enhanced repair equipment and a repair method. The stacked gate laser secondary injection enhanced repair equipment comprises a conveying belt; the feeding assembly comprises a first feeding mechanism and a second feeding mechanism which can be used in a power-off state; a first dual-laser assembly; a second dual-laser assembly; a carrying assembly; a turntable; the feeding assembly, the rotary table and the discharging assembly are sequentially arranged, and the carrying assembly is located on one side of the rotary table so that position switching of products between the conveying belt and the rotary table can be achieved. The device can be suitable for battery pieces of different sizes, the battery pieces of different sizes are positioned for four times through laser, the acting contact time of the laser and the battery pieces is prolonged, ohmic contact is better, current is increased, silver-silicon microcrystals are promoted to be formed, sintering is sufficient, and the filling factor of the battery pieces is improved.

Provided in the present application are a solar cell, a solar cell module, and a manufacturing method for a solar cell, so as to guarantee good ohmic contact between a first electrode and a passivation layer, improve the transmission efficiency of carriers, and weaken parasitic absorption of light, thereby ensuring the cell efficiency of TOPCon cells. The solar cell comprises a semiconductor substrate, an ultrathin dielectric layer, a passivation layer, a first electrode and a metal crystal, wherein the semiconductor substrate has a light receiving face and a backlight face which are opposite each other, the ultrathin dielectric layer is located on at least one of the backlight face and the light receiving face of the semiconductor substrate, the passivation layer is located on the ultrathin dielectric layer, the first electrode is located on the passivation layer, and the metal crystal is located in the passivation layer; and the metal crystal comprises a first metal crystal, one end face of the first metal crystal abuts against the ultrathin dielectric layer, and the other end face of the first metal crystal is connected to the first electrode.

The invention discloses a butt-joint epitaxial growth ridge waveguide laser chip and a manufacturing method thereof, and belongs to the technical field of lasers, and the manufacturing method comprises the following steps: manufacturing a ridge waveguide structure on an epitaxial wafer subjected to butt-joint growth, coating a layer of photoresist adhesive and two layers of photoresist on the ridge waveguide structure, forming a window at a convex ridge of the overlay ridge waveguide structure, and forming the butt-joint epitaxial growth ridge waveguide laser chip. The window covers an area above the passive area and a part of the active area, exposing and developing the epitaxial wafer in the window, removing a part of photoresist, etching and removing the residual photoresist in the window to expose the ohmic contact layer, corroding and removing the ohmic contact layer in the window, and removing all the photoresist on the surface of the epitaxial wafer. The length of the ohmic contact layer is controlled through double-layer adhesive photoetching and wet etching, and the ohmic contact layer above the active region is further etched, so that diffusion of current to the passive waveguide direction is effectively inhibited, the threshold current of the chip is reduced, the heating value of the passive waveguide region is reduced, and the reliability of the chip is improved.

The invention relates to a high-speed low-dark-current three-step structure avalanche photodetector and a preparation method thereof, and belongs to the technical field of semiconductor devices. Comprising an intrinsic InP substrate, an N-type InAlAs ohmic contact layer, an intrinsic InAlAs transition layer, an N-type InAlAs charge layer, an intrinsic InAlAs multiplication layer, a P-type InAlAs charge layer, an intrinsic InAlGaAs transition layer, an intrinsic InGaAs absorption layer, a gradient-doped P-type InGaAs absorption layer and a P-type InAlAs ohmic contact layer which are stacked from bottom to top. The intrinsic InGaAs absorption layer 8 and the N-type InAlAs ohmic contact layer 2 are both of a step structure so as to form a three-stage step structure of the photoelectric detector. According to the invention, through growing the SiNx antireflection film with the refractive index of 1.85 and the thickness of 210 nm on the light incident surface, the reflectivity of incident light can be less than 1%. For an optical signal with the wavelength of 1550 nm, the single light absorption quantum efficiency can reach 0.45.

The invention relates to a solar cell and a preparation method and application thereof. The solar cell comprises a cell main body, a silver seed layer and a metal transmission layer, the silver seed layer has a patterned structure and is arranged on the cell main body, and the silver seed layer and the doped silicon layer in the cell main body form ohmic contact; the material of the metal transmission layer comprises at least one of copper and aluminum; the metal transmission layer is arranged on the battery main body and covers the silver seed layer, and the width of the metal transmission layer is greater than that of the silver seed layer; and the metal transmission layer and the silver seed layer form metal contact. The solar cell provided by the invention can give consideration to relatively low electrode preparation cost and relatively high conversion efficiency.

The invention relates to the technical field of electronic paste, in particular to copper electrode paste for an NTC thermistor and a preparation method and application of the copper electrode paste. A copper electrode slurry for an NTC thermistor comprises copper powder, an inorganic glass binder, an organic carrier and a dispersant, the inorganic glass binder comprises CuO and NiO, and the organic carrier comprises a polymer thickener. The copper electrode slurry can be coated on the surface of an NTC thermistor ceramic substrate through a silk-screen printing method, can be used as a metallized conductive layer after being sintered in nitrogen, is used for temperature measurement, temperature compensation, temperature control components and the like, and is wide in application. The copper electrode slurry for the NTC thermistor provided by the invention can be sintered in nitrogen at 550-650 DEG C, and has the advantages of wide sintering interval, good sintering appearance, excellent welding performance and strong adhesive force. After sintering, the ohmic contact is good, so that the prepared NTC thermistor can truly reflect the resistance value of a substrate, and the phenomenon of ion migration is avoided.

The invention discloses an in-situ TEM (Transmission Electron Microscope) device sample preparation method based on a suspended thinning and parallel carrying technology, which can be used for preparing in-situ TEM samples of semiconductor two-end devices and three-end devices, and mainly solves the problems of unstable ohm contact, nonuniform thinning, low success rate and high time cost in the prior art. According to the invention, an FIB sample preparation technology is adopted, and stable and reliable ohmic contact between a sample electrode and an MEMS chip electrode is ensured through specific-angle sample extraction, suspended thinning, parallel carrying, circuit breaking treatment and an accurate electrode welding process. According to the sample prepared by the invention, the failure state of a device can be observed in real time under a transmission electron microscope, the sample has the advantages of high sample preparation success rate, good repeatability, stable electrical parameters and wide applicable chip variety, and the reliability and repeatability of in-situ TEM test data are remarkably improved.

The invention relates to the technical field of semiconductors, in particular to a columnar array enhanced photoelectric detector and a preparation method thereof, and the method comprises the following steps: depositing a continuous GaN layer on a substrate through an epitaxial growth method; forming a columnar array structure pattern and an electrode region on the GaN layer through a photoetching process, and removing a part of the GaN layer through an etching process to form an exposed columnar GaN array; depositing a metal electrode layer on two sides of the GaN array, and forming ohmic contact or Schottky contact with the GaN layer to obtain a photoelectric detector; the photoelectric detector is connected with a peripheral circuit to form a complete columnar array enhanced photoelectric detector system, the GaN layer of the columnar array structure is adopted, multiple times of reflection and interference on incident light are achieved, and therefore the detection efficiency and the response speed of the photoelectric detector are improved.

The invention discloses a Ga2O3 heterojunction beta irradiation battery with a multi-groove radioactive source, relates to the technical field of microelectronics, and solves the problems of low energy utilization rate and low energy conversion efficiency of a Ga2O3 nuclear battery radioactive source in the prior art. The battery comprises a filling type multi-groove radioactive source; the Ga2O3 heterojunction diode unit sequentially comprises a P-type ohmic contact electrode, a P-type NiO ion implantation region, an N-type Ga2O3 low-doped epitaxial layer, an N-type Ga2O3 high-doped substrate and an N-type ohmic contact electrode from top to bottom; a multi-T-type radioactive isotope source layer in the filling type multi-groove radioactive source is arranged above the P-type NiO ion implantation region and forms radiation energy coupling with the Ga2O3 heterojunction diode unit; the groove type structure is filled with the radioactive source, the energy deposition of the radioactive source entering the semiconductor conversion device is greatly increased, and the energy conversion efficiency of the Ga2O3 beta irradiation battery is improved.

The invention provides a Micro LED display device and a preparation method thereof. The Micro LED display device comprises a driving substrate; each pixel unit comprises a semiconductor multilayer structure in which a second semiconductor layer, a light-emitting layer and a first semiconductor layer are sequentially stacked from bottom to top, and a groove penetrating through the semiconductor multilayer structure is formed between the pixel units; the first reflection structure is formed on the side wall of the groove of each pixel unit and the edge position of the second semiconductor layer, and a conductive opening is formed in the surface of the second semiconductor layer; the bonding metal layer is formed on the conductive opening corresponding to each pixel unit; the bonding glue layer is formed on the periphery of the bonding metal layer; and the ohmic contact structure is of a net structure formed by mutually connecting the metal walls formed on the surfaces of the pixel units and is formed along the grooves between the pixel units, and one metal wall is shared at the joint of every two adjacent pixel units. The problems that a Micro LED is low in luminous efficiency and insufficient in optical collimation are effectively solved.

The TBC solar cell slice comprises a silicon substrate, and first areas and second areas are alternately arranged on the back face of the silicon substrate; the first region comprises a first tunneling oxide layer, a first conductive passivation layer, a first back passivation layer and a first metal electrode, and the first metal electrode is in ohmic contact with the first conductive passivation layer; the second region sequentially comprises a second tunneling oxide layer, a second conductive passivation layer, a second back passivation layer and a second metal electrode, and the second metal electrode is in ohmic contact with the second conductive passivation layer; the first conductive passivation layer and the second conductive passivation layer have opposite conductive media; the isolation region between the first region and the second region is recessed inwards; at least one end of the TBC solar cell slice along the first direction is an isolation area. According to the invention, the slicing position is in the isolation region, the damage to the first conductive passivation layer or the second conductive passivation layer caused by cutting the first region and the second region during slicing is avoided, the cutting damage is reduced, and the battery performance is improved.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, and the semiconductor body comprises a first surface, a second surface, a well region and a first region; the first surface is provided with a gate trench and a source trench; the first insulating layer is located on the bottom surface and the side wall of the gate trench; the trench gate is located on the side, away from the semiconductor body, of the first insulating layer in the gate trench; the source trench structure comprises a filling layer located in the source trench; the barrier layer is located on the side, away from the semiconductor body, of the filling layer and located in the source trench; the ohmic contact metal layer is located on the first surface and provided with an opening; the source electrode is located on one side, away from the first surface, of the ohmic contact metal layer and contacts the barrier layer through the opening; the drain is located on the second surface. According to the technical scheme of the embodiment of the invention, the surface of the source trench can be flat, no abnormal morphology such as holes or grooves exists, and the reliability of the semiconductor device is improved.

The invention discloses a near-infrared flexible polarized photoelectric detector and a preparation method thereof. The photoelectric detector comprises an Sb2Se3 micron wire, a PET flexible substrate, a metal Ag electrode, a silver wire and polydimethylsiloxane (a PDMS mixture). According to the preparation method, an effective metal-semiconductor-metal (M-S-M) structure is constructed by combining the Sb2Se3 micron wire and the Ag electrode, curing packaging is carried out by adopting a PDMS mixture, the incident light transmittance is improved, meanwhile, the response speed of a device can be greatly improved through ohmic contact formed by the micron wire and the Ag electrode, and the power loss of the device is remarkably reduced. Compared with the prior art, the detector provided by the invention still keeps a stable and high extinction ratio under mechanical bending deformation, and realizes sensitive polarization, quick response and stable performance of a near-infrared band at the same time.

A disclosed semiconductor photodetector includes a first semiconductor layer having a first refractive index and a first band gap; a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a second refractive index and a second band gap; a first electrode; and a second electrode. The second refractive index is greater than the first refractive index, and the second band gap is smaller than the first band gap. The first semiconductor layer includes a p-type first region, an n-type second region, and a non-conductive third region between the first region and the second region. The second semiconductor layer includes a p-type fourth region in ohmic contact with the first electrode, an n-type fifth region in ohmic contact with the second electrode, and a non-conductive sixth region between the fourth region and the fifth region.

The invention relates to the technical field of solar cell structures, in particular to a flexible multi-junction solar cell and a manufacturing method thereof. The flexible multi-junction solar cell comprises a PI film, a bonding metal layer, a back metal layer, an ohmic contact metal layer, a DBR reflecting layer, an epitaxial layer structure, an antireflection film and an N electrode. According to the flexible multi-junction solar cell, the GaAs substrate is firstly used, the sapphire substrate is used in the middle, the PI film is finally used as the final substrate, the mode of overturning the epitaxial wafer twice is adopted, the process is simple, and the problems that the consumption of precious metal is large due to multiple times of metal bonding, and the performance of the epitaxial wafer is affected due to high temperature of the evaporation and thermal stripping film process can be solved; germanium materials are saved, and cost is low; the PI film is used as the cell substrate, the weight is light, the mechanical strength is high, the cell substrate can be bent, and the design requirement of a solar cell array on a spacecraft can be met.