1120 results about "Ohmic contact" patented technology

The invention discloses an annealing temperature control method based on a differentiated ohmic contact material, and aims to solve the problems that the annealing temperature of an N-surface Au / Ge ohmic contact layer of an existing AlGaInP-based red light Micro-LED is not accurately monitored, a temperature field is not uniform and is difficult to detect, and abnormal response lags, the method comprises seven steps of processes (two times of patterning, two times of metal coating, two times of photoresist removal, annealing and observation), and the annealing temperature of the N-surface Au / Ge ohmic contact layer of the existing AlGaInP-based red light Micro-LED is controlled. Preparing a first Au / Ge ohmic contact layer (for function) and a second Au / Ge / Ni ohmic contact layer (for detection) on the N surface of the wafer; by means of the characteristic that Ni inhibits Au / Ge agglomeration, the two-layer agglomeration state difference is observed through an optical microscope, and the temperature is judged (in the normal state, the former agglomerates, and the latter does not agglomerate); the method is convenient in detection, supports batch detection, can find temperature abnormity in real time, improves the process stability, and is suitable for industrial mass production.

The invention discloses an in-situ TEM (Transmission Electron Microscope) device sample preparation method based on a suspended thinning and parallel carrying technology, which can be used for preparing in-situ TEM samples of semiconductor two-end devices and three-end devices, and mainly solves the problems of unstable ohm contact, nonuniform thinning, low success rate and high time cost in the prior art. According to the invention, an FIB sample preparation technology is adopted, and stable and reliable ohmic contact between a sample electrode and an MEMS chip electrode is ensured through specific-angle sample extraction, suspended thinning, parallel carrying, circuit breaking treatment and an accurate electrode welding process. According to the sample prepared by the invention, the failure state of a device can be observed in real time under a transmission electron microscope, the sample has the advantages of high sample preparation success rate, good repeatability, stable electrical parameters and wide applicable chip variety, and the reliability and repeatability of in-situ TEM test data are remarkably improved.

Techniques are provided to form an integrated circuit having different semiconductor devices with different backside contact structures. Field effect transistors (FETs) each includes semiconductor material extending in a first direction between source and drain regions, and gate structures extending in a second direction around the semiconductor material of each FET. Different contact structures are formed on the source or drain regions of the n-channel FETs compared to the p-channel FETs. A backside contact structure on an n-channel source or drain region includes a first layer of phosphorous-doped titanium, a second layer that includes scandium, and a third layer that includes a metal, such as molybdenum. A backside contact structure on a p-channel source or drain region may include only a layer of metal, such as molybdenum, or the layer of metal and a layer of boron-doped titanium. The contact structures may be used to provide enhanced ohmic contact.

The invention discloses a thermal-decay-resistant red light Micro LED epitaxial structure and a preparation method thereof. The epitaxial structure sequentially comprises a substrate layer, an n-type buffer layer, an n-type etching barrier layer, an n-type ohmic contact layer, an n-type limiting layer, a quantum well structure, a p-type spacer layer, a p-type electron barrier layer and a p-type ohmic contact layer from bottom to top. Wherein the quantum well structure is formed by alternating 1-5 pairs of InGaP well layers and three-section type p-type AlGaInP barrier layers, and the three sections of barrier layers adopt gradient energy level design and are all subjected to p-type doping; according to the invention, the problems of carrier loss and low recombination efficiency at high temperature in the prior art are solved by blocking electron overflow through the gradient energy level barrier and supplementing the hole concentration through p-type doping, so that the 85 DEG C external quantum efficiency attenuation rate is less than or equal to 10%, the service life is prolonged to more than 50,000 hours, and the process is compatible with mass production and is suitable for the fields of display, illumination and the like.

The invention discloses a gallium oxide solar-blind ultraviolet detector based on selective area etching and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric detection. Comprises from bottom to top: a substrate; the first epitaxial layer is located on the substrate, and the first epitaxial layer is a highly doped n-Ga2O3 layer; the second epitaxial layer is located on the first epitaxial layer, and the second epitaxial layer is a lightly doped n-Ga2O3 layer; the third epitaxial layer is located on the second epitaxial layer, the third epitaxial layer is a highly-doped p-NiO layer, and the third epitaxial layer is distributed at intervals through selective area etching; and the first ohmic contact layer is located on the area where the third epitaxial layer is distributed at intervals. The detector adopts a PN junction structure working in a reverse bias state, and compared with a Schottky structure, the detector has the advantages that the built-in electric field intensity and the leakage current level of a device are less affected by high-energy photon irradiation and working environment temperature change, and the anti-irradiation performance of the device and the working capability under an extreme temperature condition are effectively improved.

The invention discloses a graphene integrated electrode LED epitaxial structure and a chip preparation method. The epitaxial structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type limiting layer, a non-doped quantum well structure, a p-type spacer layer, a p-type electron barrier layer and a p-type GaP ohmic contact layer from bottom to top. The preparation method comprises the steps of epitaxial structure growth, p-type ITO transparent conductive layer preparation, bonding and substrate removal, mesa structure preparation, passivation isolation, graphene interconnection layer preparation and n-type electrode preparation. Graphene is used for replacing a traditional n-type GaAs ohmic contact layer and an ITO electrode, the problems of poor red light absorption, poor heat dissipation and mechanical brittleness of a traditional structure are solved, the red light transmittance of the chip is improved, the junction temperature under 3 currents is greatly reduced, the chip can bear tensile strain larger than 20%, the chip is suitable for flexible scenes, and the chip is suitable for high-performance large-scale production of red light Micro LEDs.

The invention discloses a semiconductor laser and a preparation method thereof, which can be used in the field of semiconductor device preparation, and the method comprises the steps: firstly, providing a first conductive type substrate; then, epitaxially growing a buffer layer of a first conduction type, a lower optical waveguide limiting layer, a quantum well active light-emitting layer, an upper optical waveguide limiting layer, a corrosion barrier layer, a current injection layer and an intrinsic ohmic contact layer on the substrate in sequence to obtain a multi-layer epitaxial layer; then, etching the multi-layer epitaxial layer to the corrosion barrier layer based on a preset pattern to form a ridge-shaped table which starts from the intrinsic ohmic contact layer and is deeply cut off to the corrosion barrier layer; and finally, performing particle doping in a region corresponding to the ridge-shaped table, and converting one sides, close to the corrosion barrier layer, of the intrinsic ohmic contact layer, the current injection layer, the corrosion barrier layer and the upper optical waveguide limiting layer into a second conduction type. Therefore, current limitation can be realized without performing multiple epitaxy like a traditional buried heterojunction, and the production cost and the process difficulty are greatly reduced.

The invention discloses an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof. The chip structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type etching barrier layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, a non-doped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an insertion layer and an n-type ohmic contact layer from bottom to top. Wherein the p-type AlGaInP polarization induction doping layer introduces a piezoelectric polarization electric field through an Al component gradual change design, high-density two-dimensional hole gas is formed through induction, and the high-Al component insertion layer and the n-type ohmic contact layer form a tunnel junction; according to the invention, the problems of low p-type doping efficiency and high resistivity of the AlGaInP material with high Al component are fundamentally solved, the epitaxial structure and the chip process are simplified, the series resistance of the chip is reduced, the luminous efficiency is improved, the yield is improved, and the method has remarkable technical and commercial values.

The present invention discloses a tellurium-lead-lithium oxide glass powder for BC cell N-region conductive paste and its preparation method, belonging to the field of photovoltaic silver paste. The glass powder adopts components with high Pb, Te, and Li: aTeO2 - bPbO - cLi2O - dBi2O3 - eWO3 - fZnO - gSiO2 - hNa2O; where a + b + c + d + e + f + g + h = 1, 0.2 < a < 0.4, 0.1 < b < 0.4, 0.1 < c < 0.25, 0 < d < 0.1, 0 < e < 0.1, 0 < f < 0.1, 0 < g < 0.1, 0 < h < 0.05, and a + b > 0.5, and the ratio of c to h is (3 - 10):1. By controlling the specific Pb, Te, and Li contents and the specific Li / Na ratio in the present invention, a strong corrosion effect on the poly layer of the cell is achieved, enabling more silver ions dissolved in the glass liquid to recrystallize on the surface of the silicon wafer, thereby achieving good ohmic contact.

The invention discloses a method for preparing a boron nitride-gallium oxide thin film flexible dual-band ultraviolet solar blind detector through Van der Waals stripping, and aims to improve the comprehensive performance of the detector. The method comprises the steps of h-BN substrate pretreatment and surface modification, Sn gradient doped beta-Ga2O3 layer preparation, heterojunction interface passivation treatment, two-step Van der Waals stripping and flexible transfer, ohmic contact electrode preparation, gate type Schottky contact electrode preparation, post-treatment and packaging. According to the core, the interface state density is reduced through Al2O3 passivation, and carrier transport is optimized through Sn gradient doping, so that the detector achieves 200-280 nm dual-band response, the peak response rate is high, the response time is short, the leakage current is low, the flexible bending stability is good, high performance and flexibility are both considered, and industrial application can be achieved.

The invention, which relates to the technical field of the semiconductor laser chip, discloses a wide-temperature working high-power DFB semiconductor laser chip comprising a P-InGaAsP lower waveguide layer, an InGaAsP strain multiple quantum channel, an N-InGaAsP upper waveguide layer, an InAlAs-InP superlattice barrier layer, an N-InP spacing layer 1, an N-InGaAsP corrosion stop layer, an N-InP spacing layer 2, an N-InGaAsP grating layer, and an N-InP grating cover layer. According to the wide-temperature working high-power DFB semiconductor laser chip, a laser material structure is epitaxially grown on a P-InP substrate; a P-InP substrate is adopted, so that large-area back ohmic contact effectively reduces P-type series resistance of a device, and the problem of high heating of a traditional high-power laser is effectively solved; then, an InGaAsP strain compensation quantum well is adopted as a gain region, and wide-temperature single-mode work is realized by utilizing the advantage that an InGaAsP gain spectrum is insensitive to temperature; and the InAlAs-InP two-dimensional superlattice barrier structure is adopted to realize transverse and lateral limitation of carriers, so that the limiting efficiency of the carriers in a gain region is effectively improved, and the problem of low energy band difference of an InGaAsP conduction band is effectively solved.

The invention relates to the technical field of solar cells, and provides a photovoltaic module, a laminated cell, a back contact cell and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein a second surface of the substrate comprises a first region and a second region; forming a tunneling layer on the second surface; forming a first polycrystalline silicon layer on the surface of the tunneling layer by adopting a first deposition process; forming a second polycrystalline silicon layer on the surface of the first polycrystalline silicon layer by adopting a second deposition process; the temperature and pressure of the first deposition process are higher than those of the second deposition process; carrying out doping treatment, and converting the first polycrystalline silicon layer and the second polycrystalline silicon layer into a first semiconductor doped layer; forming a second semiconductor doping layer on the second region; a first electrode and a second electrode are formed, the first electrode being in electrical contact with the first semiconductor doped layer and the second electrode being in electrical contact with the second semiconductor doped layer. According to the invention, low-resistance ohmic contact between the first semiconductor doping layer and the first electrode is realized at least while a good surface passivation effect is ensured.

The invention discloses a laser chip ohmic contact annealing optimization method and related equipment. The method comprises the steps that a metal electrode and a conductive mark layer are formed on the surface of a semiconductor through deposition; applying electrical excitation to the conductive mark layer and collecting electrical response in the annealing temperature rise stage to establish an initial response reference of the position of the conductive mark layer; in the annealing heat preservation stage, the electrical response change of the conductive mark layer is monitored, and the real-time response is compared with the initial response reference so as to judge the ohmic contact forming state of the position where the conductive mark layer is located; and adjusting annealing process parameters according to the judgment result of the ohmic contact forming state. According to the scheme, in-situ monitoring and self-adaptive adjustment of ohmic contact forming states at different positions in the annealing process can be achieved, and the uniformity and yield of ohmic contact of the laser chip are improved.

The invention discloses a photosensitive pixel unit and an image sensor. The photosensitive pixel unit comprises a semiconductor substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the N-type semiconductor layer is positioned above the dielectric layer, is in ohmic contact with the signal reading electrode through the opening part, and sequentially comprises a nanocrystalline particle layer, a metal oxide semiconductor thin film layer and an interface layer which is arranged between the nanocrystalline particle layer and the metal oxide semiconductor thin film layer and has two-dimensional electron gas characteristics from bottom to top; the photoelectric conversion layer is located above the N-type semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

The invention relates to a manufacturing method of a thin-film resistor and a thin-film resistor structure. The method comprises the following steps: forming a first metal layer on a first main surface of a wafer; forming a masking layer in contact with the first metal layer; a resistance material layer is formed on the first main face and patterned, the patterned resistance material layer comprises a thin-film resistor, and the thin-film resistor is in ohmic contact with the first metal connecting line in the first metal layer through the masking layer. According to the method, the first metal layer serving as the metal connecting line of the thin-film resistor is firstly formed, and then the masking layer and the thin-film resistor are formed, so that the etching of the first metal layer and the etching of the masking layer can adopt dry etching, the damage of the dry etching to the thin-film resistor does not need to be considered, and the process difficulty can be reduced.

The invention discloses a photosensitive pixel element containing a P-type thin film transistor transmission gate and an image sensor. The photosensitive pixel element comprises a substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the single-layer or double-layer P-type thin film semiconductor layer is positioned above the dielectric layer and is in ohmic contact with the signal reading electrode through the opening part; the photoelectric conversion layer is located above the P-type thin film semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

The invention provides a vertical cavity surface emitting laser and an epitaxial growth method thereof, and belongs to the technical field of semiconductors. The vertical cavity surface emitting laser comprises a substrate, an N-DBR, an active region growth layer, an oxidation limiting layer, a tunnel junction, a P-DBR and a surface ohmic contact layer which are stacked in sequence. The tunnel junction comprises a p + + layer, a first diffusion barrier layer, an n + + layer and a second diffusion barrier layer which are stacked in sequence. The p + + layer and the n + + layer are obtained through pulse doping growth, and P-DBR growth is carried out after stepped heating is carried out on the tunnel junction. The invention provides a comprehensive process based on pulse doping, an in-situ protection layer and stepped heating control, pulse doping is adopted when the n + + / p + + layer of the tunnel junction grows, the first diffusion barrier layer, the second diffusion barrier layer and the stepped heating process in subsequent growth are combined, and doping diffusion is remarkably inhibited while high conductivity of the tunnel junction is maintained.

The invention discloses a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure comprises a bottom electrode, a resistive random layer and a top electrode which are sequentially stacked from bottom to top, the upper surface of the bottom electrode is in Schottky contact with the lower surface of the resistive layer, and the lower surface of the top electrode is in ohmic contact with the upper surface of the resistive layer; the resistive layer is a single oxide film layer; the bottom electrode and the top electrode are made of the same metal nitride, and the atomic number ratio of metal elements to nitrogen elements in the top electrode is larger than the atomic number ratio of metal elements to nitrogen elements in the bottom electrode. The structure of the memory can be simplified, and the process complexity and the manufacturing cost can be reduced.

A light-emitting device includes a light-emitting laminating structure having an ohmic contact layer, a transition layer, a current-spreading layer, a first type semiconductor layer, an active layer, and a second type semiconductor layer. The current-spreading layer has aluminum, and, in the current-spreading layer, a relative content of the aluminum with respect to a composition of the current-spreading layer is fixed. The transition layer has aluminum, and, in the transition layer, a relative content of the aluminum with respect to a composition of the transition layer is less than the relative content of the aluminum in the current-spreading layer. A method for producing the light-emitting device is also disclosed.

The utility model discloses an anti-crosstalk micro-display light-emitting pixel, and relates to the technical field of semiconductors. The micro-display light-emitting pixel comprises a driving back plate and a display device layer on the driving back plate, wherein the display device layer comprises a light-emitting unit, an insulating layer and a groove structure; a bonding layer is arranged between the P-type ohmic contact layer in the light-emitting unit and the driving back plate; the insulating layer is formed outside the light-emitting unit in a filling manner; the groove structure penetrates through the insulating layer and surrounds the periphery of the light-emitting unit, the groove structure is filled with a metal material, the light-emitting unit is an inorganic compound semiconductor, and the top height of the groove structure is not smaller than that of the light-emitting unit. Based on the technical scheme provided by the invention, light emitting constraint can be carried out through the through type groove structure, and better optical crosstalk isolation is realized.

The invention provides a glass powder composition, base metal conductive paste, a preparation method and application, and the glass powder composition comprises the following components in percentage by weight: 10 to 80 percent of TeO2, 10 to 70 percent of PbO, 0 to 70 percent of Bi2O3, 0 to 20 percent of Li2O, 0 to 20 percent of WO3, 0 to 20 percent of ZnO, 0 to 30 percent of SiO2, 0 to 10 percent of Na2O and 1 to 20 percent of Cu2S. Through reasonable design of components and content of the glass powder, the transition temperature (Tg) of the glass powder composition is relatively increased, atomic diffusion is inhibited, glass active components are prevented from being consumed too early, the etching effect of the glass powder on a silicon wafer is guaranteed, and good ohmic contact is formed; the high-conductivity copper can assist in enhancing the conductivity of a base metal conductive system, and the conductivity of the sintered slurry is improved; on the other hand, in the initial stage of sintering, Cu2S can preferentially react with a base metal material, so that consumption of the base metal to active ingredients of the glass powder composition is reduced, the good activity of the glass powder is kept, and the contact performance of an electrode is improved.

The present disclosure is applicable to the technical field of solar cells, and provides a solar cell, a battery module, and a photovoltaic system. The solar cell comprises: a silicon substrate, the silicon substrate comprising a first area and a second area, and the first area and the second area being located on a same side or two opposite sides of the silicon substrate; a P-type doped polysilicon layer, at least formed on the first area; an N-type doped polysilicon layer, at least formed on the second area; a first electrode, being in contact with the P-type doped polysilicon layer; and a second electrode, being in contact with the N-type doped polysilicon layer, wherein the bonding strength between the second electrode and the N-type doped polysilicon layer is greater than that between the first electrode and the P-type doped polysilicon layer. In the solar cell of the present disclosure, the bonding strength between the second electrode and the N-type doped polysilicon layer is increased, so that the connection between the second electrode and the N-type doped polysilicon layer is more stable and reliable, and the second electrode maintains good ohmic contact with the N-type doped polysilicon layer, thereby improving the structural stability of the cell.

The invention provides a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) integrated with an SCR (Selective Catalytic Reduction) and a manufacturing method thereof, and relates to the technical field of power semiconductor devices, the device is integrated with a PNPN four-layer structure consisting of a P + region, an N-type epitaxial layer, a P-type body region and an N + source region between a grid electrode and a source electrode, and the P + region is in metal ohmic contact with the source electrode. Through collaborative design of the distance and the doping concentration of the P + region and the N + source region, the forward and reverse trigger voltage thresholds of the PNPN structure can be accurately matched with the asymmetric driving window of the electric control main drive. The structure is arranged on the outer edge of a cellular area or a terminal area, and is electrically isolated from an active area, a field plate is arranged to suppress false triggering, ohmic contact is optimized to accelerate turn-off, and it is ensured that holding current is higher than parasitic latch triggering current, so that rapid and reliable discharge and self-protection of bidirectional surge between a gate and a source are achieved on the premise that the performance of a main device is not affected, and the reliability of the device is improved. And the gate oxide reliability is obviously improved.

The invention relates to a photovoltaic cell piece, a preparation method of the photovoltaic cell piece and a photovoltaic module, and relates to the technical field of photovoltaics. The photovoltaic battery piece comprises a substrate and a bonding pad group which are in ohmic contact, the bonding pad group comprises a middle bonding pad and two outer bonding pads which are arranged at intervals in the same bonding pad group, the middle bonding pad is located between the two outer bonding pads, the middle bonding pad and the outer bonding pads are used for welding the same welding strip, the middle bonding pad has a first thickness H1, the outer bonding pads have a second thickness H2, and the first thickness H1 is larger than the second thickness H2. H2 > H1. After the welding pads of the photovoltaic cell are welded with the welding strip, the outer side welding pad with the relatively large thickness can generate relatively large plastic deformation, and the relatively large plastic deformation can absorb or dissipate relatively much energy, so that the acting force or energy transmitted to the substrate by the welding strip through the outer side welding pad is relatively small; the warping amount of the substrate can be relatively small or the substrate does not warp, so that the possibility of structural damage of the photovoltaic cell is reduced.

The application discloses a gallium oxide vertical device and a preparation method thereof. The gallium oxide vertical device comprises an epitaxial structure, a cathode and an anode matched with the epitaxial structure, the epitaxial structure comprises a heavily doped n-type Ga2O3 substrate, a lightly doped n-type Ga2O3 drift region, an interlayer and a p-type nitride epitaxial layer which are sequentially stacked, the lightly doped n-type Ga2O3 drift region, the interlayer and the p-type nitride epitaxial layer form a p-i-n structure, the cathode forms an ohmic contact with the heavily doped n-type Ga2O3 substrate, and the anode forms an ohmic contact with the p-type nitride epitaxial layer, wherein the material of the interlayer is an Al-containing compound, and the surface layer region of the lightly doped n-type Ga2O3 drift region close to the interlayer also has Al elements, the Al elements are diffused into the lightly doped n-type Ga2O3 drift region in the bonding process under high pressure.

The embodiment of the invention provides a gallium nitride device, a preparation method and a chip. The gallium nitride device comprises an epitaxial layer, a source electrode, a drain electrode and a grid electrode, the drain electrode and the epitaxial layer form Schottky contact and ohmic contact distributed at intervals in an array mode, the electric field distribution on one side of the drain electrode is improved, the output capacitance of the gallium nitride device is reduced, the breakdown voltage and the frequency gain characteristic of the gallium nitride device are improved, and therefore the gallium nitride device is suitable for a broadband power amplifier and a higher frequency range. The problem that a scheme for improving the breakdown voltage of a device from the perspective of reducing electric leakage or modulating electric field distribution in the prior art is not suitable for a communication system of a high-frequency end is solved.

The application discloses a kind of detection p-type group III nitride activation effect characterization method, the present application is based on kelvin probe force microscope, by preparing metal electrode layer on the surface of p-type group III nitride to form ohmic contact, and metal electrode layer and the sample stage of kelvin probe force microscope form conductive connection, to weaken the influence of other epitaxial layer except p-type group III nitride on test result, according to the difference of p-type group III nitride and metal electrode layer surface potential or the conversion of surface potential is tested to the combination hall test system, realizes the relatively accurate measurement of p-type group III nitride activation effect.The present application method is simple and fast and effective, can accurately determine the change of p-type group III nitride surface potential before and after activation, and will play an important role for the research p-type group III nitride activation method.

The invention provides a method for improving metal-semiconductor contact based on a silane coupling agent and application. The method comprises the steps that a semiconductor device is provided, the semiconductor device comprises a metal-semiconductor contact structure, the metal-semiconductor contact structure is Schottky contact, and a semiconductor material, in contact with a metal material, contained in the metal-semiconductor contact structure comprises a two-dimensional semiconductor material with hydroxyl on the surface; the semiconductor device is in contact with a silane coupling agent solution, so that the silane coupling agent reacts with hydroxyl on the surface of the two-dimensional semiconductor material, a molecular passivation layer is formed on the surface of the two-dimensional semiconductor material, and Schottky contact is converted into ohmic contact. According to the method provided by the invention, the molecular passivation layer is constructed on the surface of the two-dimensional semiconductor material by adopting the silane coupling agent, so that a surface dangling bond and an interface state in the metal-semiconductor contact structure are effectively eliminated, the metal-semiconductor contact structure is converted from Schottky contact to ohmic contact, and the stability and the reliability of a semiconductor device are improved.

This invention relates to the field of semiconductor optoelectronic device technology, specifically to a method and application for reducing the contact resistance of high-Al-content n-AlGaN materials in device manufacturing processes. The method involves surface atom adsorption and annealing of the n-AlGaN layer under a protective gas atmosphere; the atoms are Si and N atoms. This method significantly increases the carrier concentration on the material surface, thereby contributing to excellent ohmic contact performance and reducing the material's contact resistivity. It solves the problem of difficult ohmic contact preparation for high-Al-content n-AlGaN materials, especially the difficulty in forming ohmic contacts after etching. The method is simple and reproducible, effectively avoiding the complexity and instability of existing processes such as acid / alkali corrosion or high-temperature annealing. It ensures large-scale mass production and has no adverse effects on subsequent device fabrication, exhibiting good process compatibility.

This apparatus for manufacturing a GaAs semiconductor device comprises: a first metal layer forming unit for forming a first metal layer 161 on a GaAs semiconductor structure 11 including a GaAs semiconductor as a Group III-V compound semiconductor containing gallium (Ga) as a Group III element and arsenic (As) as a Group V element; a laser beam irradiation unit for irradiating the first metal layer 161 with a laser beam in order to create an ohmic contact between the GaAs semiconductor structure 11 and the first metal layer 161; and a second metal layer forming unit for forming, on the first metal layer 161, a second metal layer 162 having a higher laser beam reflectance than the first metal layer 161 after irradiation with the laser beam.