2888 results about "Ohmic contact" patented technology

The invention discloses a gallium oxide monolithic heterogeneous integrated device and a manufacturing method thereof, which can be used in the field of semiconductor devices, in the device, an N-type gallium oxide epitaxial wafer comprises an epitaxial layer and a substrate layer; one side of the epitaxial layer of the N-type gallium oxide epitaxial wafer is bonded with one side of the P-type material layer; the N-type doped region is arranged in the P-type material layer and is in contact with the epitaxial layer of the N-type gallium oxide epitaxial wafer; the gate control region covers the N-type doped region and is arranged on the other side of the P-type material layer; ohmic contact is formed between the source electrode and the P-type material layer. The drain electrode is arranged on one side of the substrate layer of the N-type gallium oxide epitaxial wafer and forms ohmic contact with the substrate layer; and the substrate layer is bonded with the drain electrode. Therefore, small-size gallium oxide is bonded to the substrate for tape-out, so that large-scale preparation of the device on a production line can be realized, and the heat dissipation performance of the gallium oxide device is improved; by bonding the N-type gallium oxide and the P-type material, a heterogeneous PN junction is formed to make up for a missing gallium oxide homogeneous PN junction, and the stability of the structure is improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention relates to an enhanced gallium nitride high-mobility transistor and a preparation method thereof. The transistor sequentially comprises a substrate, a buffer layer, an i-GaN channel layer, an AlGaN barrier layer, a p-GaN layer and a gate dielectric layer from bottom to top, the source electrode and the drain electrode are respectively in ohmic contact with the two-dimensional electron gas, and the grid electrode and the p-GaN layer are in Schottky contact, so that the two-dimensional electron gas below the grid electrode is exhausted to realize normal closing; an electrode is arranged in a region between the grid electrode and the drain electrode, a thin-layer medium is arranged below the electrode, and the thin-layer medium and the electrode form an equivalent MIS grid structure; and the electrode is electrically connected with the source electrode. The switching time of the device is determined by the switching speed of the p-GaN HEMT composed of S-G1-D. Compared with a traditional Si MOS cascade structure, the device has the advantages of being fast in switching and free of reverse recovery charges. And meanwhile, the withstand voltage of the device is determined by a depletion mode MIS GaN HEMT consisting of S-G2-D, and the p-GaN grid does not bear high voltage, so that the device has the advantage of high reliability.

The utility model relates to the technical field of solar cells, in particular to a solar cell, a photovoltaic module and a photovoltaic system. The potential risk that high-temperature slurry is sintered and diffused into a tunneling oxide layer is reduced while parasitic absorption of a doped polycrystalline silicon layer is reduced, and non-radiative recombination is reduced. A solar cell comprises a silicon substrate layer which comprises a first surface and a second surface which are oppositely arranged; the tunneling oxide layer is arranged on the first surface of the silicon substrate layer; the doped polycrystalline silicon layer is arranged on one side, far away from the silicon substrate layer, of the tunneling oxide layer; the doped polycrystalline silicon layer comprises a first sub-layer and a second sub-layer which are sequentially stacked in the direction gradually away from the silicon substrate layer; and a gate line electrode pattern; wherein the first sub-layer is further doped with a carbon element, and ohmic contact is formed between the grid line electrode pattern and the second sub-layer.

The invention discloses a directional diagram reconfigurable antenna capable of switching feed through an MEMS switch, and belongs to the field of radio frequency front-end devices. The directional diagram reconfigurable antenna is composed of a micro-strip radiation unit, a guide parasitic unit, a composite beam ohmic contact type MEMS switch, a one-to-four feed network, a direct current bias line, a test patch bonding pad, a coplanar waveguide, a gradual change micro-strip line, a dielectric substrate and a metal ground backboard. The two-stage MEMS switches are erected on the one-to-four feed network, when the two-stage switches on a certain feeder line are turned on, radio frequency current can flow to the corresponding basic radiation unit through the feeder line to generate an inclined beam facing the quadrant, and the two basic radiation units on the front side can be enabled by simultaneously turning on the four switches on the front side to generate an inclined beam facing the quadrant. And generating an inclined beam in the front side positive direction. The antenna adopts a single-layer board design, the dielectric substrate does not need to be punched, the structure is simple, manufacturing is convenient, the adopted MEMS switch is small in loss and high in isolation degree, and rapid printing and manufacturing can be achieved through the surface etching process.

The invention relates to the technical field of chips, in particular to a red light LED chip and a manufacturing method thereof. The red light LED chip comprises a back electrode, a Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type limiting layer, a P-type waveguide layer, a light emitting layer, an N-type semiconductor layer, a roughened spherical island, a passivation layer and a front electrode from bottom to top. The Au filling barrier layer is positioned in a chip cutting channel projection area and is coated by the dielectric film layer; the surface, protruding towards the mirror surface layer, of the ohmic contact layer is an arc-shaped surface. Pyramid suede surfaces are uniformly distributed on the surfaces of the roughened spherical islands. The manufacturing method is optimized, and the obtained red light LED chip is high in luminous efficiency, good in reliability and stable in overall performance.

A solar cell comprises a substrate, a first passivated contact layer and a second passivated contact layer, a first passivation film layer and a first dielectric layer, and a first electrode. The first passivation film layer is stacked on the first passivated contact layer, in an insulating isolation groove and on the second passivated contact layer; a first through groove is formed in an area, which corresponds to each first polycrystalline silicon doped conductive layer, of the first passivation film layer; one end of the first electrode passes through the first through groove to be in ohmic contact with the first passivated contact layer; and the first dielectric layer covers the first passivation film layer and covers first areas on the first passivated contact layer, wherein the first areas are areas that are located in a surface, which is exposed from the first through groove, of the first passivated contact layer, and are located between side walls of the first through groove and the first electrode.

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a semiconductor body including a well region, a first region, and a second region; the well region is located on the side, away from the first surface, of the first region; the first surface is also provided with a gate trench and a source trench; the second region surrounds the bottom surface and the side wall of the source trench; the trench gate is positioned on one side, far away from the semiconductor body, of the insulating layer in the gate trench; the source trench structure comprises a filling layer located in a source trench; the ohmic contact resistance between the ohmic contact layer and the semiconductor body is smaller than the ohmic contact resistance when the metal titanium and the semiconductor body form ohmic contact; and no chemical reaction intermediate product exists between the filling layer and the ohmic contact layer at the annealing temperature of the ohmic contact layer. According to the technical scheme provided by the embodiment of the invention, the electrical performance of the semiconductor device is improved.

Lateral III-N devices such as AlGaN / GaN HEMTs can have structures which serve to improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure that includes a III-N buffer layer, a III-N channel layer and a III-N barrier layer where a compositional difference induces a 2DEG channel therein. The first portion is in ohmic contact with the 2DEG channel and the second portion extends over a top surface of the III-N barrier layer and is in direct contact with the top surface of the III-N barrier layer. The device further includes a drain-to-substrate pinch-off voltage and a maximum rated drain-to-source operating voltage which is greater than the drain-to-substrate pinch-off voltage, and the 2DEG channel is fully depleted of charge below the second portion of the drain electrode when the III-N device is biased at or above the maximum rated drain-to-source operating voltage.

The invention provides a GaN HEMT (High Electron Mobility Transistor) device. The GaN HEMT device comprises a low-resistance substrate; the grounded back grounding metal is formed on the back side of the substrate; the P-type epitaxial layer is formed on the substrate; a GaN HEMT structure layer, wherein the GaN HEMT structure layer comprises an active region and a high resistance region; the deep hole is formed downwards from the upper surface of the high-resistance region, and the bottom end of the deep hole enters the substrate; the first connecting region is formed in the deep hole in a filling mode, the bottom end of the first connecting region enters the substrate, and the contact between the first connecting region and the substrate is ohmic contact. According to the GaN on SiC HEMT device, the technical problem that the grounding process is complex due to the structure of a traditional GaN on SiC HEMT device is solved.

The invention provides a heterojunction solar cell and a preparation method thereof, and the method comprises the steps: sequentially arranging oxygen-containing crystalline silicon layers of a first conduction type on the surface, far away from a substrate, of a first passivation layer through employing a set deposition technology, wherein the oxygen atom doping concentration of the oxygen-containing crystalline silicon layers is gradually increased in the direction away from the substrate; on one hand, light oxygen doping is arranged at the interface of the first passivation layer, so that the dark attenuation phenomenon of a heterojunction cell is reduced, and the power off-shift problem of a photovoltaic module is further reduced; on the other hand, heavy oxygen doping is arranged on one side far away from the first passivation layer, so that the optical band gap and the short-circuit current of the crystalline silicon layer on the light receiving surface are effectively improved; and finally, oxygen-free doping is arranged at an interface adjacent to the transparent conducting layer, so that ohmic contact between the oxygen-containing crystal silicon layer and the transparent conducting layer is effectively reduced. Therefore, the comprehensive electrical performance of the heterojunction solar cell is effectively ensured and improved.

The invention discloses an enhanced HEMT (High Electron Mobility Transistor) device, a preparation method, a chip and electronic equipment. The device structurally comprises a substrate layer, a buffer layer, a channel layer, a barrier layer and a cap layer, wherein the buffer layer, the channel layer, the barrier layer and the cap layer are sequentially positioned on the substrate layer; the passivation layer is located on the side wall of the cap layer and located on the upper surface of the barrier layer; the isolation structure is located on the side wall of the HEMT device, and the isolation structure penetrates through the barrier layer and the channel layer and is located on the buffer layer; the drain electrode and the source electrode respectively penetrate through the passivation layer and are positioned on the upper surface of the barrier layer; the grid electrode is located on the upper surface of the cap layer, and the contact interface of the grid electrode and the cap layer at least comprises ohmic contact and Schottky contact. Compared with the prior art, the hybrid gate HEMT device is formed by replacing a part of Schottky gate metal with ohmic gate metal in the gate structure of the HEMT device, so that the reliability and the stability of the threshold voltage of the gate of the p-GaN gate HEMT device can be effectively improved.

The invention discloses a double-groove super junction structure and a manufacturing method thereof, the double-groove super junction structure comprises a plurality of MOS cells which are connected in parallel, and each MOS cell comprises a drain electrode, an upper metal source electrode, a grid electrode, a semiconductor epitaxial layer, a substrate layer, a P well layer and an N well layer; a groove is formed between adjacent MOS cells and in the middle of the heavily doped P well layer I through etching, an oxide layer is deposited at the bottom of the groove, a side metal source electrode is arranged on the surface of the oxide layer, and the top of the side metal source electrode is in contact with the upper metal source electrode; the side surface of the side metal source is in ohmic contact with the N well layer, the lightly doped P well layer I and the heavily doped P well layer I; the grid electrode is a longitudinal groove type grid electrode and is arranged between the two N well layers of the single MOS cell, and the grid electrode is connected with the N well layers, the first lightly-doped P well layer and the diffusion layer in an isolated mode through a grid oxide layer. According to the invention, the injection depth of the heavily doped P well layer I is increased through the groove, and the (11-20) surface channel is adopted, so that the interface state density is greatly reduced, and the overall size of the device is reduced.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor), and discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) semiconductor structure for optimizing source and drain contact, which comprises a drain, a semiconductor epitaxial layer, a source and a grid, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P well layer, an N well layer and a P-layer, the P-layer is internally provided with source polycrystalline silicon, and the N drift layer is internally provided with drain polycrystalline silicon. The top end of the source polycrystalline silicon is in ohmic contact with the source electrode; three metal oxide layers are arranged in the N well layer, and the top ends of the three metal oxide layers are connected with a source electrode; a plurality of semicircular metal layers are also arranged in the drain electrode; and the semicircular metal layers are in ohmic contact with the N substrate layer. According to the invention, a low-resistance channel is formed through the high-concentration phosphorus-doped heavily-doped gate, the charge and discharge time of gate charges is reduced, and the doped gate provides an additional conductive path, so that the switching time is reduced, the power conversion efficiency is improved, and the heat loss is reduced.

The present invention relates to a solar cell and a preparation method therefor, and a photovoltaic module. The solar cell comprises: an N-type substrate; a patterned first passivation contact structure, which is arranged on a light-receiving surface of the substrate, and comprises a first dielectric layer having a thickness less than or equal to 2 nm and an N-type first doped polysilicon layer; a second passivation contact structure, which is arranged on the entire backlight surface of the substrate, and comprises a second dielectric layer having a thickness greater than 2 nm and having a through hole and a P-type second doped polysilicon layer having a doping concentration of 5×1018 to 3×1020 atom / cm3; a first functional layer on the substrate and the first passivation contact structure; a second functional layer on the second doped polysilicon layer; a first electrode, which penetrates the first functional layer to make ohmic contact with the first doped polysilicon layer; and a second electrode, which penetrates the second functional layer to make ohmic contact with the second doped polysilicon layer.

A series connection method of back contact battery pieces belongs to the field of solar battery preparation, and is characterized by comprising the following steps: printing UV glue on the surfaces of the back contact battery pieces; conductive wires are arranged on the surfaces of the battery pieces needing to be connected in series; an ultraviolet lamp is turned on for irradiation, so that the UV glue is cured, and a back contact cell string is prepared; laying an adhesive film protection layer on the surface of the battery string; laminating the battery strings, and pressing the conductive wires on the surfaces of the battery pieces; and the conductive wires are in ohmic contact with a to-be-conducted area on the surface of the battery piece. The narrow conductive wires are adopted, the double-sided rate of the module is high, the generating capacity of the module can be effectively improved, and the LCOE of the system is reduced; the UV glue is used for fixing the conductive wires, so that the problem that the conductive wires deviate on the surfaces of the battery pieces in the lamination process and the long-term use process of the assembly can be avoided, and the short-circuit risk of the conductive wires is reduced; crimping or welding is achieved in the laminating process, battery string bending caused by high-temperature welding is avoided, and meanwhile the pseudo soldering problem is avoided.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure with high heat dissipation performance, which comprises a plurality of MOS cells arranged in parallel, and is characterized in that each MOS cell comprises a metal drain electrode, a semiconductor epitaxial layer, a metal source electrode and a gate oxide layer covering the surface of the metal source electrode, performing ion implantation in the semiconductor epitaxial layer to form an N substrate layer, an N drift layer, an N well layer, a heavily doped P layer and a P well layer; source electrode doping layers are arranged on the two sides of a single MOS cell, the source electrode doping layers are in ohmic contact with the metal source electrodes, and the source electrode doping layers are made of gallium arsenide or gallium nitride or nichrome. According to the invention, the source electrode doping layer with the sinking design is arranged above the MOS cell, so that the N well layer can be in direct contact with the metal source electrode, and the N well layer can be in indirect contact with the metal source electrode through the source electrode doping layer, thereby reducing the ohmic resistance of the N well layer and the metal source electrode, and reducing the heating at the contact position.

The invention discloses an AlScN device with low working voltage and low leakage current and a preparation method of the AlScN device. The device comprises a bottom electrode layer, a functional layer and a top electrode layer which are stacked in sequence, the functional layer comprises an AlScN ferroelectric material, and the bottom electrode layer is in ohmic contact with the functional layer; the top electrode layer is made of low-melting-point metal with the melting point lower than 200 DEG C, and part of the low-melting-point metal element is diffused and permeated into the functional layer. According to the invention, the low-melting-point metal is used as the top electrode, the working voltage and leakage current of the top electrode can be remarkably reduced, and preferably, the low-melting-point metal is melted and diffused and permeated into the functional layer through annealing treatment to form good contact and permeation doping with the functional layer, so that deep modification of electrical properties of the functional layer is formed; the working voltage and the leakage current of the AlScN-based ferroelectric memory device can be further reduced at the same time, and the AlScN-based ferroelectric memory device has far-reaching significance for the development of the AlScN-based ferroelectric memory device.

The invention discloses a solar cell, a photovoltaic module and a preparation method thereof. The solar cell may include: a silicon substrate having a textured first main surface; an emitter, a passivation layer and a front antireflection layer are laminated on the first main surface from inside to outside; a first silver-aluminum gate line arranged on the front antireflection layer, wherein the first silver-aluminum gate line is in ohmic contact with the emitter; in the textured structure, a metalized area and a non-metalized area corresponding to the first silver-aluminum gate line meet at least one of the following conditions: a first projection coefficient of the metalized area is greater than a second projection coefficient of the non-metalized area except the metalized area; the roughness of the metalized region is greater than that of the non-metalized region; the top of the suede area corresponding to the metalized area is of a plane structure or a cambered surface structure, and the top of the suede area corresponding to the non-metalized area is of a pointed structure; the metalized region is of a planar structure, and the non-metalized region is of a pyramid structure. The structure can improve the reliability of the solar cell.

The utility model relates to the technical field of solar cells, and discloses a solar cell which is provided with a grid line area and a non-grid line area. The solar cell includes: a silicon substrate; the backlight surface is provided with a first backlight area and a second backlight area, the first backlight area corresponds to the grid line area in position, and the second backlight area corresponds to the non-grid line area in position; the patterned passivation contact structure comprises a dielectric layer and a doped polycrystalline silicon layer, the doped polycrystalline silicon layer is provided with a first surface deviating from one side of the dielectric layer, and a patterned area of the passivation contact structure corresponds to the grid line area in position; the first functional layer is arranged on the surface of the silicon substrate and the doped polycrystalline silicon layer corresponding to the second backlight area; the first electrode penetrates through the first functional layer and is in ohmic contact with the doped polycrystalline silicon layer; the flatness of the first surface is higher than that of the second backlight area. The solar cell can reduce the problem of film explosion of the first passivation layer and reduce the contact resistance between the doped polycrystalline silicon layer and the first electrode.

An aerosol generation device (1) and a manufacturing method therefor. The aerosol generation device (1) comprises a microwave resonator (10) and an accommodating base (20). The microwave resonator (10) comprises an outer conductor unit (11) and an inner conductor unit (12) arranged in the outer conductor unit (11), the inner conductor unit (12) having one end connected to a closed end of the outer conductor unit and one end extending towards an open end of the outer conductor unit (11). The accommodating base (20) is connected to the open end, and comprises an accommodating portion (21) for accommodating an aerosol generation substrate, and the accommodating portion (21) is arranged in a resonant cavity (13). The inner conductor unit (12) comprises a conductor column (121) and a probe device (122), the conductor column (121) comprising a free end extending toward the accommodating portion (21), the probe device (22) comprising at least one probe (1222) extending to a side portion of the accommodating portion (21). The probe device (122) is arranged on the accommodating portion (21) and is in ohmic contact with the free end of the conductor column (121). The probe device (122) is arranged on the accommodating base (20), and is independent from the conductor column (121), thereby facilitating manufacturing. The probe (1222) extends to the side portion of the accommodating portion (21), so that the uniformity of a microwave field is significantly improved.

The invention relates to the technical field of semiconductor lasers, and discloses a semiconductor laser and a preparation method thereof, and the semiconductor laser comprises an epitaxial structure which comprises a substrate, a buffer layer, a lower limiting layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper limiting layer and an ohmic contact layer which are stacked from bottom to top; the back electrode is formed on the surface of one side, far away from the buffer layer, of the substrate; the side, close to the ohmic contact layer, of the epitaxial structure is etched to form a first current injection window, the etching end point of the first current injection window is the ohmic contact layer, and a plurality of suppression current injection structures are arranged in the edge area of the first current injection window at intervals in the first direction; and the front electrode is formed on the first current injection window and the plurality of suppression current injection structures. According to the invention, the thermal lens effect can be counteracted, a small far-field horizontal divergence angle can be realized, the temperature distribution of the current injection region can be uniform, and the reliability of the semiconductor laser can be improved.

The invention discloses a diamond MOSFET device compatible with a CMOS ohmic contact process and a preparation method of the diamond MOSFET device. The preparation method comprises the steps that S1, a diamond substrate is selected, and an intrinsic diamond layer is grown on the diamond substrate in a homoepitaxial mode; s2, preparing a mask, and forming a boron-doped diamond layer in a source region and a drain region on the intrinsic diamond layer through boron ion implantation; s3, depositing a layer of Si film and a layer of Ti film on the surface of the sample; s4, performing two-step annealing on the sample to obtain ohmic contact formed by the boron-doped diamond layer, the boron-doped silicon layer and the titanium silicide layer; s5, removing the mask and the thin film above the mask; s6, preparing a terminal diamond surface layer; s7, preparing a passivation layer and windowing to form a source window and a drain window; and S8, preparing a gate electrode. According to the method, high-quality ohmic contact can be formed on the diamond through the gold-free process, the gold ion pollution risk is thoroughly avoided, and CMOS process compatibility is achieved.

The invention discloses a microstructure silicon carbide ultraviolet photoelectric detector with high quantum efficiency and a preparation method thereof, and belongs to the technical field of ultraviolet photoelectric detection. The detector adopts a bottom-to-top structural design and comprises a silicon carbide highly-doped n + type substrate, an n type buffer layer, a low-doped n-type absorption layer, a low-doped p-type absorption layer (containing a microstructure), an annular highly-doped p + type ohmic contact layer and a passivation isolation layer. Reverse bias voltage is applied to the p + type ohmic contact electrode to form a depletion electric field, and the microstructure promotes the p-i-n structure electric fields to be mutually connected and coupled, so that the photon-generated carrier depletion efficiency is improved, and the responsivity of the device and the external quantum efficiency are enhanced. And meanwhile, the microstructure enables a short-wave ultraviolet signal to directly penetrate through the p-type absorption layer to enter the internal absorption layer, so that photon-generated carrier recombination caused by surface defects of the p + type ohmic contact layer is avoided, the collection efficiency of photon-generated carriers is improved, and ultraviolet full-band detection is realized.

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

The invention discloses an annealing temperature control method based on a differentiated ohmic contact material, and aims to solve the problems that the annealing temperature of an N-surface Au / Ge ohmic contact layer of an existing AlGaInP-based red light Micro-LED is not accurately monitored, a temperature field is not uniform and is difficult to detect, and abnormal response lags, the method comprises seven steps of processes (two times of patterning, two times of metal coating, two times of photoresist removal, annealing and observation), and the annealing temperature of the N-surface Au / Ge ohmic contact layer of the existing AlGaInP-based red light Micro-LED is controlled. Preparing a first Au / Ge ohmic contact layer (for function) and a second Au / Ge / Ni ohmic contact layer (for detection) on the N surface of the wafer; by means of the characteristic that Ni inhibits Au / Ge agglomeration, the two-layer agglomeration state difference is observed through an optical microscope, and the temperature is judged (in the normal state, the former agglomerates, and the latter does not agglomerate); the method is convenient in detection, supports batch detection, can find temperature abnormity in real time, improves the process stability, and is suitable for industrial mass production.

The invention provides a silicon carbide trench MOSFET device with a three-side trench structure and a preparation method thereof, and the method comprises the steps: growing a silicon carbide epitaxy on a silicon carbide substrate, and carrying out the injection to form a P-well region; forming a first barrier layer on the P-well region, and performing injection to form a P + region; removing the first barrier layer to form a second barrier layer, and performing injection to form an N + region; removing the second barrier layer, and simultaneously performing rapid thermal annealing on the P-well region, the P + region and the N + region; forming a third barrier layer, and etching to form a gate trench region; removing the third barrier layer, and performing dry-oxygen thermal oxidation to form a gate oxide layer; forming polycrystalline silicon by using chemical vapor deposition; after the polycrystalline silicon is doped, etching is carried out to form a grid electrode; and depositing metal to form a drain electrode and a source electrode, and performing rapid thermal annealing on the drain electrode and the source electrode to form ohmic contact. By arranging the three-side groove structure, the area of the channel is increased, and conduction resistance is reduced.

The invention provides an EML laser and a preparation method of an air bridge, belongs to the technical field of optical communication lasers, and is used for solving the problem that the stray capacitance of connecting metal between a waveguide electrode and a PAD electrode of the EML laser is too large. The preparation method of the air bridge process of the EML comprises the following steps: growing a mask layer on the surface of an epitaxial InP wafer, photoetching to form a ridge waveguide pattern, etching the mask layer by adopting ICP (Inductively Coupled Plasma), and removing photoresist; etching the ohmic contact layer by adopting ICP (Inductively Coupled Plasma) and removing the mask layer; gluing and photoetching the surface of the wafer to form a pier pattern; adopting ICPCVD to grow a dielectric film at low temperature; gluing and photoetching the surface of the wafer to form a dielectric film bridge pattern; carrying out ICP etching on the dielectric film and removing the bridge and pier photoresist to form a dielectric film bridge; and performing wet etching on the InP epitaxial layer to the etching stop layer. According to the method, the dielectric film bridge is built at the connecting metal between the waveguide electrode and the PAD electrode, the low dielectric constant characteristic of air is utilized, the distance between the metal and the quantum well is greatly increased, the stray capacitance of the EML is reduced, and the bandwidth is improved.

The invention provides stacked gate laser secondary injection enhanced repair equipment and a repair method. The stacked gate laser secondary injection enhanced repair equipment comprises a conveying belt; the feeding assembly comprises a first feeding mechanism and a second feeding mechanism which can be used in a power-off state; a first dual-laser assembly; a second dual-laser assembly; a carrying assembly; a turntable; the feeding assembly, the rotary table and the discharging assembly are sequentially arranged, and the carrying assembly is located on one side of the rotary table so that position switching of products between the conveying belt and the rotary table can be achieved. The device can be suitable for battery pieces of different sizes, the battery pieces of different sizes are positioned for four times through laser, the acting contact time of the laser and the battery pieces is prolonged, ohmic contact is better, current is increased, silver-silicon microcrystals are promoted to be formed, sintering is sufficient, and the filling factor of the battery pieces is improved.

Provided in the present application are a solar cell, a solar cell module, and a manufacturing method for a solar cell, so as to guarantee good ohmic contact between a first electrode and a passivation layer, improve the transmission efficiency of carriers, and weaken parasitic absorption of light, thereby ensuring the cell efficiency of TOPCon cells. The solar cell comprises a semiconductor substrate, an ultrathin dielectric layer, a passivation layer, a first electrode and a metal crystal, wherein the semiconductor substrate has a light receiving face and a backlight face which are opposite each other, the ultrathin dielectric layer is located on at least one of the backlight face and the light receiving face of the semiconductor substrate, the passivation layer is located on the ultrathin dielectric layer, the first electrode is located on the passivation layer, and the metal crystal is located in the passivation layer; and the metal crystal comprises a first metal crystal, one end face of the first metal crystal abuts against the ultrathin dielectric layer, and the other end face of the first metal crystal is connected to the first electrode.