1450results about How to "High electron mobility" patented technology

The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate and wherein the third gaseous material is inert with respect to reacting with the first or second gaseous materials.

A zinc oxide (ZnO) field effect transistor exhibits large input amplitude by using a gate insulating layer. A channel layer and the gate insulating layer are sequentially laminated on a substrate. A gate electrode is formed on the gate insulating layer. A source contact and a drain contact are disposed at the both sides of the gate contact and are electrically connected to the channel layer via openings. The channel layer is formed from n-type ZnO. The gate insulating layer is made from aluminum nitride/aluminum gallium nitride (AlN/AlGaN) or magnesium zinc oxide (MgZnO), which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a silicon metal oxide semiconductor field effect transistor (Si-MOS-type FET), resulting in the formation of an inversion layer.

Disclosed is a novel compound useful as a constituent of an organic EL device. Also disclosed is a practical organic EL device using this compound. This organic EL device has low driving voltage, long life, and reduced leakage current. Specifically disclosed is a compound characterized by having at least one structure (1) shown below in a molecule. Structure (1)

A method of fabricating an optoelectronic device, comprising growing an active layer of the device on an oblique surface of a suitable material, wherein the oblique surface comprises a facetted surface. The present invention also discloses a method of fabricating the facetted surfaces. One fabrication process comprises growing an epitaxial layer on a suitable material, etching the epitaxial layer through a mask to form the facets having a specific crystal orientation, and depositing one or more active layers on the facets. Another method comprises growing a layer of material using a lateral overgrowth technique to produce a facetted surface, and depositing one or more active layers on the facetted surfaces. The facetted surfaces are typically semipolar planes.

A method for an enhanced deposition control, comprises forming at least one device within a substrate of a semiconductor wafer, and depositing a silicon nitride layer over the wafer in a reactor at a pressure of at least approximately 104 Pa.

There is provided a thin film transistor (TFT) capable of improving electron mobility and minimizing the occurrence of hysteresis due to traps. The TFT includes a channel layer and a gate insulating layer, wherein the channel layer is made of an oxide semiconductor. In the TFT, the gate insulating layer includes one or more first dielectric layer and a second dielectric layer, and the first dielectric layer has a dielectric constant different from that of the second dielectric layer.

An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

A semiconductor device includes a semiconductor substrate, a first oxide layer on the semiconductor substrate including an element from the semiconductor substrate, and a second oxide layer on the first oxide layer opposite the semiconductor substrate. The second oxide layer includes a stoichiometric, single-phase complex oxide represented by the formula:

A_hB_jO_k, or equivalently (A_mO_n)_a(B_qO_r)_b

• • in which the elemental oxide components, (A_mO_n) and (B_qO_r) are combined so that h=j or, equivalently, ma=bq, and a, b, h, j, k, m, n, q and r are non-zero integers; and wherein: A is an element of the lanthanide rare earth elements of the periodic table or the trivalent elements from cerium to lutetium; and B is an element of the transition metal elements of groups IIIB, IVB or VB of the periodic table.

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10<5>, nitrogen source material partial pressure in a range of from about 1 to about 10<3 >torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10<2 >microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

A panel structure and a manufacturing method thereof are provided. The panel structure is disposed in a display device. The panel structure includes a substrate, several first transistors and second transistors. The substrate has a display circuit and a control circuit. The first transistors are disposed at the display circuit of the substrate. Each of the first transistors has a first active layer. The second transistors are disposed at the control circuit of the substrate. Each of the second transistors has a second active layer. The materials of at least one of the first active layer and the second active layer include ZnO.

A p-type MOSFET of a CMOS structure has a silicon-germanium alloy channel to which a longitudinal compressive stress is applied by embedded epitaxial silicon-germanium alloy source and drain regions comprising a silicon-germanium alloy having a higher concentration of germanium than the channel of the p-type MOSFET. An n-type MOSFET of the CMOS structure has a silicon-germanium alloy channel to which a longitudinal tensile stress is applied by embedded epitaxial silicon source and drain regions comprising silicon. The silicon-germanium alloy channel in the p-type MOSFET provides enhanced hole mobility, while the silicon-germanium alloy channel in the n-type MOSFET provides enhanced electron mobility, thereby providing performance improvement to both the p-type MOSFET and the n-type MOSFET.

A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction IGFET is normally of materially greater gate dielectric thickness than the surface-channel IGFET so as to operate across a greater voltage range than the surface-channel IGFET. Alternatively or additionally, the channel-junction IGFET may conduct current through a field-induced surface channel. A p-channel surface-channel IGFET (102 or 162), which is typically of approximately the same gate-dielectric thickness as the n-channel surface-channel IGFET, is preferably combined with the two n-channel IGFETs to produce a complementary-IGFET structure. A further p-channel IGFET (106, 180, 184, or 192), which is typically of approximately the same gate dielectric thickness as the n-channel channel-junction IGFET, is also preferably included. The further p-channel IGFET can be a surface-channel or channel-junction device.

The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material.

The present invention is related to a semiconductor device with group III-V channel and group IV source-drain and a method for manufacturing the same. Particularly, the energy level density and doping concentration of group III-V materials are increased by the heteroepitaxy of group III-V and group IV materials and the structural design of elements. The method comprises: preparing a substrate; depositing a dummy gate material layer on the substrate and defining a dummy gate from the dummy gate material layer by photolithography; performing doping by self-aligned ion implantation using the dummy gate as a mask and performing activation at high temperature, so as to form source-drain; removing the dummy gate; forming a recess in the substrate between the source-drain pair by etching; forming a channel-containing stacked element in the recess by epitaxy; and forming a gate on the channel-containing stacked element.

Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.

A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si_1-xGe_x; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.

A multi-layer structure for use in the fabrication of integrated circuit devices is adapted for the formation of enhancement mode high electron mobility transistors, depletion mode high electron mobility transistors, and power high electron mobility transistors. The structure has, on a substrate, a channel layer, spacer layer on the channel layer, a first Schottky layer, a second Schottky layer on the first Schottky layer, and a third Schottky layer on the second Schottky layer, and a contact layer on the third Schottky layer. Etch stops are defined intermediate the first and second Schottky layers, intermediate the second and third Schottky layers, and intermediate the third Schottky layer and the contact layer.