42352results about "Semiconductor devices" patented technology

Tailored doping of barrier layers enables balancing of the radiative recombination among the multiple-quantum-wells in III-Nitride light-emitting diodes. This tailored doping enables more symmetric carrier transport and uniform carrier distribution which help to reduce electron leakage and thus reduce the efficiency droop in high-power III-Nitride LEDs. Mitigation of the efficiency droop in III-Nitride LEDs may enable the pervasive market penetration of solid-state-lighting technologies in high-power lighting and illumination.

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

A sensor and method for page-based optical data storage. The sensor includes a partially-reflective mirror, a reflective mirror disposed substantially collinear with and spaced apart from the partially-reflective mirror, and an active layer disposed substantially collinear with and between the partially-reflective mirror and the reflective mirror. The partially-reflective mirror has a first and second side and transmits a portion of light incident on the first side. The reflective mirror reflects light incident on the reflective mirror toward the partially-reflective mirror. The active layer absorbs at least a portion of the light oscillating at the resonant frequency.

A method of manufacturing a circuit package is described that includes connecting a photonic interposer and a second interposer, connecting a die to both the photonic interposer and the second interposer, where the die partially overlaps both the photonic interposer and the second interposer, and connecting an optical element to the photonic interposer.

Ultrasound devices and systems are disclosed in which cooling of an active acoustic element of an ultrasound transducer is achieved via an electrically conductive member that extends beyond a proximal side of the active acoustic element to contact a heat exchanger. The electrically conductive member delivers electrical driving signals to the active acoustic element while conducting heat to the heat exchanger. A region of the proximal surface of the active acoustic element that is free from contact with the electrically conductive member may also absent from contact with a liquid or a solid, thereby facilitating reflection of ultrasound energy. The heat exchanger may include an electrically insulating fluid that contacts the electrically conductive member to remove the heat conducted through the electrically conductive member. The active acoustic element may be a multilayer lateral mode element, and the electrically conductive member may form an electrode of the lateral mode element.

A method for surface defect inspection can comprise obtaining topographical data from one or more portions of a semiconductor element. The semiconductor element can have a surface comprising a dielectric and a plurality of metal pads. The method can further comprise processing the topographical data of the one or more portions of the semiconductor element to determine at least a first property of the plurality of metal pads, computing at least one variability value for the first property, and identifying candidate defects in the one or more portions of the semiconductor element based at least in part on the at least one variability value.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

The invention belongs to the technical field of semiconductors, and discloses a SiC power semiconductor module with low parasitic parameters and a preparation method. Comprising a SiC power semiconductor chip, a SiC power semiconductor chip substrate cushion block, a positive electrode power terminal, a negative electrode power terminal, an output power terminal, a positive electrode side middle layer cushion block, a positive electrode side ceramic decoupling capacitor, a positive electrode side substrate middle layer cushion block, a negative electrode side middle layer cushion block, a negative electrode side ceramic decoupling capacitor and a negative electrode side substrate middle layer cushion block. A first copper-clad ceramic substrate, a third copper-clad ceramic substrate, a fourth copper-clad ceramic substrate, a second copper-clad ceramic substrate, a first commutation loop middle copper layer and a second commutation loop middle copper layer; according to the invention, a commutation path is provided for the SiC power semiconductor device by using the middle layer copper of the laminated copper-clad ceramic substrate, the concept of mutual inductance offset of double commutation loops is innovatively introduced, and the parasitic inductance of the module is further reduced.

A multi-layer display including an upper substrate including light emitting diodes (LEDs) fabricated on a topside of the upper substrate, and LED bonding pads fabricated on a bottomside of the upper substrate. The LED bonding pads being electrically connected to the LEDs through vias extending through the upper substrate. The display also including a lower substrate including LED driver circuits and driver bonding pads fabricated on a topside of the lower substrate. The driver bonding pads being electrically connected to the LED driver circuits, where the LED bonding pads and driver bonding pads are aligned and electrically connected to each other, thereby electrically connecting the LED driver circuits to the LEDs.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention relates to the technical field of chip heat dissipation, and provides an immersed heat dissipation system with liquid nitrogen as a cooling medium and an integrated circuit assembly. In an immersed heat dissipation system with liquid nitrogen as a cooling medium, huge heat generated by a high-power-density chip under an extreme working condition can be efficiently absorbed and taken away under the extremely low working temperature and the large phase change heat absorption capacity, the heat transfer limit of a traditional cooling technology is broken through, and deep cooling of the chip is achieved; meanwhile, the liquid nitrogen is non-conductive and stable in chemical property, the electrical short circuit risk and physical and chemical corrosion problems caused by leakage of the cooling working medium are thoroughly eliminated, and the long-term operation reliability and safety of the immersed heat dissipation system with the liquid nitrogen as the cooling medium are remarkably improved. Therefore, stable operation of the chip under high load is guaranteed, physical damage and performance frequency reduction caused by overheating are avoided, and even favorable conditions are created for safe and efficient operation of the chip under higher working frequency.

An antenna apparatus includes an antenna substrate with opposite first and second surfaces; and a PCB having opposite first and second surfaces. Antenna elements are disposed at the first surface of the antenna substrate. Electrically conductive columns, each having a first end attached to the second surface of the PCB and a second end attached to the second surface of the antenna substrate, secure the PCB to the antenna substrate and provide an electrical interconnect between the PCB and the antenna substrate. RFIC chips are each attached to the second surface of the antenna substrate and are coupled to the antenna elements. At least one circuit element is attached to the first surface of the PCB and electrically coupled to at least one of the RFIC chips through at least one of the electrically conductive columns.

The invention provides a manufacturing method of an MEMS device and the MEMS device, and the manufacturing method comprises the steps: providing a first wafer which is provided with a groove; a protective layer is arranged in the groove; providing a second wafer, and bonding the second wafer and the first wafer to seal the groove to obtain a first cavity; the second wafer is etched to form a comb tooth structure, and the protection layer is used for protecting the comb tooth structure. According to the embodiment of the invention, the protection layer is arranged in the first cavity of the first wafer as a buffer layer, so that when the second wafer is etched to form the comb tooth structure, the plasma backwash in the over-etching stage can be reduced, the comb tooth structure is further protected, the damage to the bottom of the comb tooth caused by the backwash of etching particles is reduced and solved, and the service life of the comb tooth structure is prolonged. Therefore, the mechanical strength and the anti-failure capability of the device are enhanced.

The invention discloses a micro-channel liquid cooling method, device, equipment and medium for heat dissipation of an integrated circuit chip, and the method comprises the steps: collecting temperature data of different depths of the surface and the interior of the chip in real time through a temperature sensor array, an embedded temperature probe and an infrared detector, and generating a three-dimensional temperature field matrix; carrying out region division according to the microchannel physical layout of the chip, mapping a three-dimensional temperature field matrix, and generating a region temperature field matrix; calculating a thermal load change rate of the regional temperature field matrix, and generating a main flow regulation parameter by adopting a PI D algorithm based on the change rate; calculating branch flow adjusting parameters by combining the temperature field matrixes of the adjacent areas and a pre-constructed topological association table, and fusing the main flow adjusting parameters and the branch flow adjusting parameters to generate a flow adjusting quantity instruction. According to the invention, dynamic and accurate regulation and control of chip heat dissipation are realized, and the heat dissipation efficiency is effectively improved.

The invention relates to the technical field of radio frequency integrated circuits and advanced semiconductor packaging, in particular to a multilayer spiral inductor structure based on an RDL process and a preparation method. The preparation method comprises the steps of seed layer deposition, gradient line width coil formation through photoetching and electroplating, alternate dielectric layer deposition, through hole etching to form vertical interconnection copper columns, air bridge forming through a photoresist sacrificial layer process and silicon nitride passivation packaging. Through fan-shaped topological layout, dielectric material collaborative optimization and three-dimensional interconnection structure design, the self-resonant frequency bandwidth is effectively improved, conductor and dielectric loss is reduced, and miniaturization integration and high reliability of high-frequency inductance elements are achieved.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NAND architecture. Multi-bit weight values are stored encoded as sets of threshold voltages for sets of memory cells. A weight value is stored in multiple memory cells on the same word line and connected between a bit line and a source line, each of the memory cells programmed to one of multiple threshold voltages. When multiplying an input value with the weight value, the word line is biased so that, for at least one of the threshold voltages, the memory cell will be in the linear operation region. Input values are encoded as a set of one or more voltage levels applied to a corresponding set of bit lines, each bit line connected memory cells also storing the weight value, connected to the word line, and connected to the source line.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The wireless RF semiconductor system is described for use in wireless communication devices that operate in frequency range from 6 GHz to 100 GHz. The system comprises of at least one RF antenna and at least one active RF component fabricated (or built) on the same semiconductor substrate inside a one single packaged module. The wireless RF semiconductor system is described in a variety of different configurations with its functionality divided up over several single chip circuits. The system simplifies assembly, reduces size and cost, and allows for a quick time to market, while maximizing the RF performance demanded by fixed and mobile 4G, 5G and other wireless standards.

The invention belongs to the technical field of semiconductor device packaging, and discloses a power semiconductor module three-dimensional stacking vertical commutation low-inductance packaging structure. The two vertical commutation structures are stacked and integrated on the same substrate; different from traditional two-dimensional packaging in which all elements are laid on a two-dimensional plane, three-dimensional stacked packaging suitable for power devices is proposed for the first time, and power loops are stacked and integrated; the magnetic fluxes of the stacked power loops are cancelled, so that ultra-low inductance (pH level) integration is realized; under the condition that the areas of the substrates are the same, the capacity of the module is doubled; meanwhile, dynamic current sharing design is considered, and one driving chip simultaneously drives eight GaN chips to realize parallel dynamic current sharing for the first time; the method is suitable for various topological structures including half-bridge structures, full-bridge structures, three-level ANPC structures and the like; the method is suitable for various packaging schemes, including PCB on DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module double-sided parallel PCB on DBC as an example, low-inductance, low-thermal-resistance and high-power-density integration is realized.

Technologies for cooling conformal power delivery structures are disclosed. In one embodiment, an integrated circuit component has a die with a backside power plane mated to it. A lid of the integrated circuit component is mated with the backside power plane, forming a sealed cavity. The lid has an inlet and an outlet, and a channel is defined in the lid for liquid coolant to flow from the inlet, across the backside power plane, and to the outlet. The liquid coolant directly contacts the backside power plane, efficiently removing heat from the backside power plane.

The invention relates to the field of packaging substrates, in particular to a heterogeneous stack-up packaging substrate and a manufacturing method thereof. A glass core plate is arranged in the packaging substrate, and one or more first core plates are arranged between the surface of the packaging substrate and the glass core plate; one or more circuit layers are arranged between the glass core plate and the first core plate; one or more circuit layers are arranged between the first core boards; one or more circuit layers are arranged between the first core board and the surface of the substrate; the packaging substrate is internally provided with a metal column, and the metal column is connected with the circuit layer. Different dielectric materials and different core plates are matched in the manufacturing process of the packaging substrate, so that the problem of warping of the dielectric materials caused by expansion and shrinkage and stress or temperature change in the stacking process can be effectively solved, and the flatness of the large-size substrate in the machining process is effectively ensured. The technology of an upper-layer thin circuit and a lower-layer thick circuit is realized. And the manufacturing feasibility of the large-size packaging substrate is greatly improved.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

The invention provides a preparation method of a package carrier plate, the package carrier plate and a package structure. The preparation method of the package carrier plate comprises the steps that conductive columns and filling materials are placed in through holes; and curing the filling material to form a filling part. The conductive columns do not need to be prepared in the through holes in an electroplating mode, so that the packaging carrier plate with a high aspect ratio can be prepared conveniently, pores generated in the conductive columns due to non-uniform diffusion of electroplating liquid medicine in the through holes can be avoided, and the electrical performance and the reliability of the packaging carrier plate are ensured. Meanwhile, the arrangement of the filling parts can enhance the connection stability between the conductive columns and the substrate.

A substrate 10 has an integrated circuit formed therein and has a pad electrode PD formed on an upper surface thereof and electrically connected to the integrated circuit. An insulating film IF2 is formed on the upper surface of the substrate 10, and an opening OP is formed in the insulating film IF2. A redistribution wiring PW1 is formed in the opening OP and on the insulating film IF2 and is electrically connected to the pad electrode PD. An external connection terminal ET1 electrically connected to the redistribution wiring RW1 is formed on the redistribution wiring RW1. Also, a redistribution wiring RW2 is formed on the insulating film IF2 and is electrically isolated from the redistribution wiring RW1, the pad electrode PD, and the integrated circuit. A plurality of external connection terminals ET2 electrically connected to the redistribution wiring RW2 are formed on the redistribution wiring RW2. The redistribution wiring RW2 and the external connection terminal ET2 constitute a measuring circuit (20) for measuring a resistance value.

A system comprises an encoder configured to compress attribute information and / or spatial for a point cloud and / or a decoder configured to decompress compressed attribute and / or spatial information for the point cloud. To compress the attribute and / or spatial information, the encoder is configured to convert a point cloud into an image based representation. Also, the decoder is configured to generate a decompressed point cloud based on an image based representation of a point cloud. Additionally, an encoder is configured to signal and / or a decoder is configured to receive a supplementary message comprising volumetric tiling information that maps portions of 2D image representations to objects in the point. In some embodiments, characteristics of the object may additionally be signaled using the supplementary message or additional supplementary messages.

A described example includes: a leadframe having a high voltage section and a low voltage section spaced from and electrically isolated from the high voltage section, and a heat slug mounted to the high voltage section. The high voltage section includes an input portion connected to the heat slug at an interior end by a mount portion, and further includes an interior lead portion that is connected to the mount portion by a flexible connect portion. An insulating material mounted to the heat slug provides a die mount area for a semiconductor die having a Hall element that is positioned so that the Hall element is proximate to the heat slug. Mold compound covers the semiconductor die, portions of the leadframe, and portions of the heat slug while a board side surface of the heat slug is exposed forming a thermal pad for a semiconductor device package.