330 results about "Schottky barrier" patented technology

The invention relates to the technical field of sensors, in particular to a high-sensitivity pressure-temperature dual-mode sensor and a preparation method thereof.The preparation method comprises the steps that a carbon nano tube is subjected to acid treatment and then reacts with a silane coupling agent KH550, and an aminated carbon nano tube is prepared; the method comprises the following steps: carrying out hydrothermal reaction on a phosphorus source and a graphene oxide aqueous solution to prepare phosphorus-doped reduced graphene oxide; the preparation method comprises the following steps: synthesizing Au-Ag heterojunction nano dispersion liquid through an Au nano seed method; mixing the three components and carrying out ultrasonic treatment to obtain mixed dispersion liquid; the preparation method comprises the following steps: modifying a PDMS substrate with KH560 and polyethylene glycol diamine to prepare a modified PDMS substrate; and coating the mixed dispersion liquid on a modified substrate to form a sensitive layer, and preparing an electrode to obtain the sensor. The aminated carbon nanotubes and the phosphorus-doped reduced graphene oxide construct a three-dimensional conductive network, so that high-sensitivity pressure detection is realized; the phosphorus-doped reduced graphene oxide and the Au-Ag heterojunction form a Schottky barrier, so that stable temperature sensing is realized; and the modified PDMS and the sensitive layer are strongly combined to improve the mechanical durability.

The invention discloses an N-surface GaN / AlGaN heterojunction transverse JTE diode, and belongs to the technical field of semiconductors, and the diode comprises an epitaxial structure which at least comprises an N-surface unintentionally doped GaN channel layer; the P-type JTE layer, the anode and the cathode are positioned on the surface of the N-surface unintentionally doped GaN channel layer; wherein the anode and the P-type JTE layer are located in an anode region, the P-type JTE layer comprises a first sub-part and a second sub-part which are arranged at an interval, the anode metal layer covers part of the first sub-part, part of the second sub-part and a channel region between the two sub-parts, and the orthographic projection of the cathode in the first direction is annular; the first direction is a direction perpendicular to a plane where the epitaxial structure is located; and the passivation layer covers the surface of the N-surface unintentionally doped GaN channel layer and part of the cathode. By introducing the P-type JTE layer, the equivalent Schottky barrier height of the anode is remarkably improved, and reverse electric leakage is effectively reduced.

A Schottky barrier integrated field effect transistor and a manufacturing method therefor. The field effect transistor comprises: a first conductive type substrate (1); a first conductive type epitaxial layer (2), wherein the first conductive type epitaxial layer (2) comprises second conductive type doped regions (21), and a JFET region (23) is formed between adjacent second conductive type doped regions (21); gate-source isolation structures (3), wherein an accommodating region (4) is formed between adjacent gate-source isolation structures (3); a Schottky barrier layer (5), wherein the Schottky barrier layer (5) is located in the accommodating region (4) and in contact with the JFET region (23); and gates (6), separated from the Schottky barrier layer (5) by means of at least the gate-source isolation structures (3), wherein the thickness of the sides of the gate-source isolation structures (3) close to the Schottky barrier layer (5) is greater than the thickness of the sides of the gate-source isolation structures (3) distant from the Schottky barrier layer (5).

The invention belongs to the technical field of flexible transparent energy storage, and discloses a preparation method and application of a flexible stretchable transparent MXene / AgNWs / PDMS composite film electrode, according to the method, a PDMS substrate film, AgNWs and MXene are assembled layer by layer, and a Schottky barrier is formed between one-dimensional AgNWs and two-dimensional MXene, so that the MXene material is firmly attached to the surface of the AgNWs material, corrosion of the AgNWs can be prevented, and the service life of the flexible stretchable transparent MXene / AgNWs / PDMS composite film electrode is prolonged. According to the MXene / AgNWs / PDMS composite film electrode, the cycle stability of the composite electrode is improved, a 1D / 2D heterostructure can be formed, the electrochemical storage capacity of the MXene / AgNWs / PDMS composite film electrode is effectively improved, and a flexible transparent supercapacitor with high light transmittance, high capacitance and mechanical flexibility perfectly unified is expected to be achieved.

A trench cell structure having Schottky barriers and a preparation method thereof are provided. The trench cell structure includes a silicon substrate. A back metal layer is disposed on a back surface of the silicon substrate. The silicon substrate is heavily doped. A body region, a dielectric layer, and a front metal layer are sequentially disposed on a front surface of the silicon substrate from bottom to top. The drift region is lightly doped. Deep trench regions and a shallow trench region are defined on the body region at intervals. The deep trench regions and the shallow trench region include shielding electrodes and ohmic contact structures. The Schottky contact barriers are disposed between the deep trench regions and the shallow trench region, which reduces anode carrier injection efficiency when the trench cell structure is forwardly conducted, reduces reverse recovery charge, and reduces a reverse recovery time.

The present application relates to a trench-type Schottky barrier diode and a manufacturing method therefor. The trench-type Schottky barrier diode comprises: a substrate (170), having a first conductivity type; a first conductivity type layer (160), located on the substrate (170), the doping concentration of the first conductivity type layer (160) being less than the doping concentration of the substrate (170); a trench structure, extending from the front surface of the first conductivity type layer (160) to the substrate (170), the trench structure comprising a conductive material (140) and further comprising a dielectric layer (130) surrounding the conductive material (140) from the side surface and the bottom surface; a Schottky barrier layer (120), located on the first conductivity type layer (160) and on the trench structure; and a second conductivity type region (150), located below the trench structure, the top of the second conductivity type region (150) being in direct contact with the bottom of the dielectric layer (130), and the bottom of the second conductivity type region (150) being spaced apart from the substrate (170) by part of the first conductivity type layer (160). The present application can maintain reverse withstand voltage characteristics while reducing the on-state forward voltage drop of devices.

A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and formed on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating film covering the inner wall of a trench formed in the drift layer, and a protective film covering the anode electrode, wherein a part of the protective film is embedded in the trench. The part of the protective film is thus embedded in the trench, so that adhesion performance between the anode electrode and protective film is enhanced. This makes it possible to prevent peeling at the boundary between the anode electrode and the protective film.

The present invention relates to a silicon carbide Schottky barrier diode and a manufacturing method thereof, the silicon carbide Schottky barrier diode comprising: a substrate having a first conductivity type; the first epitaxial layer has a first conductive type and is positioned above the substrate; the second epitaxial layer has the first conductive type and is located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is larger than that of the first epitaxial layer; the doped region has a second conductive type and extends downwards from the top of the second epitaxial layer; the silicon carbide Schottky barrier diode is further provided with a groove extending from the top of the doped region to the interior of the doped region. The first conductive type and the second conductive type are opposite; and the Schottky metal layer is positioned on the doped region and is filled in the groove. According to the invention, the VF can be reduced without sacrificing the BV of the device.

The invention discloses a gallium oxide-based Schottky barrier diode and a preparation method thereof. The method comprises the following steps: preparing a gallium oxide substrate; performing oxygen plasma treatment in a reactive ion etching system; feeding the sample into a tubular furnace, and annealing in an air atmosphere; then sending the annealed sample into electron beam evaporation equipment for back metal silver electrode growth; next, the sample is sent into rapid thermal annealing equipment to be annealed in the N2 atmosphere, and ohmic contact is formed; then, under the conditions that the growth speed is 0.01-0.1 nm / s and the vacuum degree is lower than 1 * 10 <-4 > Pa, field plate oxide Al2O3 grows on the surface treatment acting layer of the substrate through electron beam evaporation; and finally growing a metal anode at the top of the device by electron beam evaporation equipment. According to the technical scheme provided by the invention, the problem of preparing the gallium oxide-based Schottky barrier diode with low forward conduction loss under the condition of maintaining high breakdown voltage of the device is solved.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source / drain regions and n-type source / drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source / drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source / drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source / drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for both p-type source / drain regions and n-type source / drain regions.

The invention discloses a polarization-sensitive narrow-band solar blind self-driven photoelectric detector and a preparation method thereof, and belongs to the technical field of semiconductor photoelectric devices. The detector comprises an n-type conductive single Ga2O3 micron wire, a p-type conductive GaN substrate, a PET substrate and a two-dimensional graphene film. According to the device, Ni / Au alloy is selected as a positive electrode, and a two-dimensional graphene film is used as a transparent window of ultraviolet solar blind light and a negative electrode of the device. By means of built-in potential formed by the n-Ga2O3 / p-GaN heterojunction and a Schottky barrier of Ga2O3 / Graphene, high-sensitivity detection of solar-blind ultraviolet light under the self-driving condition is achieved. The device has relatively high responsivity, specific detection rate and external quantum efficiency. The preparation method comprises the following steps: cleaning the GaN substrate, evaporating the Ni / Au electrode, adhering the PET substrate with the channel, transferring the Ga2O3 micron wire to form the heterojunction, and transferring and curing the graphene electrode. The device has the characteristics of polarization sensitivity and low power consumption, and can be applied to the fields of ultraviolet solar blind band encryption communication and environment monitoring.

A semiconductor device including: a plurality of unit cells arranged side-by-side across a top surface of the semiconductor device, and where the plurality of unit cells are of a first type or a second type, each unit cell of the first type includes a first electrode, a second electrode, and a third electrode formed at the top surface of the semiconductor device. The second electrode is arranged to enclose the first electrode. Each of the first and second electrodes are arranged to enclose the third electrode. The unit cells of the first type form high electron mobility transistor (HEMT) cells, and the unit cells of the second type form Schottky Barrier Diode (SBD) cells.

The invention provides a transistor with a programmable horizontal double-floating-gate homojunction. The transistor comprises two floating gate layers which are independent from each other and are composed of multiple layers of graphene; the tunneling layer is positioned above the floating gate layer; the channel layer is positioned above the tunneling layer; the source electrode and the drain electrode are located above the two ends of the channel layer respectively, so that the floating gate layer can achieve regulation and control of source-drain contact, and then it is guaranteed that a floating gate electric field can achieve regulation and control of Schottky barriers of the source electrode and the drain electrode; and the two direct tunneling electrodes are respectively positioned above two ends of the tunneling layer and are not in contact with the channel layer, so as to inject charges into the floating gate layer. The invention also provides a preparation method of the transistor. According to the transistor provided by the invention, a bilateral floating gate is used for regulating and controlling an energy band in contact with two sides, and any one of four junctions (a p-n junction, an n-p junction, a p-p junction and an n-n junction) can be freely formed and switched.

The invention discloses a metal-semiconductor direct current friction nanometer generator based on a depletion mode u-GaN / AlGaN / AlN / GaN high electron mobility transistor. The generator comprises a titanium (Ti) metal friction layer and a depletion mode GaN HEMT friction layer, and direct current is generated through the interface friction volt effect. The core of the invention lies in that high-concentration two-dimensional electron gas (2DEG) and surface state characteristics in the u-GaN / AlGaN / AlN / GaN heterojunction are utilized, and the friction volt effect is combined, so that efficient mechanical energy-electric energy conversion is realized. In the dynamic Schottky contact of the D-GaN HEMT and metal, unbalanced carriers in u-GaN Cap are excited by friction, electrons and holes are separated by a built-in electric field, surface state electrons of u-GaN Cap obtain friction energy to be transited to a conduction band, and a Schottky barrier is overcome to form current; in the sliding process, metal and a semiconductor interact to increase the surface state density, a large number of electrons are excited, chemical bonds are formed, two-dimensional electron gas is formed on an AlN / GaN interface and flows back under a reverse electric field, the electron concentration is maintained, current is continuously generated, and finally direct current is formed in an external circuit.

The technical problem of the present invention is to prevent insulation breakdown caused by charge accumulation in a Schottky barrier diode. This Schottky barrier diode (1) is provided with: a semiconductor substrate (20); a drift layer (30); a field insulating film (80) that covers an outer peripheral region (31B) in the upper surface (31) of the drift layer (30); an anode electrode (40) that is in Schottky contact with a central region (31A) in the upper surface (31) of the drift layer (30) and has an end positioned on the field insulating film (80); and a conductive member (90) in contact with the field insulating film (80) and electrically connected to the semiconductor substrate (20). Consequently, when a reverse voltage is applied, the charge accumulated in the drift layer (30) is relaxed, and thus it is possible to prevent insulation breakdown caused by the accumulation of the charge.

A Schottky barrier tunneling field effect transistor biosensor with a tooth-shaped channel and multiple tunneling regions comprises the tooth-shaped channel, a source electrode is arranged on a protruding part of the tooth-shaped channel, grid electrodes are arranged in a concave part of the tooth-shaped channel and on the two outer sides of the tooth-shaped channel, a biomolecule detection cavity is formed between the grid electrodes and the tooth-shaped channel, and a plurality of tunneling regions are arranged in the biomolecule detection cavity. A gate dielectric layer is arranged at the bottom of the biomolecule detection cavity, and a drain electrode is arranged at the bottom of the tooth-shaped channel; the device is provided with more sources through the channels of the tooth-shaped structure, multi-directional conduction of current is formed, the working speed is increased, the biomolecule detection cavity is oppositely arranged on one sides of the three sources, more Schottky tunneling areas can be generated, the probability of Schottky tunneling of carriers is increased, and the sensitivity of the sensor is improved.

The invention discloses a silicon carbide intelligent power module with voltage and current dual-detection over-current protection, and relates to the technical field of semiconductors. In order to solve the problem that when an existing silicon-based intelligent power module (IPM) is matched with a silicon carbide metal-oxide-semiconductor field effect transistor, due to the fact that the over-current protection response speed is low, interference and false triggering are likely to happen, a dual over-current protection mechanism combining desaturation voltage detection and sub-current detection is adopted. And by mixing and integrating the silicon substrate and the silicon carbide power device, the performance requirements of different application scenes are considered. Three driving control chips, six IGBT chips, six fast recovery diode chips, one SiC MOSFET chip, two silicon carbide Schottky barrier diode chips and one patch sampling resistor are integrated in the module, and all the elements are packaged in the same insulation heat dissipation substrate and lead frame combined structure, so that high integration level, high reliability and fast overcurrent protection are realized; the method can be widely applied to the fields of household appliances, industrial control, new energy and the like.

A Schottky barrier diode, including a first n-type semiconductor layer including a β-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a β-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The β-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.

The invention discloses a high-voltage SIC groove type junction barrier Schottky device structure which comprises a Schottky contact area, the Schottky contact area is provided with a plurality of shielding structures, each shielding structure comprises multiple stages of grooves which are vertically arranged, and a P + masking layer is arranged outside the bottommost groove. By introducing the multi-stage groove, the electrostatic shielding effect of a bottom P + masking layer on Schottky barrier contact is improved, the width of a JFET region is widened, the JBS leakage current of the groove is reduced, and the bulk resistance of the JBS is reduced; the polycrystalline silicon in the trench is connected with the cathode, so that the electrostatic shielding effect during reverse blocking can be enhanced, and the bulk resistance of the JFET region can be reduced during forward conduction.

The Schottky barrier diode of the present invention comprises: an n-type semiconductor substrate; at least one p-type guard ring, which is arranged on the upper surface side of the semiconductor substrate; an anode electrode, which is arranged on the upper surface of the semiconductor substrate; a cathode electrode, which is arranged on the back surface of the semiconductor substrate; and an insulating film, which is arranged on the innermost inner guard ring of the at least one guard ring, the anode electrode being overlapped on the insulating film, the end of the anode electrode being arranged directly above the inner guard ring, the anode electrode being arranged separately from the inner guard ring, and the thickness of the insulating film being greater than or equal to 1.0 μm.

A semiconductor device includes a dual-stage Schottky barrier. The dual-stage Schottky barrier includes a first stage and a second stage. The first stage is formed over a substrate stack and includes an upper layer having a length corresponding to a gate length for the device. The second stage is formed at least partially over the first stage and includes a contact segment having a length less than the gate length.

The invention relates to a compression type direct current triboelectric sensor and a preparation method and application thereof, the sensor comprises a main body and an insulating part for packaging the main body, the main body comprises two metal electrodes arranged oppositely and a dielectric material layer located between the two metal electrodes, the dielectric material layer is formed by laying a granular dielectric material between two metal electrodes, charges lost by electrostatic breakdown are greatly inhibited through an interface Schottky barrier formed by layer-by-layer assembly, and quick response to static pressure and dynamic pressure is realized.

The invention relates to a manufacturing method of a trench Schottky diode with an adjustable forward voltage. A Schottky diode includes a substrate having an active region. The grooves extend into the substrate epitaxial layer, the side walls and the bottom surfaces of the grooves are lined with insulating layers, and the rest part of each groove is filled with polycrystalline silicon (polycrystalline silicon) filler. A doped region having a dopant of the same conductivity type as the semiconductor substrate is implanted in the epitaxial layer at a position between adjacent trenches. A silicide is provided at each polysilicon filler and a Schottky barrier is provided at each doped region. An anode contact of the diode contacts the silicide and the Schottky barrier, and a cathode contact of the diode contacts the lower surface of the substrate. The dopant concentration level of the selected doped region controls the setting of the forward voltage (VF) level of the Schottky diode.

The invention relates to the field of semiconductors, in particular to a silicon carbide MOSFET with low on-resistance and optimized electromagnetism, a high-conductivity region is arranged in a junction field effect transistor region on the side of a Schottky barrier diode, the on-resistance is reduced, the current density uniformity is improved, Schottky barrier diode metal and a source electrode metal electrode are connected through a diversion slope, and the current density uniformity is improved. A junction field effect transistor region is integrated with a grounding metal shielding layer, gate source parasitic capacitance is reduced, inductive coupling is reduced, high-frequency stability is improved, a P-type shielding doping layer is arranged between a source groove and the junction field effect transistor region and between the source groove and an epitaxial layer, double isolation with the metal shielding layer is achieved, and electromagnetic interference is reduced. The high-conductivity region, the diversion slope and the P-type shielding doping layer cooperate to reduce the amplification of short-circuit resistance, prolong the short-circuit tolerance time and avoid the risk of thermal breakdown.

The present disclosure relates to an ESD protection device and a chip. The device comprises: an N-type drift region; a first P-type doped region, which is located in the N-type drift region; a first N-type doped region, which is located in the N-type drift region; a Schottky barrier structure, which comprises a Schottky metal layer, wherein the Schottky metal layer, together with a semiconductor material that comes into contact with the bottom of the Schottky metal layer, forms a Schottky barrier; a P well, which is connected to the N-type drift region; a second N-type doped region, which is at least partially located in the P well; a second P-type doped region, which is at least partially located in the P well; and a gate electrode, which is located above a region between the first N-type doped region and the second N-type doped region, wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer are connected to an anode, and the gate electrode, the second N-type doped region and the second P-type doped region are connected to a cathode. The present disclosure can increase the holding voltage of the ESD protection device, thereby improving the latch-up immunity capability of the ESD protection device.

The application discloses a kind of photodetector based on bottom metal regulation and preparation method thereof, comprising the following steps: substrate surface photoetching two electrode area patterns and metal regulation layer area pattern, electrode and metal regulation layer are evaporated simultaneously in electrode area pattern and metal regulation layer area pattern and remove photoresist, MoS2 film is transferred to electrode and metal regulation layer, after annealing, photodetector based on bottom metal regulation is obtained.The metal regulation layer of the application forms Schottky barrier after contacting with MoS2 film, and built-in electric field perpendicular to channel is introduced through metal regulation layer, to promote the separation of photo-generated carriers in MoS2 device channel; Bottom electrode is protruding compared to substrate, MoS2 channel does not contact with substrate, optimize the bottom interface of MoS2 channel, improve carrier transport efficiency and response speed, compared with original MoS2 device, rise / fall time reaches 7.3 / 47 μs, to realize superfast response.

An electronic device and a manufacturing process of the electronic device, in particular to a method for regulating the Schottky barrier height in a silicon carbide power diode, and to the power diode thereof is provided. An example electronic device comprises: a body of semiconductor material having a surface and an N-type electrical conductivity; switching regions of a P-type electrical conductivity, the switching regions extending into the body starting from the surface; surface portions having the P-type electrical conductivity, extending at the surface between the switching regions; ohmic contact regions at the switching regions; and a contact metal layer above the surface and in direct electrical contact with the surface portions and the ohmic contact regions.

The present application relates to the technical fields of dynamic reverse bias test, and relates to a circuit and a method for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, the circuit comprises a circuit for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, including a gate resistor, a half-bridge topology circuit, a Schottky barrier diode, a differential amplifier and a direct current power supply, the half-bridge topology circuit comprises an upper bridge auxiliary measurement silicon carbide power device, a lower bridge measured sample and a lower bridge sampling resistor, the gate of the auxiliary measurement silicon carbide power device and the gate of the measured sample are respectively connected with a gate drive input signal through the gate resistor; a plurality of Schottky barrier diodes are connected in parallel with the lower bridge sampling resistor to form an active low-pass filter, the non-inverting input and the inverting input of the differential amplifier are respectively connected with the anode and the cathode of the Schottky barrier diode; the present application can effectively filter out current spikes, solve the problem of related high dV / dt current spikes, and ensure the high precision of the leakage current monitoring signal.

The application discloses a low-cost heat-enhanced gallium nitride Schottky barrier diode and a preparation method thereof. The diode comprises a transmission layer, a drift layer arranged on the lower surface of the transmission layer, a positive electrode arranged on the middle area of the lower surface of the drift layer, a negative electrode arranged on the middle area of the upper surface of the transmission layer, a first dielectric layer arranged on the lower surface of the remaining drift layer and the sidewall and part of the lower surface of the positive electrode, a second dielectric layer arranged on the upper surface of the remaining transmission layer and the sidewall and part of the upper surface of the negative electrode, a part of a positive electrode thickening layer arranged on the lower surface of the first dielectric layer and the lower surface of the remaining negative electrode, another part of the positive electrode thickening layer exposed to the first dielectric layer, a heat dissipation substrate arranged on the lower surface of the positive electrode thickening layer and a negative electrode thickening layer arranged on the upper surface of part of the second dielectric layer and the upper surface of the remaining negative electrode. The application realizes a full-vertical gallium nitride Schottky barrier diode with greater forward current and higher heat dissipation capacity.

The present invention relates to a semiconductor device (100) comprising: a plurality of unit cells (120a, 120b) arranged side by side across a top surface of the semiconductor device (100) wherein the plurality of unit cells (120a, 120b) have a first type (120a) or a second type (120b), each of the first type unit cells (120a) includes a first electrode (121), a second electrode (122), and a third electrode (123) formed at the top surface of the semiconductor device (100); the second electrode (122) is arranged so as to surround the first electrode (121); each of the first electrode (121) and the second electrode (122) is arranged so as to surround the third electrode (123); the first type unit cell (120a) forms a high electron mobility transistor (HEMT) cell, and the second type unit cell (120a) forms a high electron mobility transistor (HEMT) cell. The second type of unit cells (120b) form a Schottky barrier diode (SBD) cell, and the second type of unit cells (120b) form a Schottky barrier diode (SBD) cell.