124 results about "Schottky barrier" patented technology

The invention relates to the technical field of sensors, in particular to a high-sensitivity pressure-temperature dual-mode sensor and a preparation method thereof.The preparation method comprises the steps that a carbon nano tube is subjected to acid treatment and then reacts with a silane coupling agent KH550, and an aminated carbon nano tube is prepared; the method comprises the following steps: carrying out hydrothermal reaction on a phosphorus source and a graphene oxide aqueous solution to prepare phosphorus-doped reduced graphene oxide; the preparation method comprises the following steps: synthesizing Au-Ag heterojunction nano dispersion liquid through an Au nano seed method; mixing the three components and carrying out ultrasonic treatment to obtain mixed dispersion liquid; the preparation method comprises the following steps: modifying a PDMS substrate with KH560 and polyethylene glycol diamine to prepare a modified PDMS substrate; and coating the mixed dispersion liquid on a modified substrate to form a sensitive layer, and preparing an electrode to obtain the sensor. The aminated carbon nanotubes and the phosphorus-doped reduced graphene oxide construct a three-dimensional conductive network, so that high-sensitivity pressure detection is realized; the phosphorus-doped reduced graphene oxide and the Au-Ag heterojunction form a Schottky barrier, so that stable temperature sensing is realized; and the modified PDMS and the sensitive layer are strongly combined to improve the mechanical durability.

The invention provides a transistor with a programmable horizontal double-floating-gate homojunction. The transistor comprises two floating gate layers which are independent from each other and are composed of multiple layers of graphene; the tunneling layer is positioned above the floating gate layer; the channel layer is positioned above the tunneling layer; the source electrode and the drain electrode are located above the two ends of the channel layer respectively, so that the floating gate layer can achieve regulation and control of source-drain contact, and then it is guaranteed that a floating gate electric field can achieve regulation and control of Schottky barriers of the source electrode and the drain electrode; and the two direct tunneling electrodes are respectively positioned above two ends of the tunneling layer and are not in contact with the channel layer, so as to inject charges into the floating gate layer. The invention also provides a preparation method of the transistor. According to the transistor provided by the invention, a bilateral floating gate is used for regulating and controlling an energy band in contact with two sides, and any one of four junctions (a p-n junction, an n-p junction, a p-p junction and an n-n junction) can be freely formed and switched.

The invention discloses a silicon carbide intelligent power module with voltage and current dual-detection over-current protection, and relates to the technical field of semiconductors. In order to solve the problem that when an existing silicon-based intelligent power module (IPM) is matched with a silicon carbide metal-oxide-semiconductor field effect transistor, due to the fact that the over-current protection response speed is low, interference and false triggering are likely to happen, a dual over-current protection mechanism combining desaturation voltage detection and sub-current detection is adopted. And by mixing and integrating the silicon substrate and the silicon carbide power device, the performance requirements of different application scenes are considered. Three driving control chips, six IGBT chips, six fast recovery diode chips, one SiC MOSFET chip, two silicon carbide Schottky barrier diode chips and one patch sampling resistor are integrated in the module, and all the elements are packaged in the same insulation heat dissipation substrate and lead frame combined structure, so that high integration level, high reliability and fast overcurrent protection are realized; the method can be widely applied to the fields of household appliances, industrial control, new energy and the like.

A Schottky barrier diode, including a first n-type semiconductor layer including a β-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a β-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The β-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.

The invention relates to a manufacturing method of a trench Schottky diode with an adjustable forward voltage. A Schottky diode includes a substrate having an active region. The grooves extend into the substrate epitaxial layer, the side walls and the bottom surfaces of the grooves are lined with insulating layers, and the rest part of each groove is filled with polycrystalline silicon (polycrystalline silicon) filler. A doped region having a dopant of the same conductivity type as the semiconductor substrate is implanted in the epitaxial layer at a position between adjacent trenches. A silicide is provided at each polysilicon filler and a Schottky barrier is provided at each doped region. An anode contact of the diode contacts the silicide and the Schottky barrier, and a cathode contact of the diode contacts the lower surface of the substrate. The dopant concentration level of the selected doped region controls the setting of the forward voltage (VF) level of the Schottky diode.

The present disclosure relates to an ESD protection device and a chip. The device comprises: an N-type drift region; a first P-type doped region, which is located in the N-type drift region; a first N-type doped region, which is located in the N-type drift region; a Schottky barrier structure, which comprises a Schottky metal layer, wherein the Schottky metal layer, together with a semiconductor material that comes into contact with the bottom of the Schottky metal layer, forms a Schottky barrier; a P well, which is connected to the N-type drift region; a second N-type doped region, which is at least partially located in the P well; a second P-type doped region, which is at least partially located in the P well; and a gate electrode, which is located above a region between the first N-type doped region and the second N-type doped region, wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer are connected to an anode, and the gate electrode, the second N-type doped region and the second P-type doped region are connected to a cathode. The present disclosure can increase the holding voltage of the ESD protection device, thereby improving the latch-up immunity capability of the ESD protection device.

The present application relates to the technical fields of dynamic reverse bias test, and relates to a circuit and a method for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, the circuit comprises a circuit for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, including a gate resistor, a half-bridge topology circuit, a Schottky barrier diode, a differential amplifier and a direct current power supply, the half-bridge topology circuit comprises an upper bridge auxiliary measurement silicon carbide power device, a lower bridge measured sample and a lower bridge sampling resistor, the gate of the auxiliary measurement silicon carbide power device and the gate of the measured sample are respectively connected with a gate drive input signal through the gate resistor; a plurality of Schottky barrier diodes are connected in parallel with the lower bridge sampling resistor to form an active low-pass filter, the non-inverting input and the inverting input of the differential amplifier are respectively connected with the anode and the cathode of the Schottky barrier diode; the present application can effectively filter out current spikes, solve the problem of related high dV / dt current spikes, and ensure the high precision of the leakage current monitoring signal.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

To provide a two-dimension photosensor which can be manufactured at a low cost in a thin film transistor plant and covers a relatively wide two-dimension plane.SOLUTION: The two-dimensional photosensor 100 includes a plurality of photodiodes arranged, each photodiode including a stack of a first metal electrode 11, a first semiconductor layer 12, a first ohmic contact layer 13, and a first transparent electrode 16, the first semiconductor layer 12 and the first ohmic contact layer 13 being disposed between the first metal electrode 11 and the first transparent electrode 16, A Schottky barrier is provided on an interface between the first semiconductor layer 12 and the first metal electrode 11 or an interface between the first semiconductor layer 12 and the first transparent electrode 16, and light incident from the side of the first transparent electrode 16 toward the first semiconductor layer 12 is sensed.SELECTED DRAWING: Figure 6

The invention discloses a method for assisting hydrogenation of Ga2O3 by Pd and application, mainly solving the problem of damage to materials in the existing gallium oxide hydrogenation preparation process, and the method is implemented by the following steps: preparing Pd metal on a gallium oxide sample by a sputtering or electron beam evaporation method; placing the Pd / Ga2O3 sample in a closed cavity with the air pressure smaller than or equal to 10 Pa, introducing mixed gas containing 0.1%-100% of hydrogen, catalyzing the hydrogen to be decomposed and sucked into Pd crystal lattices at low temperature to obtain a Pd / Ga2O3 sample in which Pd metal adsorbs hydrogen atoms, and performing laser annealing and annealing heat treatment on the Pd / Ga2O3 sample to enable the hydrogen atoms to be diffused into gallium oxide so as to obtain the gallium oxide. A Pd / Ga2O3 sample with hydrogen atoms entering the gallium oxide is obtained; and removing Pd metal on the sample by a chemical etching or physical method to obtain the hydrogenated gallium oxide. While the doping effectiveness is improved, the hydrogenated gallium oxide is not damaged, and the method can be used for manufacturing Schottky barrier diodes, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and deep ultraviolet photoelectric detectors.

A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.

The present application has an object to prevent insulation breakdown caused by misalignment of a trench and a field insulation layer in a Schottky barrier diode of gallium oxide. The Schottky barrier diode includes an anode electrode (40) in Schottky contact with a drift layer (30), a cathode electrode (50) in ohmic contact with a semiconductor substrate (20), an insulation film (63) covering an inner wall of a trench (61) provided in the drift layer (30), a metal film (64) covering the inner wall of the trench (61) through the insulation film (63) and electrically connected to the anode electrode (40), and a field insulation layer (70). The field insulation layer (70) includes a first portion (71) between an upper surface (31) of the drift layer (30) and the anode electrode (40) and a second portion (72) covering the inner wall of the trench (61) through the metal film (64) and the insulation film (63). Thus, even if the alignment of the trench (61) and the field insulation layer (70) is misaligned, insulation breakdown does not occur.

A Schottky diode includes a substrate with an active region. Sidewall and bottom surfaces of trench extending into an epitaxial layer of the substrate are lined with an insulating layer, and the remainder of each trench is filled with a polycrystalline silicon (polysilicon) fill. A doped region having the same conductivity type dopant as the semiconductor substrate is implanted in the epitaxial layer at locations between adjacent trenches. A silicide is provided at each polysilicon fill and a Schottky barrier is provided at each doped region. An anode contact for the diode contacts the silicide and Schottky barrier, and a cathode contact for the diode contacts a lower surface of the substrate. The selection of a dopant concentration level for the doped region controls setting of a forward voltage VF level for the Schottky diode.

A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

The application discloses a kind of based on van der waals contact vertical p-n junction diode and preparation method, semiconductor device.The two-dimensional material vertical p-n junction diode includes metal top electrode, p-type two-dimensional material, n-type two-dimensional material and bottom electrode from top to bottom vertically stacked, wherein, the material between adjacent two layers is formed by van der waals force van der waals contact, so that the material of adjacent two layers mutually adhere and do not fall off.Based on the interface of vertical p-n junction diode of van der waals contact is flat and has no defect and lattice damage, avoid the damage of traditional evaporation method to two-dimensional material lattice, make that the schottky barrier and tunneling current caused by fermi pinning in device significantly reduce, to greatly improve the rectification performance of the device.The application solves the technical problem that existing two-dimensional material vertical p-n junction device has schottky barrier and larger tunneling current.

The application relates to a second-order adjustable transistor with a time-domain programmable characteristic and a preparation method thereof. The transistor comprises an insulator substrate, a gate bottom electrode, a ferroelectric blocking layer, a floating gate layer, a tunneling layer, a channel layer and a source and a drain, wherein the blocking layer is a ferroelectric material layer with an electrically programmable polarization state. Through the coupling of the ferroelectric polarization effect and the floating gate charge capture mechanism, the Schottky barrier height at the floating gate interface is regulated, thereby changing the release dynamics of photo-generated carriers, realizing the adjustable relaxation time of photo-generated carriers in the millisecond to second range, and realizing the time-domain programmable regulation of multiple different time factors without the need of a continuous external bias voltage. The device breaks through the limitation of a single time factor of a neuromorphic device and is suitable for in-situ computing scenes such as multi-speed motion perception.

This invention relates to the field of laser technology and discloses a vertical-cavity surface-emitting laser and its fabrication method. The fabrication method includes: providing a substrate layer; sequentially stacking a first mirror layer, a first confinement layer, an active layer, and a second confinement layer on the substrate layer; forming a ring-shaped nitride barrier layer on a portion of the surface of the second confinement layer, with a first aperture formed in the central region; forming a second mirror layer on the nitride barrier layer, the second mirror layer filling the first aperture and forming a second aperture corresponding to the first aperture on a side opposite to the nitride barrier layer; the work function of the nitride barrier layer is higher than that of the second confinement layer and the second mirror layer, so that the nitride barrier layer forms a first Schottky barrier and a second Schottky barrier. In this invention, the nitride barrier layer blocks the lateral path with an interface energy barrier and widens the vertical path with a geometric structure, forcing vertical current transmission, while also possessing high thermal conductivity, significantly improving reliability at high power.

The invention relates to the technical field of semiconductor power devices, and discloses a method for optimizing a beta-Ga2O3 Schottky diode interface through hydrogen treatment, and the method comprises the steps: providing a beta-Ga2O3 Schottky diode, the beta-Ga2O3 Schottky diode comprises a beta-Ga2O3 semiconductor substrate, an n-type drift layer located on the beta-Ga2O3 semiconductor substrate, a Schottky anode located on the n-type drift layer and formed by stacking a nickel layer and a gold layer, and an edge terminal surrounding the Schottky anode. The beta-Ga2O3 Schottky diode is subjected to hydrogen treatment in a hydrogen-containing environment, so that hydrogen atoms are preferentially gathered and act on a contact interface of the nickel layer and the n-type drift layer, and the interface state of the interface is passivated. According to the invention, hydrogen treatment passivates interface defects, the Schottky barrier height and ideal factors can be reduced, the forward current density can be improved, and the on-resistance can be reduced, so that the overall electrical performance and energy conversion efficiency of the device can be improved.

This invention provides a Schottky diode structure and an electronic device. The structure includes a substrate and a first doped region formed therein. The first doped region includes a cathode active region and an anode active region. A second N-type doped region and a cathode metallization layer are sequentially formed within the cathode active region. The anode active region includes a first region and an anode metallization layer formed thereon. A metallization barrier layer is formed on the substrate surrounding the first region and at least covers a portion of the anode active region adjacent to the cathode active region. By providing a metallization barrier layer on the substrate between the cathode and anode of the Schottky diode and covering a portion of the anode active region, the electric field distribution at the edge of the Schottky barrier can be effectively optimized and surface leakage current can be suppressed. This effectively improves the reverse breakdown voltage without increasing the anode-cathode spacing or affecting the forward conduction performance, and saves device area and cost.

The invention relates to a semiconductor device (100) comprising: a die layer (110) comprising a top surface and a bottom surface opposite the top surface; the die layer (110) forms a plurality of unit cells (120) arranged side by side across the top surface of the die layer (110), where each unit cell (120) includes a first type of sub-cells (120a) and a second type of sub-cells (120b) integrated in the unit cell (120); a first type sub-cell (120a) including a first electrode (121), a second electrode (122) and a third electrode (123) formed at the top surface of the die layer (110), the first electrode of the three electrodes (121, 122, 123) being arranged to surround the second electrode of the three electrodes (121, 122, 123); the first electrode and the second electrode of the three electrodes (121, 122, 123) are arranged so as to surround a third electrode of the three electrodes (121, 122, 123); the first type of sub unit cells (120a) form a high electron mobility transistor (HEMT) unit cell, and the second type of sub unit cells (120a) form a high electron mobility transistor (HEMT) unit cell. The second type of sub unit cells (120b) form a Schottky barrier diode (SBD) unit cell, and the second type of sub unit cells (120b) form a Schottky barrier diode (SBD) unit cell.

NON-VOLATILE TRANSISTOR, ASSEMBLY OF NON-VOLATILE TRANSISTORS AND MATRIX OF NON-VOLATILE TRANSISTORS The invention relates to a non-volatile transistor (10) comprising a ferroelectric semiconductor layer (11) comprising a ferroelectric domain (12) exhibiting a spontaneous electrical bias (13) capable of taking a plurality of distinct states, a source (14), a gate (15) and a drain (16).The source (14), gate (15), and drain (16) are spaced apart and arranged such that an electrical potential applied between the source (14) and the gate (15) applies an electric field to the ferroelectric domain (12). The drain (16) is in electrical contact with the ferroelectric layer (11). The source (14) forms, with the ferroelectric layer (11), a Schottky barrier (17) at an interface between the source (14) and the ferroelectric layer (11). This barrier has an electrical resistance that is a function of the electrical bias (13). The transistor is such that the ferroelectric semiconductor layer (11) is degenerate at the interface between the source (14) and the ferroelectric layer (11), and the ferroelectric semiconductor layer (11) has an electrical conductivity independent of the spontaneous bias (13). Figure to be published with the abbreviation: Figure 1.

The semiconductor device (1) is a chip-scale semiconductor device (1) that is square in plan view, and is provided with a semiconductor layer (40), a vertical MOS transistor (10) formed on the semiconductor layer (40), and a Schottky barrier diode (20) in which the semiconductor layer (40) functions as an anode or a cathode. A first pad (51), a second pad (52), a third pad (53), and a fourth pad (54) are provided on the upper surface of a semiconductor device (1), and the center of the first pad (51) and the center of the third pad (53) are located on one diagonal line of the semiconductor device (1) in a plan view of the semiconductor device (1). The center of the second pad (52) and the center of the fourth pad (54) are located on the other diagonal line of the semiconductor device (1), and the first pad (51), the second pad (52), the third pad (53), and the fourth pad (54) are circles having the same diameter.

The invention provides a solar cell and a manufacturing method thereof. The solar cell comprises a substrate; the epitaxial structure is arranged on the surface of one side of the substrate; the ohmic contact layer is arranged on the surface, deviating from the substrate, of the epitaxial structure; the grid line electrode is in contact with the ohmic contact layer; the back electrode is arranged on the surface of one side, deviating from the epitaxial structure, of the substrate; wherein the ohmic contact layer comprises a composite stacked structure formed by a phosphide layer and an arsenide layer. Through the arrangement, the conduction band bottom of the phosphide layer is higher than the arsenide layer, and an electron barrier (delta Ec) is formed at the interface of the phosphide layer and the arsenide layer; heavy doping is carried out on the ohmic contact layer, so that a Schottky barrier between the grid line electrode and the phosphide layer and a heterojunction barrier (delta Ec) between the phosphide layer and the arsenide layer become thin barriers capable of being tunneled by electrons due to narrowing of a depletion region, and overall low-resistance ohmic contact is achieved.

The invention discloses an epitaxial Schottky junction beta radiation voltage conversion device and a preparation method thereof. The epitaxial Schottky junction beta radiation voltage conversion device comprises a lower electrode metal layer, a lower electrode diffusion barrier layer, a lower electrode adhesion metal layer, an N + type heavily doped layer, an N + type substrate layer, an epitaxial P type silicon layer, a Schottky barrier metal layer, a passivation layer and a radioactive isotope source which are sequentially stacked from bottom to top. The upper electrode metal layer is embedded into the passivation layer and arranged along the periphery of the radioactive isotope source, and the thickness of the upper electrode metal layer is larger than that of the passivation layer; the device obtained by the invention has the characteristics of high short-circuit current density, high carrier collection efficiency, low energy loss, high stability, long service life and the like, the preparation method is simple, the cost is controllable, and the device is suitable for batch production.

This invention discloses an electrocatalyst with enhanced catalytic performance through an ohmic contact and its applications. A NiMo alloy is anchored on the surface of a semiconductor NiCuP microflower using electrodeposition. By precisely controlling the work function matching between NiMo and NiCuP, an ohmic contact heterointerface is successfully constructed. This effectively eliminates the Schottky barrier at the heterostructure interface and removes the energy barrier for interfacial charge transport, thereby significantly optimizing the intrinsic conductivity of the catalyst and accelerating the transfer of electrons from the catalyst interior to the surface active sites. Benefiting from this efficient interfacial electron transport channel, the catalyst exhibits significantly enhanced catalytic activity in the cathode hydrogen evolution reaction. In the anodic half-reaction, a more thermodynamically favorable FOR is used instead of OER, enabling energy-saving hydrogen production by coupling the cathode HER at a lower battery voltage. Simultaneously, at the anode, furfural, a biomass-derived platform molecule, is efficiently converted into high-value-added furoic acid.

The invention relates to an ESD (Electro-Static Discharge) protection device and a chip. The device comprises an N-type drift region; the first P-type doped region is located in the N-type drift region; the first N-type doped region is located in the N-type drift region; the Schottky barrier structure comprises a Schottky metal layer, and the Schottky metal layer and the semiconductor material making contact with the bottom of the Schottky metal layer form a Schottky barrier; the P well is connected with the N-type drift region; the second N-type doped region is at least partially located in the P well; at least part of the second P-type doped region is located in the P well; the grid electrode is positioned above a region between the first N-type doped region and the second N-type doped region; wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer are connected with the anode, and the grid electrode, the second N-type doped region and the second P-type doped region are connected with the cathode. According to the ESD protection device, the maintaining voltage of the ESD protection device can be increased, so that the latch-up resistance of the ESD protection device is improved.

This application discloses a method for manufacturing a converter in a nuclear battery and a nuclear battery, applicable to the field of nuclear batteries. The method involves firstly, in a first vacuum environment, performing a first plasma treatment on the surface of a diamond epitaxial layer using argon plasma; then, in the same first vacuum environment, performing a second plasma treatment on the surface of the diamond epitaxial layer using oxygen plasma; subsequently, in a second vacuum environment, transferring the diamond epitaxial layer treated with the second plasma to a spraying chamber; and finally, in the spraying chamber, forming a Schottky contact layer on the surface of the diamond epitaxial layer using a magnetron spraying method. Thus, on the one hand, the composite plasma treatment process on the surface of the diamond epitaxial layer enhances the adhesion of the Schottky contact metal to the diamond surface, enabling the formation of a diamond converter with a stable Schottky barrier.

A Schottky barrier diode includes a SiC substrate, a GaN buffer layer, a first unintentionally doped GaN layer, an AlN layer, an AlGaN layer, a second unintentionally doped GaN layer, a p-GaN layer doped with Mg, and a cathode and an anode, each in direct contact with the first unintentionally doped GaN layer, the AlN layer, the AlGaN layer, the second unintentionally doped GaN layer, and the p-GaN layer. The anode has a length LA along the p-GaN layer, the cathode has a length LC along the p-GaN layer, and the anode and the cathode are separated by a distance LAC. An outer surface of the p-GaN layer defines n portions, each portion having a length LTn extending along the p-GaN layer between the cathode and the anode and defining an array Tn of activated p-GaN regions. Each element in array Tn is separated by a passivated p-GaN region.

The invention discloses a circuit structure for realizing IGBT follow current and on-state voltage drop extraction by multiplexing Cascode diodes, and belongs to the technical field of power semiconductor devices. The circuit structure comprises a cascade diode structure connected in parallel between a collector electrode and an emitter electrode of an IGBT to be tested; the low-voltage clamping circuit is connected in parallel with the two ends of the low-voltage silicon Schottky barrier diode in the structure; the cascode diode structure is formed by connecting a high-voltage normally-on silicon carbide junction field effect transistor and a low-voltage silicon Schottky barrier diode in a cascode manner; the low-voltage clamping circuit consists of a resistor and two voltage stabilizing diodes which are reversely connected in series; when the IGBT is turned off, the high-voltage blocking function is automatically achieved, when the IGBT is turned on, a follow current path is automatically formed, a signal corresponding to the on-state voltage drop of the IGBT is synchronously output from the low-voltage clamping circuit, and meanwhile the functions of a follow current diode and an on-state voltage measuring circuit are achieved. According to the invention, the circuit structure is simplified, the cost and the loss are reduced, and the high-speed and high-precision measurement requirements of the on-state voltage drop of the IGBT are met.