228 results about "Schottky barrier" patented technology

The invention relates to the technical field of sensors, in particular to a high-sensitivity pressure-temperature dual-mode sensor and a preparation method thereof.The preparation method comprises the steps that a carbon nano tube is subjected to acid treatment and then reacts with a silane coupling agent KH550, and an aminated carbon nano tube is prepared; the method comprises the following steps: carrying out hydrothermal reaction on a phosphorus source and a graphene oxide aqueous solution to prepare phosphorus-doped reduced graphene oxide; the preparation method comprises the following steps: synthesizing Au-Ag heterojunction nano dispersion liquid through an Au nano seed method; mixing the three components and carrying out ultrasonic treatment to obtain mixed dispersion liquid; the preparation method comprises the following steps: modifying a PDMS substrate with KH560 and polyethylene glycol diamine to prepare a modified PDMS substrate; and coating the mixed dispersion liquid on a modified substrate to form a sensitive layer, and preparing an electrode to obtain the sensor. The aminated carbon nanotubes and the phosphorus-doped reduced graphene oxide construct a three-dimensional conductive network, so that high-sensitivity pressure detection is realized; the phosphorus-doped reduced graphene oxide and the Au-Ag heterojunction form a Schottky barrier, so that stable temperature sensing is realized; and the modified PDMS and the sensitive layer are strongly combined to improve the mechanical durability.

The present invention relates to a silicon carbide Schottky barrier diode and a manufacturing method thereof, the silicon carbide Schottky barrier diode comprising: a substrate having a first conductivity type; the first epitaxial layer has a first conductive type and is positioned above the substrate; the second epitaxial layer has the first conductive type and is located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is larger than that of the first epitaxial layer; the doped region has a second conductive type and extends downwards from the top of the second epitaxial layer; the silicon carbide Schottky barrier diode is further provided with a groove extending from the top of the doped region to the interior of the doped region. The first conductive type and the second conductive type are opposite; and the Schottky metal layer is positioned on the doped region and is filled in the groove. According to the invention, the VF can be reduced without sacrificing the BV of the device.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source / drain regions and n-type source / drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source / drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source / drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source / drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source / drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source / drain region. This reduces the contact resistance for both p-type source / drain regions and n-type source / drain regions.

A semiconductor device including: a plurality of unit cells arranged side-by-side across a top surface of the semiconductor device, and where the plurality of unit cells are of a first type or a second type, each unit cell of the first type includes a first electrode, a second electrode, and a third electrode formed at the top surface of the semiconductor device. The second electrode is arranged to enclose the first electrode. Each of the first and second electrodes are arranged to enclose the third electrode. The unit cells of the first type form high electron mobility transistor (HEMT) cells, and the unit cells of the second type form Schottky Barrier Diode (SBD) cells.

The invention provides a transistor with a programmable horizontal double-floating-gate homojunction. The transistor comprises two floating gate layers which are independent from each other and are composed of multiple layers of graphene; the tunneling layer is positioned above the floating gate layer; the channel layer is positioned above the tunneling layer; the source electrode and the drain electrode are located above the two ends of the channel layer respectively, so that the floating gate layer can achieve regulation and control of source-drain contact, and then it is guaranteed that a floating gate electric field can achieve regulation and control of Schottky barriers of the source electrode and the drain electrode; and the two direct tunneling electrodes are respectively positioned above two ends of the tunneling layer and are not in contact with the channel layer, so as to inject charges into the floating gate layer. The invention also provides a preparation method of the transistor. According to the transistor provided by the invention, a bilateral floating gate is used for regulating and controlling an energy band in contact with two sides, and any one of four junctions (a p-n junction, an n-p junction, a p-p junction and an n-n junction) can be freely formed and switched.

The technical problem of the present invention is to prevent insulation breakdown caused by charge accumulation in a Schottky barrier diode. This Schottky barrier diode (1) is provided with: a semiconductor substrate (20); a drift layer (30); a field insulating film (80) that covers an outer peripheral region (31B) in the upper surface (31) of the drift layer (30); an anode electrode (40) that is in Schottky contact with a central region (31A) in the upper surface (31) of the drift layer (30) and has an end positioned on the field insulating film (80); and a conductive member (90) in contact with the field insulating film (80) and electrically connected to the semiconductor substrate (20). Consequently, when a reverse voltage is applied, the charge accumulated in the drift layer (30) is relaxed, and thus it is possible to prevent insulation breakdown caused by the accumulation of the charge.

The invention discloses a silicon carbide intelligent power module with voltage and current dual-detection over-current protection, and relates to the technical field of semiconductors. In order to solve the problem that when an existing silicon-based intelligent power module (IPM) is matched with a silicon carbide metal-oxide-semiconductor field effect transistor, due to the fact that the over-current protection response speed is low, interference and false triggering are likely to happen, a dual over-current protection mechanism combining desaturation voltage detection and sub-current detection is adopted. And by mixing and integrating the silicon substrate and the silicon carbide power device, the performance requirements of different application scenes are considered. Three driving control chips, six IGBT chips, six fast recovery diode chips, one SiC MOSFET chip, two silicon carbide Schottky barrier diode chips and one patch sampling resistor are integrated in the module, and all the elements are packaged in the same insulation heat dissipation substrate and lead frame combined structure, so that high integration level, high reliability and fast overcurrent protection are realized; the method can be widely applied to the fields of household appliances, industrial control, new energy and the like.

A Schottky barrier diode, including a first n-type semiconductor layer including a β-Ga2O3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a β-Ga2O3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The β-Ga2O3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5° from a (010) plane.

A semiconductor device includes a dual-stage Schottky barrier. The dual-stage Schottky barrier includes a first stage and a second stage. The first stage is formed over a substrate stack and includes an upper layer having a length corresponding to a gate length for the device. The second stage is formed at least partially over the first stage and includes a contact segment having a length less than the gate length.

The invention relates to a manufacturing method of a trench Schottky diode with an adjustable forward voltage. A Schottky diode includes a substrate having an active region. The grooves extend into the substrate epitaxial layer, the side walls and the bottom surfaces of the grooves are lined with insulating layers, and the rest part of each groove is filled with polycrystalline silicon (polycrystalline silicon) filler. A doped region having a dopant of the same conductivity type as the semiconductor substrate is implanted in the epitaxial layer at a position between adjacent trenches. A silicide is provided at each polysilicon filler and a Schottky barrier is provided at each doped region. An anode contact of the diode contacts the silicide and the Schottky barrier, and a cathode contact of the diode contacts the lower surface of the substrate. The dopant concentration level of the selected doped region controls the setting of the forward voltage (VF) level of the Schottky diode.

The present disclosure relates to an ESD protection device and a chip. The device comprises: an N-type drift region; a first P-type doped region, which is located in the N-type drift region; a first N-type doped region, which is located in the N-type drift region; a Schottky barrier structure, which comprises a Schottky metal layer, wherein the Schottky metal layer, together with a semiconductor material that comes into contact with the bottom of the Schottky metal layer, forms a Schottky barrier; a P well, which is connected to the N-type drift region; a second N-type doped region, which is at least partially located in the P well; a second P-type doped region, which is at least partially located in the P well; and a gate electrode, which is located above a region between the first N-type doped region and the second N-type doped region, wherein the first P-type doped region, the first N-type doped region and the Schottky metal layer are connected to an anode, and the gate electrode, the second N-type doped region and the second P-type doped region are connected to a cathode. The present disclosure can increase the holding voltage of the ESD protection device, thereby improving the latch-up immunity capability of the ESD protection device.

The application discloses a kind of photodetector based on bottom metal regulation and preparation method thereof, comprising the following steps: substrate surface photoetching two electrode area patterns and metal regulation layer area pattern, electrode and metal regulation layer are evaporated simultaneously in electrode area pattern and metal regulation layer area pattern and remove photoresist, MoS2 film is transferred to electrode and metal regulation layer, after annealing, photodetector based on bottom metal regulation is obtained.The metal regulation layer of the application forms Schottky barrier after contacting with MoS2 film, and built-in electric field perpendicular to channel is introduced through metal regulation layer, to promote the separation of photo-generated carriers in MoS2 device channel; Bottom electrode is protruding compared to substrate, MoS2 channel does not contact with substrate, optimize the bottom interface of MoS2 channel, improve carrier transport efficiency and response speed, compared with original MoS2 device, rise / fall time reaches 7.3 / 47 μs, to realize superfast response.

The present application relates to the technical fields of dynamic reverse bias test, and relates to a circuit and a method for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, the circuit comprises a circuit for detecting dynamic leakage current in dynamic reverse bias of silicon carbide power devices, including a gate resistor, a half-bridge topology circuit, a Schottky barrier diode, a differential amplifier and a direct current power supply, the half-bridge topology circuit comprises an upper bridge auxiliary measurement silicon carbide power device, a lower bridge measured sample and a lower bridge sampling resistor, the gate of the auxiliary measurement silicon carbide power device and the gate of the measured sample are respectively connected with a gate drive input signal through the gate resistor; a plurality of Schottky barrier diodes are connected in parallel with the lower bridge sampling resistor to form an active low-pass filter, the non-inverting input and the inverting input of the differential amplifier are respectively connected with the anode and the cathode of the Schottky barrier diode; the present application can effectively filter out current spikes, solve the problem of related high dV / dt current spikes, and ensure the high precision of the leakage current monitoring signal.

The application discloses a low-cost heat-enhanced gallium nitride Schottky barrier diode and a preparation method thereof. The diode comprises a transmission layer, a drift layer arranged on the lower surface of the transmission layer, a positive electrode arranged on the middle area of the lower surface of the drift layer, a negative electrode arranged on the middle area of the upper surface of the transmission layer, a first dielectric layer arranged on the lower surface of the remaining drift layer and the sidewall and part of the lower surface of the positive electrode, a second dielectric layer arranged on the upper surface of the remaining transmission layer and the sidewall and part of the upper surface of the negative electrode, a part of a positive electrode thickening layer arranged on the lower surface of the first dielectric layer and the lower surface of the remaining negative electrode, another part of the positive electrode thickening layer exposed to the first dielectric layer, a heat dissipation substrate arranged on the lower surface of the positive electrode thickening layer and a negative electrode thickening layer arranged on the upper surface of part of the second dielectric layer and the upper surface of the remaining negative electrode. The application realizes a full-vertical gallium nitride Schottky barrier diode with greater forward current and higher heat dissipation capacity.

The present invention relates to a semiconductor device (100) comprising: a plurality of unit cells (120a, 120b) arranged side by side across a top surface of the semiconductor device (100) wherein the plurality of unit cells (120a, 120b) have a first type (120a) or a second type (120b), each of the first type unit cells (120a) includes a first electrode (121), a second electrode (122), and a third electrode (123) formed at the top surface of the semiconductor device (100); the second electrode (122) is arranged so as to surround the first electrode (121); each of the first electrode (121) and the second electrode (122) is arranged so as to surround the third electrode (123); the first type unit cell (120a) forms a high electron mobility transistor (HEMT) cell, and the second type unit cell (120a) forms a high electron mobility transistor (HEMT) cell. The second type of unit cells (120b) form a Schottky barrier diode (SBD) cell, and the second type of unit cells (120b) form a Schottky barrier diode (SBD) cell.

The application discloses a high-performance bismuth-free ZnO-Cr2O3-based pressure-sensitive ceramic and a preparation method and application of defect regulation, and belongs to the technical field of pressure-sensitive materials. The method comprises the following steps: ZnO, doped oxides, polyvinyl alcohol aqueous solution, tributyl phosphate and deionized water are ball-mixed to obtain mixed powder; after drying, sieving, granulating and compression molding, oxide-doped ZnO green bodies are obtained; after glue removal and sintering, high-performance bismuth-free ZnO-Cr2O3-based pressure-sensitive ceramic is obtained. The bismuth-free ZnO-Cr2O3-based pressure-sensitive ceramic is obtained by adopting a solid-phase sintering method, taking ZnO as main raw material, and doping multiple oxides for compression and sintering. Immovable acceptor defects and stable double Schottky barrier structures are formed in the oxides enriched at the ZnO grain boundaries, which provides an important technical thought for the electrical performance optimization of different system pressure-sensitive ceramics. The high-performance bismuth-free ZnO-Cr2O3-based pressure-sensitive ceramic has high nonlinearity coefficient and breakdown field strength and small leakage current density, and has a wide application prospect in miniaturized electronic circuit systems.

This application relates to integrating a FinFET and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two pressure source portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. The source and drain structures of the FinFET are respectively formed on the two pressure source portions of the first fin structure. A source metal material, a drain metal material, and a first metal material are formed to be electrically coupled to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metal material.

Disclosed is a trench-type power device and a manufacturing method thereof. The trench-type power device comprises: a semiconductor substrate; a drift region located on the semiconductor substrate; a first trench and a second trench located in the drift region; a gate stack located in the first trench; and Schottky metal located on a side wall of the second trench, wherein the Schottky metal and the drift region form a Schottky barrier diode. The trench-type power device adopts a double-trench structure, which combines a trench-type MOSFET with the Schottky barrier diode and forms the Schottky metal on the side wall of the trench, so that the performance of the power device can be improved, and the unit area of the power device can be reduced.

The invention discloses a gallium oxide-based Schottky barrier diode with low reverse electric leakage and a preparation method thereof, which are applied to a high-voltage-resistant scene, and the method comprises the following steps: preparing a gallium oxide substrate; growing a mark layer on the gallium oxide substrate; performing N ion implantation by using an ion implanter to form box type distribution; then, feeding the sample into a tubular furnace, and annealing in a nitrogen atmosphere; feeding the annealed sample into electron beam evaporation equipment for back cathode growth; then sending the sample into rapid thermal annealing equipment for nitrogen atmosphere annealing to form ohmic contact; then electron beam evaporation is adopted to grow field plate oxide; and finally growing an anode on the top of the device by electron beam evaporation equipment. According to the technical scheme provided by the invention, the gallium oxide-based Schottky barrier diode with low reverse leakage characteristic can be obtained under the condition of maintaining high breakdown voltage of a device.

The invention relates to a Schottky barrier diode and a manufacturing method thereof. The Schottky barrier diode comprises a semiconductor layer; the barrier metal layer is positioned on the semiconductor layer and is in direct contact with the semiconductor layer; the anode metal contact layer is located on the barrier metal layer, and the anode metal contact layer comprises a gold layer; and the passivation layer surrounds the side wall of the barrier metal layer, the inner surface of the passivation layer is in direct contact with the side wall of the barrier metal layer, the passivation layer is provided with a circular opening above the barrier metal layer, and the lower part of the anode metal contact layer is located in the opening. The device is low in leakage current and forward conduction voltage drop, so that the power consumption of the device is low. The circular opening enables the thickness of the anode metal contact layer serving as the bonding pad to be more uniform, the stress is uniform, the stress is improved, and meanwhile, the abnormal influence possibly caused by defects is reduced.

The application belongs to the technical field of chemical looping combustion, and discloses a nano oxygen carrier particle, a photo reactor and a chemical looping system. The nano oxygen carrier particle comprises a metal oxide, a noble metal / rare earth metal and a semiconductor material. The metal oxide has oxidizing property. The semiconductor material generates photo-generated holes and photo-generated electrons under light irradiation. The photo-generated holes have oxidizing property, and the photo-generated electrons have reducing property. The noble metal serves as a catalytic site and forms a Schottky barrier with the semiconductor. The Schottky barrier continuously captures the photo-generated electrons to improve the separation efficiency of the photo-generated electron-photo-generated hole pair. The application further discloses a photo reactor and a chemical reaction chain using the nano oxygen carrier. Through the application, the multifunctional nano oxygen carrier particle with lattice oxygen transfer, photocatalysis and thermal catalysis is synthesized, the operation temperature of the chemical looping system is below 200 DEG C, the low-temperature chemical looping combustion process is realized, and the sintering and agglomeration of the oxygen carrier material are avoided.

To provide a two-dimension photosensor which can be manufactured at a low cost in a thin film transistor plant and covers a relatively wide two-dimension plane.SOLUTION: The two-dimensional photosensor 100 includes a plurality of photodiodes arranged, each photodiode including a stack of a first metal electrode 11, a first semiconductor layer 12, a first ohmic contact layer 13, and a first transparent electrode 16, the first semiconductor layer 12 and the first ohmic contact layer 13 being disposed between the first metal electrode 11 and the first transparent electrode 16, A Schottky barrier is provided on an interface between the first semiconductor layer 12 and the first metal electrode 11 or an interface between the first semiconductor layer 12 and the first transparent electrode 16, and light incident from the side of the first transparent electrode 16 toward the first semiconductor layer 12 is sensed.SELECTED DRAWING: Figure 6

The present application provides a circular Schottky barrier thin film transistor and a preparation method thereof, relating to the field of semiconductor technology. The present application sequentially prepares a circular gate layer, a gate dielectric layer, a circular semiconductor layer, a circular barrier control layer, a source layer with a circular boundary contour, a passivation layer, a drain wiring layer, and a source wiring layer electrically connected to the source layer on a substrate, wherein the gate layer, the semiconductor layer, the barrier control layer, and the source layer coincide with the center of the circle, the conductive film layer portion of the semiconductor layer not covered by the source layer and the barrier control layer will be electrically connected to the drain wiring layer as a drain region, the source layer is in direct contact with a portion of the semiconductor film layer portion of the semiconductor layer to form an ohmic (quasi-ohmic) contact, and the barrier control layer is separated from another portion of the semiconductor film layer portion to form a Schottky barrier.

The invention relates to a composite conductive adhesive tape for a conductive polymer film and a preparation method and application thereof, and the composite conductive adhesive tape comprises the following structural layers: a copper foil layer with a thickness of 5-50 [mu] m; the copper foil layer is provided with two opposite wide surfaces, namely a first side surface and a second side surface; the first side surface of the copper foil layer is uniformly coated with the first pressure-sensitive adhesive layer, and the thickness of the first pressure-sensitive adhesive layer is 10-30 microns; the second side surface of the copper foil layer is uniformly coated with the second pressure-sensitive adhesive layer, and the thickness of the second pressure-sensitive adhesive layer is 10-30 microns; the silver paste layer is formed in a local area, far away from the surface of the copper foil layer, of the second pressure-sensitive adhesive layer, and the thickness of the silver paste layer is 5-20 microns. Therefore, the silver paste layer can significantly reduce interface Schottky barrier and contact resistance, has corrosion resistance and good chemical stability, combines adhesion and conductivity, and can realize application of the copper adhesive tape on a conductive polymer film.

A radiation detection device includes at least one heterojunction Schottky barrier diode (HSBD). The at least one HSBD includes at least one boron-doped diamond layer located on top of at least one epitaxial layer, the epitaxial layer located on top of at least one buffer layer, and the buffer layer located on top of a bulk substrate layer. At least one contact layer is located on a side of the bulk substrate layer opposite the epitaxial layer.

The invention discloses a method for assisting hydrogenation of Ga2O3 by Pd and application, mainly solving the problem of damage to materials in the existing gallium oxide hydrogenation preparation process, and the method is implemented by the following steps: preparing Pd metal on a gallium oxide sample by a sputtering or electron beam evaporation method; placing the Pd / Ga2O3 sample in a closed cavity with the air pressure smaller than or equal to 10 Pa, introducing mixed gas containing 0.1%-100% of hydrogen, catalyzing the hydrogen to be decomposed and sucked into Pd crystal lattices at low temperature to obtain a Pd / Ga2O3 sample in which Pd metal adsorbs hydrogen atoms, and performing laser annealing and annealing heat treatment on the Pd / Ga2O3 sample to enable the hydrogen atoms to be diffused into gallium oxide so as to obtain the gallium oxide. A Pd / Ga2O3 sample with hydrogen atoms entering the gallium oxide is obtained; and removing Pd metal on the sample by a chemical etching or physical method to obtain the hydrogenated gallium oxide. While the doping effectiveness is improved, the hydrogenated gallium oxide is not damaged, and the method can be used for manufacturing Schottky barrier diodes, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and deep ultraviolet photoelectric detectors.

A junction field-effect transistor that is normally off rather than normally on, and a method of making such a device. The junction field-effect transistor includes a volume of semiconductor material, a first gate located at a first side of the semiconductor material, a second gate located at a second side opposite and spaced apart from the first gate, a Schottky barrier diode, and a drain. The Schottky barrier diode is located at a first end of the semiconductor material between the first and second gates, and replaces a conventional source. The drain is located at the second end, opposite the diode, and a region of the semiconductor material between the diode and the drain provides a channel. The Schottky barrier diode conducts in a forward mode (i.e., the device is on) only when the anode-to-cathode voltage exceeds the metal-to-semiconductor barrier potential, which means the device is normally off.

The present application has an object to prevent insulation breakdown caused by misalignment of a trench and a field insulation layer in a Schottky barrier diode of gallium oxide. The Schottky barrier diode includes an anode electrode (40) in Schottky contact with a drift layer (30), a cathode electrode (50) in ohmic contact with a semiconductor substrate (20), an insulation film (63) covering an inner wall of a trench (61) provided in the drift layer (30), a metal film (64) covering the inner wall of the trench (61) through the insulation film (63) and electrically connected to the anode electrode (40), and a field insulation layer (70). The field insulation layer (70) includes a first portion (71) between an upper surface (31) of the drift layer (30) and the anode electrode (40) and a second portion (72) covering the inner wall of the trench (61) through the metal film (64) and the insulation film (63). Thus, even if the alignment of the trench (61) and the field insulation layer (70) is misaligned, insulation breakdown does not occur.

A Schottky diode includes a substrate with an active region. Sidewall and bottom surfaces of trench extending into an epitaxial layer of the substrate are lined with an insulating layer, and the remainder of each trench is filled with a polycrystalline silicon (polysilicon) fill. A doped region having the same conductivity type dopant as the semiconductor substrate is implanted in the epitaxial layer at locations between adjacent trenches. A silicide is provided at each polysilicon fill and a Schottky barrier is provided at each doped region. An anode contact for the diode contacts the silicide and Schottky barrier, and a cathode contact for the diode contacts a lower surface of the substrate. The selection of a dopant concentration level for the doped region controls setting of a forward voltage VF level for the Schottky diode.

This semiconductor device (1) comprises: a semiconductor layer (40) which has a semiconductor substrate (32) that has a first conductivity type and contains an impurity of a first concentration, and a low-concentration impurity layer (33) that is formed to be in contact with the upper surface of the semiconductor substrate (32), has the first conductivity type, and contains an impurity of a second concentration that is lower than the first concentration; a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which use the semiconductor substrate (32) as a common drain region; and a first Schottky barrier diode (81) which uses the low-concentration impurity layer (33) as a cathode in a case where the first conductivity type is N-type, and uses the low-concentration impurity layer (33) as an anode in a case where the first conductivity type is P-type, the first Schottky barrier diode (81) being connected in parallel in the same forward direction with a body diode of the first vertical MOS transistor (10).