9results about How to "Improve area efficiency" patented technology

The invention provides an FIFO circuit and electronic equipment, and relates to the technical field of circuit design. In the FIFO circuit, an input cache module comprises n input registers and is used for receiving n pieces of to-be-stored target data output by an upstream circuit; the storage module comprises a storage controller and a memory, the memory is divided into n virtual FIFOs, and the n virtual FIFOs are in one-to-one correspondence with the n input registers; the first address management module is used for determining a virtual FIFO meeting a first hit condition in the n virtual FIFOs as a first virtual FIFO in each clock cycle, generating a corresponding write address of a write pointer of the first virtual FIFO in the memory, sending the write address to the memory controller, and sending the write address to the memory controller; a first input register corresponding to the first virtual FIFO is controlled to output target data to a storage controller; the memory controller is to write the target data to the memory based on the write address. According to the invention, the occupied area of the whole circuit of a plurality of FIFOs can be effectively reduced, and the efficiency of the whole area is improved.

The application provides a unified systolic array computing unit for ANN and SNN, comprising a shift-add computing processing unit and a systolic array formed by arrayed deployment of the shift-add computing processing unit; an execution of artificial neural network operation or pulse neural network operation is switched through a configuration mode selection signal terminal; in the artificial neural network mode, multiplication operation is unfolded in the time dimension, and a shift register and an adder constitute a time division multiplexing operation sequence to complete multiplication and accumulation operation; in the pulse neural network mode, a weighting accumulation is directly completed through multiplexing of an addition link, and a neuron time step dependent chain is decoupled through a soft reset mechanism to realize cross-time step weight multiplexing; control signals and data are propagated in the same direction in the systolic array, which is used for realizing control logic array level multiplexing, and fixed data flow is adopted for the output, so that partial sums are preferentially resident in the array interior; the working frequency can be improved, the bandwidth and power consumption can be reduced, and the area efficiency and timing convergence can be improved.

The application discloses a three-dimensional memory device, comprising a substrate, a stack structure arranged on the substrate, and a memory string structure penetrating through the stack structure. The stack structure comprises a plurality of conductive layers and a plurality of dielectric layers arranged alternately. The memory string structure comprises a conductive pillar and a memory layer between the conductive pillar and the stack structure and surrounding the conductive pillar, wherein the memory layer comprises a plurality of first protrusions respectively filled in a plurality of first recesses at the junctions of the conductive layers and the dielectric layers. The application can improve the electrical isolation between memory cells and reduce the signal interference problem between adjacent memory cells during writing or reading.

The invention relates to a unified memory architecture supporting a multi-post quantum algorithm and a near memory mapping method thereof. The invention relates to the technical field of post quantum cryptography. The architecture comprises a program controller, an instruction ROM, a Keccak module, a sampler and a polynomial arithmetic unit, the program controller decodes an instruction from the ROM, wherein the instruction specifies an operation type, a source / target operand and a control signal; a Hash function mode is selected through a control signal of the Keccak controller; the sampler is tightly coupled with Keccak output and comprises a parallel logic unit of each mode, and an internal arbiter selects sampling variants according to a current instruction and activates corresponding sub-modules; the polynomial arithmetic unit supports high throughput polynomial operation. According to the method, multiple post quantum cryptography algorithms can be efficiently supported on a single hardware platform, and flexible switching among the algorithms can be realized on the premise of not sacrificing performance.

The invention discloses a dynamic comparator based on current injection, and belongs to the field of integrated circuits. According to the dynamic comparator, on the basis of a dynamic comparator main body structure, a calibration branch composed of a current mirror, a direction selection switch and a time sequence isolation switch is integrated, controllable current is injected into one of internal nodes in a reset stage, and a preset voltage difference is generated through reset tube impedance so as to compensate inherent imbalance; in the comparison stage, a calibration branch is physically isolated from a core node by turning off a time sequence isolation switch, and the influence of stray capacitance on the speed is thoroughly eliminated. According to the scheme, on the premise that the working speed of the dynamic comparator is not sacrificed, high-precision and linear digital calibration of the offset voltage is completed, and meanwhile the method has the advantages of being high in area efficiency and good in all-working-condition stability.

The application discloses a charge pump circuit, comprising an auxiliary charge pump and a main charge pump. The power supply end of the auxiliary charge pump is connected with a first power supply voltage, and the output end outputs a first output voltage. The gate of a first NMOS tube is connected with the first output voltage, the drain is connected with a second power supply voltage, and the source outputs a third power supply voltage. The first NMOS tube has a first threshold voltage. The power supply end of the main charge pump is connected with the third power supply voltage, and the output end outputs a second output voltage. The second power supply voltage is greater than the first power supply voltage; the second power supply voltage has a first change range. The first output voltage is within the first change range, and when the second power supply voltage is greater than the first output voltage, the third power supply voltage is clamped at the first output voltage minus the first threshold voltage. The third power supply voltage has a second change range, and the second change range is less than the upper limit of the first change range. The application can prevent the output voltage from generating a ripple defect and improve the area efficiency.

The present disclosure relates to a content addressable memory device, a memory and an electronic device, the device comprising: a plurality of memory cells, each memory cell comprising a read-only memory device, a capacitor, the read-only memory device comprising a first input terminal, a second input terminal and an output terminal, the output terminal of the read-only memory device being connected to a first terminal of the capacitor, the read-only memory device storing data through a connection relationship between the first input terminal, the second input terminal and the output terminal; and a control module connected to each memory cell, configured to: control voltages of the first input terminal and the second input terminal of the read-only memory device of each memory cell to perform a target operation; and determine an operation result of the target operation according to a voltage of a second terminal of the capacitor. The embodiments of the present disclosure implement a content addressable memory device based on a read-only memory device, which can improve the area efficiency of the content addressable memory device, reduce or even eliminate unnecessary energy consumption caused by memory access, and reduce energy consumption.

According to an aspect, there is provided a 3D IC device comprising: a first semiconductor device layer comprising a first set of active devices; a second semiconductor device layer comprising a second set of active devices; a clock distribution network comprising a plurality of clock signal routing interconnects arranged in an interconnect structure, the interconnect structure being arranged on a side of the first semiconductor device layer facing the second semiconductor device layer; and a logic circuit comprising a plurality of registers, each register comprising a first active device arranged along a data path of the register and a second active device arranged along a clock path of the register, wherein the first active device is comprised in the first set of active devices of the first semiconductor device layer, and wherein the second active device is comprised in the second set of active devices of the second semiconductor device layer and connected to the clock distribution network to receive a clock signal.

A multi-functional secure communication chip for SM2 with area optimization and its design method are disclosed. The main components include: constructing an area-optimized multiplexing architecture to achieve various secure computation functions of SM2 through time-division multiplexing; selecting an area-optimized algorithm; and setting up a configurable register set to store elliptic curve parameters to adapt to elliptic curve standards of different security levels. This method achieves area optimization by selecting appropriate algorithms and their combinations, and utilizes a step-by-step control method to achieve time-division multiplexing and reduce power consumption. Based on this architecture, basic computation modules can be shared, and all SM2 protocols can be superimposed to achieve a multi-functional design. Simultaneously, setting the basic parameters of the elliptic curve as configurable registers enables adaptation to curves in multiple prime domains.