228 results about "Electrostatic discharge protection" patented technology

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The invention discloses a chip electrostatic discharge protection method, a related device, electronic equipment and a storage medium, and the method comprises the steps: determining a first region where a target power domain is located in a chip layout based on layout planning data in the chip layout, and constructing an initial layout consistent with the chip layout in specification; filling a second region corresponding to the first region in the initial layout with a target device unit matched with the voltage type of the target power supply domain; safety verification about chip electrostatic discharge is carried out on the target layout passing the functional check, and a verification result is obtained; and in response to the verification result representing that the security verification is not passed, setting a discharge unit in the target layout, and returning to the step of performing the security verification about chip electrostatic discharge on the target layout passing the functional check to obtain the verification result until the verification result representing that the security verification is passed. According to the scheme, the efficiency and quality of constructing the chip electrostatic discharge protection network can be improved.

The present disclosure relates to a bulk acoustic wave (BAW) device with electrostatic discharge (ESD) protection. The disclosed BAW device includes a substrate (106), an ESD protection layer (106) over the substrate (106), a first bottom reflector (109-1) over the ESD protection layer (108), a first bottom electrode (112-1) over the first bottom reflector (109-1), a first top electrode (118-1) vertically aligned with the first bottom electrode (112-1), and a piezoelectric layer (116C) vertically between the first bottom electrode (112-1) and the first top electrode (118-1). Herein, the ESD protection layer (108) is electrically insulating and eligible to achieve at least a 400 V breakdown voltage with a 200 nm thickness. The first bottom reflector (109-1) includes a stack of alternating high acoustic impedance conductive layers (120A-E) and low acoustic impedance conductive layers (120A-E). The first bottom electrode (112-1) is electrically connected to the first bottom reflector (109-1). A breakdown voltage of the piezoelectric layer (116C) is no more than the breakdown voltage of the ESD protection layer (108).

A physiological signal monitoring device includes a base and a transmitter. The base is provided with a biosensor. The transmitter is removably coupled to the base, and includes a casing and an electrostatic-discharge protective unit. The casing has a socket for the biosensor to be removably inserted thereinto. The electrostatic-discharge protective unit is disposed to at least surround the periphery of the socket to dispel static electricity when electrostatic discharge occurs.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

An electrostatic discharge (ESD) protection circuit protecting a core circuit and including a first high electron mobility transistor (HEMT), a second HEMT, a first current clamping circuit, a second current clamping circuit, and a resistor is provided. The first HEMT is coupled to a first input terminal. The second HEMT is coupled between the first HEMT and a second input terminal. The first current clamping circuit includes a third HEMT. The third HEMT is coupled between the gate of the first HEMT and the second input terminal. The second current clamping circuit is coupled between the first input terminal and the gate of the second HEMT. The resistor is coupled between the first input terminal and the core circuit. The core circuit is coupled to the second input terminal.

An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes first and second N-type deep well (DNW) regions in a P-type semiconductor substrate, first to fourth N-type and P-type doped regions, and first and second P-type well (PW) regions. The first N-type and P-type doped regions and the first PW region are located in the first DNW region. The second N-type and P-type doped regions and the second PW region are located in the second DNW region. The third and fourth N-type and P-type doped regions are located in the first and second PW regions. The first P-type and fourth N-type doped regions are connected to an input / output terminal. The first N-type and second P-type doped regions are connected to a power supply terminal. The third N-type and the fourth P-type doped regions are connected to a ground terminal.

An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The disclosure provides an electrostatic discharge (ESD) protection device for protecting a core circuit coupled between a first power rail and a second power rail. The ESD protection device includes a pull-up element. The pull-up element includes a bidirectional switch element. A first terminal of the bidirectional switch element is coupled to a third power rail. A second terminal of the bidirectional switch element is coupled to a signal transmission wire. The core circuit is coupled to a signal connection pad through the signal transmission wire. A control terminal of the bidirectional switch element is coupled to a control circuit or a reference voltage.

An electrostatic discharge protection device includes: a substrate; a first doped region of the first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first diffusion region of the first conductivity type on the first doped region; a second diffusion region of a second conductivity type on the epitaxial layer; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first doped region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically bonded.

The application provides an electrostatic discharge protection device and a chip. The device comprises a substrate, a P-type region and an N-type region in the substrate, a first N-type doped region, a second N-type doped region, a first P-type doped region and a second P-type doped region in the P-type region, the second P-type doped region being between the first N-type doped region and the second N-type doped region, and the first N-type doped region being between the first P-type doped region and the second P-type doped region, a third N-type doped region and a third P-type doped region in the N-type region, and a gate above a region between the first N-type doped region and the second P-type doped region. The gate is connected with the second P-type doped region, the second N-type doped region is connected with the first P-type doped region as a negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected as a positive electrode of the electrostatic discharge protection device. The application can reduce the triggering voltage of the device and improve the holding current.

Structures including an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.

The invention provides an electrostatic discharge protection device which is used for protecting a core circuit coupled between a first power rail line and a second power rail line. The electrostatic discharge protection device comprises a first electrostatic discharge clamping circuit, a second electrostatic discharge clamping circuit and a pull-up assembly. The first electrostatic discharge clamping circuit is coupled between the first power rail and the common node. The second electrostatic discharge clamp circuit is coupled between the common node and the second power rail. The first end of the pull-up component is coupled to the common node. The second end of the pull-up assembly is coupled to the signal transmission wire. The core circuit is coupled to the signal connection pad through the signal transmission wire.

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes an N-type deep well region (DNW), first and second high-voltage P- and N-type well regions (first and second HVPW and HVNW), a low-voltage N-type well region (LVNW), first and second P- and first N-type doped regions in a P-type semiconductor substrate, and a gate structure. The first and second HVPW and HVNW are located on the DNW. The LVNW is located on the first HVPW. The first P- and N-type doped regions and second P-type doped region are located on the LVNW and the second HVNW and HVPW. The first P-type doped region is electrically connected to a first voltage source. The gate structure on the first and second HVPW and the first HVNW, the second P-type doped region and the first N-type doped region are electrically connected to a second voltage source.

This application illustrates an electro-static discharge protection structure and an electronic device. One end of a pressure-sensitive elastic component is connected to a metal housing, the other end of the pressure-sensitive elastic component extends in a direction away from the metal housing. A border frame includes a connection part—and a first side edge. A conductive layer is disposed on a side, facing the pressure-sensitive elastic component, of the connection part. The one end of the pressure-sensitive elastic component—is connected to the conductive layer, and the other end of the pressure-sensitive elastic component is connected to the metal housing.

The invention provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is coupled between the first pad and the second pad. The electrostatic discharge protection circuit comprises a substrate, a second conductive transistor structure, a resistor structure and a silicon controlled rectifier structure. The substrate has a first conductivity type. The second conductive type transistor structure is located in the substrate and is provided with a gate end. The resistive structure is in the substrate and includes a first resistor. A gate terminal of the second conductivity type transistor structure is coupled to the second pad through the resistive structure. The silicon-controlled rectifier structure is located in the substrate and is provided with a first end, a second end and a third end. A first terminal of the silicon controlled rectifier structure is coupled to the first pad, a second terminal of the silicon controlled rectifier structure is coupled to the second pad, and a third terminal of the silicon controlled rectifier structure is coupled to a gate terminal of the second conductivity type transistor structure.

ESD Protection Circuit This description relates to an electrostatic discharge protection circuit (Cesd2). An electrostatic discharge dissipation component (Cesd1) has a first conduction terminal (A1), a second conduction terminal (A2), and a control terminal (C). Identical first and second devices (Dev1, Dev2) each have first (A3) and second (A4) conduction terminals, with the respective first terminals (A3; A3') of the first and second devices (Dev1, Dev2; Dev1', Dev2') connected to the control terminal (C) of the component, and the respective second terminals (A4) of the first and second devices (Dev1, Dev2) connected to the component's first terminal (A1; A1') and second terminal (A2), respectively. Figure for the abstract: Fig. 2

An electrostatic discharge (ESD) protection device is proposed. The ESD protection device may include a semiconductor substrate, an epitaxial region formed on the semiconductor substrate, a well region formed on the epitaxial region, and a P+ diffusion region formed on the well region. The ESD protection device may also include an N+ diffusion region formed on the well region, an anode connected to the P+ diffusion region, a cathode connected to the N+ diffusion region, and a first ESD mask formed on the well region. P+ ions having predefined concentration and energy are injected through the first ESD mask.

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a conductive pad and an electrostatic discharge (ESD) protection circuitry coupled to the conductive pad. The ESD protection circuitry includes a first diode including a first node coupled to a first supply node, and a first additional node coupled to the conductive pad; a second diode including a second node coupled to the conductive pad, and a second additional node coupled to a second supply node; a resistor including a first resistor node coupled to the conductive pad, and a second resistor node; and a switch circuit including a first node coupled to the first resistor node, and a second node coupled to the second resistor node.

According to the electrostatic protection device structure and the preparation method thereof provided by the invention, in the device structure, the isolation buried layer is arranged between the drop-capacitance device structure and the substrate, so that the parasitic capacitance between the drop-capacitance device structure and the substrate can be reduced, the total capacitance of the electrostatic protection device structure is reduced, and further, the overall capacitance of the electrostatic protection device structure is reduced. And the interference on a high-speed signal is reduced, so that the signal integrity is ensured.

A printed circuit board (PCB) assembly for electrostatic discharge (ESD) protection is disclosed. The assembly includes a top layer comprising at least one signal track and configured to support at least a portion of a plurality of electronic components mounted thereon. A middle layer disposed beneath the top layer. The middle layer comprises at least one ground track configured to receive electrostatic discharge currents from adjacent layers. A bottom layer disposed beneath the middle layer. The bottom layer comprises at least one power track 108a and configured to support another portion of the plurality of electronic components. A plurality of metal discharge elements disposed on at least one of the top layer or the bottom layer. Each of the metal discharge element is electrically connected to the at least ground track of the middle layer.

A differential data transmission system (200; 700), comprising: a source (201) configured to transmit a differential signal containing data; a load (204) configured to receive the differential signal; and a common-mode suppressor (300; 400; 500; 702) comprising a long, wound differential transmission line configured to carry the differential signal from the source to the load; wherein a length of the differential transmission line is at least greater than one tenth of the wavelength of the differential signal, which is transmitted through the differential transmission lines in a predetermined operating frequency range of the differential signal, further comprising a protection circuit (202; 701) against electrostatic discharges, which is connected to the first (303; 703) and second (304; 704) input pins of the common-mode suppressor (300; 400; 500; 702) and which is configured to provide protection against shocks from electrostatic discharge.

Embodiments included herein are directed towards an electrostatic discharge (“ESD”) protection circuit and methods of using the same. The circuit may include a power supply and a power clamp operatively connected with the power supply. The circuit may further include a field effect transistor (“FET”) operatively connected with the power clamp and at least one diode operatively connected with the field effect transistor. The circuit may further include an auxiliary power clamp operatively connected with the field effect transistor.

This application discloses an electrostatic discharge (ESD) protection circuit and chip. The ESD protection circuit includes a conversion module and a dissipation module. The conversion module is connected to a power supply and a ground terminal. The conversion module is configured to obtain a second voltage based on the first voltage when the first voltage provided by the power supply exceeds a threshold voltage. The threshold voltage is the voltage corresponding to the generation of ESD, and the second voltage is less than the first voltage. The dissipation module is connected to the output terminal of the conversion module and to the power supply and ground terminal. The dissipation module is configured to receive the second voltage, operate according to the second voltage, and modulate the first voltage to be less than the threshold voltage before outputting it to the electronic device. In other words, the technical solution of this application reduces the overvoltage corresponding to the generation of ESD through the conversion module and avoids drawing additional current, thereby protecting subsequent electronic devices from damage caused by ESD overvoltage. Furthermore, the structure is simple and the cost is reduced.

An electrostatic discharge (ESD) protection circuit includes a silicon controlled rectifier (SCR). The SCR includes an N+ diffusion region (N... pick Terminal), the N+ diffusion region (N pick The source terminal of the P-channel metal-oxide-semiconductor (PMOS) transistor is formed in the n-well (NW) region and connected to the inverter; and the P+ diffusion region (P... trig Terminal), the P+ diffusion region (P trig The terminal is formed in the p-type substrate and connected to the source terminal of the N-channel metal-oxide-semiconductor (NMOS) transistor of the inverter.

The application relates to the technical field of semiconductor bridge electrostatic discharge protection and current protection, and discloses an electrostatic discharge and current protection circuit of a semiconductor bridge, which comprises an ESD protection circuit, a current protection circuit and an NMOS connected in parallel, the ESD protection circuit comprises a bidirectional transient suppression diode and a capacitor connected in parallel, the bidirectional transient suppression diode clamps a transient high voltage by breakdown conduction, the voltage is limited in a safe range, the capacitor reduces a voltage rising rate and suppresses overshoot by shunting and absorbing a transient current, the NMOS provides a low-resistance discharge path, and the voltage and current impact applied to the semiconductor bridge are reduced; the current protection circuit comprises a bidirectional rectifier circuit and a detection circuit; and the NMOS is connected between the detection circuits. The application can realize ESD protection and current protection of the semiconductor bridge, prevents current from damaging the structure, and guarantees the safety of the semiconductor bridge working in an electromagnetic and ESD environment.

An integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells over the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit cells includes first and second bits. The first bit includes a first electrostatic discharge (ESD) protection circuit and a first strap region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second strap region in the semiconductor substrate. The first strap region of the first bit is symmetric to the second strap region of the second bit with respect to a border between the first bit and the second bit in a top view, and the first p-type strap region of the first bit and the second strap region of the second bit have a first conductivity type. The first and second pads are respectively connected to the first and second ESD protection circuits.

An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.