512 results about "Electrostatic discharge protection" patented technology

A display substrate is provided. The display substrate includes a display substrate, comprising one or more scan circuits and one or more electrostatic discharge protection circuits in a peripheral area. An electrostatic discharge protection circuit is configured to provide a start signal to a scan unit of a scan circuit. The display substrate comprises a plurality of islands and a plurality of bridges connecting the plurality of islands in the peripheral area; a respective island of the plurality of islands comprises at least one scan unit of the scan circuit; and one or more signal lines connecting the electrostatic discharge protection circuit and the scan unit is at least partially in an individual bridge connecting the electrostatic discharge protection circuit and the scan unit.

Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

In one implementation, an apparatus, such as an ESD protection circuit, is disclosed. The apparatus can include a filter coupled between a local supply voltage rail to a supply voltage rail. A switch circuit can be connected in parallel with the filter. The apparatus can include a clamp configured to 1) provide a first ESD shunt path from an input line to the local supply voltage rail and 2) provide a second ESD shunt path from the input line to a lower voltage rail. A second clamp can be configured to provide a third ESD shunt path from the local supply voltage rail to the lower voltage rail. The switch circuit can be configured to close a switch to bypass the filter.

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

An electro-static discharge (ESD) protection circuit includes an ESD current discharge circuit including a first transistor, a second transistor, and a third transistor, connected in series and connected between a pad and a ground voltage, an ESD detection circuit configured to turn on the third transistor when the ESD event occurs, and a bias generation circuit configured to provide a bias voltage for turning on the first transistor to a gate of the first transistor when the ESD event occurs.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

A semiconductor device includes a through-silicon via (TSV) in a substrate, wherein the TSV extends through the substrate. The semiconductor device further includes an ESD cell in the substrate, the ESD cell comprising a set of diodes electrically connected in parallel to each other. The semiconductor device further includes an antenna electrically connected to the TSV and extending in a first direction parallel to a major axis of the TSV. The semiconductor device further includes a conductive pillar electrically connected to the ESD cell, wherein the antenna is between the TSV and the conductive pillar.

The utility model provides a kind of electrostatic discharge protection circuit and low noise amplification module, the electrostatic discharge protection circuit is applied to low noise amplification circuit, the low noise amplification circuit includes input matching circuit and the low noise amplifier of the output end being connected to the input matching circuit;The electrostatic discharge protection circuit includes inductance and resistance;The first end of the inductance is used to connect to the signal input end of low noise amplifier;The first end of the resistance is connected to the second end of the inductance, and the second end of the resistance is grounded.The electrostatic discharge protection circuit in the utility model is connected to the input end of low noise amplifier, and the noise coefficient of low noise amplifier will not be deteriorated, and the performance of low noise amplifier will not be affected, and the input stability of low noise amplifier will not be affected simultaneously.

Solid state transducers with state detection, and associated systems and methods are disclosed. A solid state transducer system may include a support substrate that carries a solid state emitter and a state device. The solid state emitter and the state device may be stacked along a common axis. Further, the state device may be positioned to detect a state of the solid state emitter and / or an electrical path of which the solid state emitter forms a part. The solid state emitter may include a first semiconductor component, a second semiconductor component, and an active region between the first and second semiconductor components. The state device may include a state-sensing component having a composition different than that of the active region and the first and second semiconductor components. In some embodiments, the state-sensing component may include an electrostatic discharge protection device, a thermal sensor, a photosensor, or a combination thereof.

The invention discloses a chip electrostatic discharge protection method, a related device, electronic equipment and a storage medium, and the method comprises the steps: determining a first region where a target power domain is located in a chip layout based on layout planning data in the chip layout, and constructing an initial layout consistent with the chip layout in specification; filling a second region corresponding to the first region in the initial layout with a target device unit matched with the voltage type of the target power supply domain; safety verification about chip electrostatic discharge is carried out on the target layout passing the functional check, and a verification result is obtained; and in response to the verification result representing that the security verification is not passed, setting a discharge unit in the target layout, and returning to the step of performing the security verification about chip electrostatic discharge on the target layout passing the functional check to obtain the verification result until the verification result representing that the security verification is passed. According to the scheme, the efficiency and quality of constructing the chip electrostatic discharge protection network can be improved.

An electro-static discharge (ESD) protection device includes a first well region and a second well region disposed to contact each other, a first diffusion region and a second diffusion region disposed in the first well region spaced apart from each other, a third diffusion region and a fourth diffusion region disposed in the second well region spaced apart from each other, a fifth diffusion region of the second conductivity type disposed in the first well region spaced apart from the first and second diffusion regions, a resistive pattern coupled to the first diffusion region through a first contact plug, a first electrode coupled to the second diffusion region through a second contact plug and electrically coupled to the resistive pattern, and a second electrode coupled to the third diffusion region through a third contact plug and coupled to the fourth diffusion region through a fourth contact plug.

The present disclosure relates to a bulk acoustic wave (BAW) device with electrostatic discharge (ESD) protection. The disclosed BAW device includes a substrate (106), an ESD protection layer (106) over the substrate (106), a first bottom reflector (109-1) over the ESD protection layer (108), a first bottom electrode (112-1) over the first bottom reflector (109-1), a first top electrode (118-1) vertically aligned with the first bottom electrode (112-1), and a piezoelectric layer (116C) vertically between the first bottom electrode (112-1) and the first top electrode (118-1). Herein, the ESD protection layer (108) is electrically insulating and eligible to achieve at least a 400 V breakdown voltage with a 200 nm thickness. The first bottom reflector (109-1) includes a stack of alternating high acoustic impedance conductive layers (120A-E) and low acoustic impedance conductive layers (120A-E). The first bottom electrode (112-1) is electrically connected to the first bottom reflector (109-1). A breakdown voltage of the piezoelectric layer (116C) is no more than the breakdown voltage of the ESD protection layer (108).

The utility model provides a display panel, a display module and a display device. The display panel comprises a first area used for arranging a driving chip, and a first protection layer is arranged on one side of the first area; in the first direction, the first protective layer sequentially comprises a first insulating layer and a first electromagnetic interference shielding layer; in the second direction, the first insulating layer and the first electromagnetic interference shielding layer are the same in size, and the second direction is perpendicular to the first direction. According to the technical scheme, the electrostatic discharge protection capability of the display device can be improved, and then the probability that the display device is damaged is reduced.

The invention provides an electrostatic discharge protection structure, a semiconductor power device and a manufacturing method of the semiconductor power device. The electrostatic discharge protection structure comprises a first groove structure, a second groove structure, a first diode string, a first interval oxide layer and a second diode string. The first trench structure includes a first polysilicon structure and a first oxide layer surrounding the first polysilicon structure. The second trench structure includes a second polysilicon structure and a second oxide layer surrounding the second polysilicon structure. The first diode string is adjacent to the first polysilicon structure and the second polysilicon structure, and is disposed between the first trench structure and the second trench structure. The first spacer oxide layer is disposed on the first diode string. The second diode string is disposed on the first spacer oxide layer and is connected in parallel with the first diode string.

A physiological signal monitoring device includes a base and a transmitter. The base is provided with a biosensor. The transmitter is removably coupled to the base, and includes a casing and an electrostatic-discharge protective unit. The casing has a socket for the biosensor to be removably inserted thereinto. The electrostatic-discharge protective unit is disposed to at least surround the periphery of the socket to dispel static electricity when electrostatic discharge occurs.

An anti-corrosion circuit, an array substrate and an electronic device are provided. The array substrate includes: source signal lines, provided in the display area, extending along a first direction and arranged sequentially along a second direction; a first power bus line, provided in the peripheral area and including a main body portion extending along the second direction; an electrostatic discharge protection circuit, provided on a side of the main body portion away from the display area and electrically connected to the source signal lines, and including first sub-signal lines and second sub-signal lines. The first sub-signal lines and the second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion is adjacent to one first sub-signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub-signal line.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

An ESD includes a detection circuit, a P-type transistor, a N-type transistor, and a discharge circuit. The detection circuit detects whether an electrostatic discharge event occurs on a first power bonding pad to generate first and second detection signals. The first P-type transistor is coupled between the first power bonding pad and a first node and receives the first detection signal. The first N-type transistor is coupled between the first node and a second power bonding pad and receives the second detection signal. The discharge circuit is coupled between the first power bonding pad and the second power bonding pad and controlled by a control signal on the first node. In response the electrostatic discharge event occurring on the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and the second power bonding pad according to the control signal.

An ESD protection circuit using GaN devices, with a ESD block including a first 2 DEG resistor with one terminal coupled to a gate of a power HEMT, a first trigger with one terminal coupled to another terminal of the first 2 DEG resistor and with another terminal coupled to a reference voltage, a first LV-HEMT with a first gate coupled to the another terminal of the first 2 DEG resistor and a first drain couple to the gate, a second trigger with one terminal coupled to the gate, a second 2 DEG resistor with one terminal coupled to another terminal of the second trigger and another terminal coupled to the reference voltage, and a second LV-HEMT with a second gate coupled to the another terminal of the second trigger and a second drain coupled to the first source and a second source coupled to the reference voltage.

An electrostatic discharge (ESD) protection circuit protecting a core circuit and including a first high electron mobility transistor (HEMT), a second HEMT, a first current clamping circuit, a second current clamping circuit, and a resistor is provided. The first HEMT is coupled to a first input terminal. The second HEMT is coupled between the first HEMT and a second input terminal. The first current clamping circuit includes a third HEMT. The third HEMT is coupled between the gate of the first HEMT and the second input terminal. The second current clamping circuit is coupled between the first input terminal and the gate of the second HEMT. The resistor is coupled between the first input terminal and the core circuit. The core circuit is coupled to the second input terminal.

An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.

An anti-corrosion circuit, an array substrate and an electronic device are provided. The array substrate includes: source signal lines, provided in the display area, extending along a first direction and arranged sequentially along a second direction; a first power bus line, provided in the peripheral area and including a main body portion extending along the second direction; an electrostatic discharge protection circuit, provided on a side of the main body portion away from the display area and electrically connected to the source signal lines, and including first sub-signal lines and second sub-signal lines. The first sub-signal lines and the second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion is adjacent to one first sub- signal line, and electrical property of the first power bus line is the same as electrical property of the one first sub-signal line.

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes first and second N-type deep well (DNW) regions in a P-type semiconductor substrate, first to fourth N-type and P-type doped regions, and first and second P-type well (PW) regions. The first N-type and P-type doped regions and the first PW region are located in the first DNW region. The second N-type and P-type doped regions and the second PW region are located in the second DNW region. The third and fourth N-type and P-type doped regions are located in the first and second PW regions. The first P-type and fourth N-type doped regions are connected to an input / output terminal. The first N-type and second P-type doped regions are connected to a power supply terminal. The third N-type and the fourth P-type doped regions are connected to a ground terminal.

The invention relates to the technical field of digital signal processing, in particular to a USB4 high-speed logic analyzer based on an FPGA and a logic analysis method.The USB4 high-speed logic analyzer comprises an electrostatic discharge protection module, an external oscillator, an FPGA module, a high-speed data transmission channel, a USB4-to-PCIe controller and a USB4 interface; the USB4 interface is used for receiving an acquisition instruction sent from an external upper computer in a DMA mode, so that the FPGA-based USB4 high-speed logic analyzer analyzes the acquisition instruction to obtain acquisition parameters, and the acquisition parameters are used for controlling the FPGA-based USB4 high-speed logic analyzer to perform data acquisition on to-be-acquired equipment to obtain target data; data transmission is carried out between the FPGA module and the USB4 to PCIe controller through a high-speed data transmission channel; the FPGA module is used for transmitting target data to the USB4 to PCIe controller through a high-speed data transmission channel; the USB4 to PCIe controller is used for performing data conversion on the received target data to obtain a target data packet; and the USB4-to-PCIe controller and an external upper computer carry out data transmission through a USB4 interface in a DMA (Direct Memory Access) mode.

An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The disclosure provides an electrostatic discharge (ESD) protection device for protecting a core circuit coupled between a first power rail and a second power rail. The ESD protection device includes a pull-up element. The pull-up element includes a bidirectional switch element. A first terminal of the bidirectional switch element is coupled to a third power rail. A second terminal of the bidirectional switch element is coupled to a signal transmission wire. The core circuit is coupled to a signal connection pad through the signal transmission wire. A control terminal of the bidirectional switch element is coupled to a control circuit or a reference voltage.

An electrostatic discharge protection device includes: a substrate; a first doped region of the first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first diffusion region of the first conductivity type on the first doped region; a second diffusion region of a second conductivity type on the epitaxial layer; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first doped region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically bonded.

A semiconductor package and semiconductor die, the semiconductor package including at least a first die. The first die includes internal circuitry disposed on a substrate, electrostatic discharge (ESD) protection circuitry disposed on the substrate but laterally spaced from the internal circuitry and including a first charge dissipation element, and a first silicon controlled rectifier (SCR) laterally adjacent.

The application provides an electrostatic discharge protection device and a chip. The device comprises a substrate, a P-type region and an N-type region in the substrate, a first N-type doped region, a second N-type doped region, a first P-type doped region and a second P-type doped region in the P-type region, the second P-type doped region being between the first N-type doped region and the second N-type doped region, and the first N-type doped region being between the first P-type doped region and the second P-type doped region, a third N-type doped region and a third P-type doped region in the N-type region, and a gate above a region between the first N-type doped region and the second P-type doped region. The gate is connected with the second P-type doped region, the second N-type doped region is connected with the first P-type doped region as a negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected as a positive electrode of the electrostatic discharge protection device. The application can reduce the triggering voltage of the device and improve the holding current.