374 results about "Electrostatic discharge protection" patented technology

The invention discloses an IO pin multiplexing circuit, a control method, a chip and electronic equipment, and the circuit comprises a gating module which is connected with a chip core and is used for transmitting a first enabling signal and / or a second enabling signal according to an on-chip control signal; the control word coding module is respectively connected with the gating module and the off-chip, and is used for enabling an IO pin to work in a control word coding mode according to the first enable signal; the digital signal input module is respectively connected with the gating module and is used for enabling an IO pin to work in a digital signal input mode according to a second enable signal; and the ESD module is connected with the digital signal input module and the control word coding module and is used for providing electrostatic protection. According to the invention, a pin function multiplexing technology is adopted, a control word writing function can be realized when the chip is just started through an enable signal switching function, a digital signal transmission function can be realized when the chip normally runs, the hardware cost is reduced, and the consumption of pin resources is reduced.

An electro-static discharge (ESD) protection circuit includes an ESD current discharge circuit including a first transistor, a second transistor, and a third transistor, connected in series and connected between a pad and a ground voltage, an ESD detection circuit configured to turn on the third transistor when the ESD event occurs, and a bias generation circuit configured to provide a bias voltage for turning on the first transistor to a gate of the first transistor when the ESD event occurs.

The invention relates to the technical field of semiconductors, in particular to a high-temperature reverse bias test method, an electrostatic discharge protection structure and electronic equipment, and the method comprises the steps: providing the electrostatic discharge protection structure; determining an initial leakage current at the initial voltage, and determining an initial breakdown voltage at the initial current; heating the electrostatic discharge protection structure for a preset time at a preset temperature and a preset voltage, and determining a target leakage current of the heated electrostatic discharge protection structure under the initial voltage and a target breakdown voltage of the heated electrostatic discharge protection structure under the initial current; performing current change analysis on the initial leakage current and the target leakage current to obtain a current change result, and performing voltage change analysis on the initial breakdown voltage and the target breakdown voltage to obtain a voltage change result; and according to the current change result and the voltage change result, generating a high-temperature reverse bias test result of the electrostatic discharge protection structure. According to the invention, the reliability of the electrostatic discharge protection structure can be accurately evaluated.

The utility model provides a kind of electrostatic discharge protection circuit and low noise amplification module, the electrostatic discharge protection circuit is applied to low noise amplification circuit, the low noise amplification circuit includes input matching circuit and the low noise amplifier of the output end being connected to the input matching circuit;The electrostatic discharge protection circuit includes inductance and resistance;The first end of the inductance is used to connect to the signal input end of low noise amplifier;The first end of the resistance is connected to the second end of the inductance, and the second end of the resistance is grounded.The electrostatic discharge protection circuit in the utility model is connected to the input end of low noise amplifier, and the noise coefficient of low noise amplifier will not be deteriorated, and the performance of low noise amplifier will not be affected, and the input stability of low noise amplifier will not be affected simultaneously.

The invention discloses a chip electrostatic discharge protection method, a related device, electronic equipment and a storage medium, and the method comprises the steps: determining a first region where a target power domain is located in a chip layout based on layout planning data in the chip layout, and constructing an initial layout consistent with the chip layout in specification; filling a second region corresponding to the first region in the initial layout with a target device unit matched with the voltage type of the target power supply domain; safety verification about chip electrostatic discharge is carried out on the target layout passing the functional check, and a verification result is obtained; and in response to the verification result representing that the security verification is not passed, setting a discharge unit in the target layout, and returning to the step of performing the security verification about chip electrostatic discharge on the target layout passing the functional check to obtain the verification result until the verification result representing that the security verification is passed. According to the scheme, the efficiency and quality of constructing the chip electrostatic discharge protection network can be improved.

The present disclosure relates to a bulk acoustic wave (BAW) device with electrostatic discharge (ESD) protection. The disclosed BAW device includes a substrate (106), an ESD protection layer (106) over the substrate (106), a first bottom reflector (109-1) over the ESD protection layer (108), a first bottom electrode (112-1) over the first bottom reflector (109-1), a first top electrode (118-1) vertically aligned with the first bottom electrode (112-1), and a piezoelectric layer (116C) vertically between the first bottom electrode (112-1) and the first top electrode (118-1). Herein, the ESD protection layer (108) is electrically insulating and eligible to achieve at least a 400 V breakdown voltage with a 200 nm thickness. The first bottom reflector (109-1) includes a stack of alternating high acoustic impedance conductive layers (120A-E) and low acoustic impedance conductive layers (120A-E). The first bottom electrode (112-1) is electrically connected to the first bottom reflector (109-1). A breakdown voltage of the piezoelectric layer (116C) is no more than the breakdown voltage of the ESD protection layer (108).

A physiological signal monitoring device includes a base and a transmitter. The base is provided with a biosensor. The transmitter is removably coupled to the base, and includes a casing and an electrostatic-discharge protective unit. The casing has a socket for the biosensor to be removably inserted thereinto. The electrostatic-discharge protective unit is disposed to at least surround the periphery of the socket to dispel static electricity when electrostatic discharge occurs.

An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.

An ESD includes a detection circuit, a P-type transistor, a N-type transistor, and a discharge circuit. The detection circuit detects whether an electrostatic discharge event occurs on a first power bonding pad to generate first and second detection signals. The first P-type transistor is coupled between the first power bonding pad and a first node and receives the first detection signal. The first N-type transistor is coupled between the first node and a second power bonding pad and receives the second detection signal. The discharge circuit is coupled between the first power bonding pad and the second power bonding pad and controlled by a control signal on the first node. In response the electrostatic discharge event occurring on the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and the second power bonding pad according to the control signal.

An ESD protection circuit using GaN devices, with a ESD block including a first 2 DEG resistor with one terminal coupled to a gate of a power HEMT, a first trigger with one terminal coupled to another terminal of the first 2 DEG resistor and with another terminal coupled to a reference voltage, a first LV-HEMT with a first gate coupled to the another terminal of the first 2 DEG resistor and a first drain couple to the gate, a second trigger with one terminal coupled to the gate, a second 2 DEG resistor with one terminal coupled to another terminal of the second trigger and another terminal coupled to the reference voltage, and a second LV-HEMT with a second gate coupled to the another terminal of the second trigger and a second drain coupled to the first source and a second source coupled to the reference voltage.

An electrostatic discharge (ESD) protection circuit protecting a core circuit and including a first high electron mobility transistor (HEMT), a second HEMT, a first current clamping circuit, a second current clamping circuit, and a resistor is provided. The first HEMT is coupled to a first input terminal. The second HEMT is coupled between the first HEMT and a second input terminal. The first current clamping circuit includes a third HEMT. The third HEMT is coupled between the gate of the first HEMT and the second input terminal. The second current clamping circuit is coupled between the first input terminal and the gate of the second HEMT. The resistor is coupled between the first input terminal and the core circuit. The core circuit is coupled to the second input terminal.

An ESD (electrostatic discharge) protection device includes a first enhancement mode HEMT (high-electron-mobility transistor) electrically connected between a protected node and a grounded node, and an RC network electrically connected between the protected node and the grounded node, The time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for positive transient pulses at the protected node having a rise time less than the time constant of the RC network. The first enhancement mode HEMT is configured to shunt the protected node to the grounded node when on.

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes first and second N-type deep well (DNW) regions in a P-type semiconductor substrate, first to fourth N-type and P-type doped regions, and first and second P-type well (PW) regions. The first N-type and P-type doped regions and the first PW region are located in the first DNW region. The second N-type and P-type doped regions and the second PW region are located in the second DNW region. The third and fourth N-type and P-type doped regions are located in the first and second PW regions. The first P-type and fourth N-type doped regions are connected to an input / output terminal. The first N-type and second P-type doped regions are connected to a power supply terminal. The third N-type and the fourth P-type doped regions are connected to a ground terminal.

An ESD (electrostatic discharge) protection device includes a first enhanced HEMT (High Electron Mobility Transistor) electrically connected between a protected node and a ground node, and an RC network electrically connected between the protected node and the ground node. A time constant of the RC network is set such that a gate of the first enhancement mode HEMT is pulled up to turn on the first enhancement mode HEMT for a positive transient pulse at the protected node having a rise time less than the time constant of the RC network. The first enhanced HEMT is configured to shunt a protected node to a ground node when turned on.

An integrated circuit including: two or more substrates stacked one over another and including first and second substrates having a P-type doping, and third and fourth substrates having an N-type doping; the first substrate including a first dielectric isolation structure electrically separating the first substrate into first and second portions; the second substrate including a second dielectric isolation structure electrically separating the second substrate into first and second portions a set of electrical components on one or more of the two or more substrates, and configured to form a circuit, the circuit comprising an internal ground node; a ground reference rail electrically connected to the first substrate and the second substrate and free from being electrically connected to the third substrate and the fourth substrate; and an electrostatic discharge (ESD) protection circuit electrically coupled between the internal ground node and the ground reference rail.

The disclosure provides an electrostatic discharge (ESD) protection device for protecting a core circuit coupled between a first power rail and a second power rail. The ESD protection device includes a pull-up element. The pull-up element includes a bidirectional switch element. A first terminal of the bidirectional switch element is coupled to a third power rail. A second terminal of the bidirectional switch element is coupled to a signal transmission wire. The core circuit is coupled to a signal connection pad through the signal transmission wire. A control terminal of the bidirectional switch element is coupled to a control circuit or a reference voltage.

An electrostatic discharge protection device includes: a substrate; a first doped region of the first conductivity type on the substrate; a second doped region of the first conductivity type on the substrate; an epitaxial layer of a second conductivity type between the first doped region and the second doped region; a first diffusion region of the first conductivity type on the first doped region; a second diffusion region of a second conductivity type on the epitaxial layer; a third diffusion region of the first conductivity type on the second doped region; and a fourth diffusion region of the second conductivity type on the first doped region and spaced apart from the first diffusion region. The first diffusion region and the fourth diffusion region are electrically bonded.

A semiconductor package and semiconductor die, the semiconductor package including at least a first die. The first die includes internal circuitry disposed on a substrate, electrostatic discharge (ESD) protection circuitry disposed on the substrate but laterally spaced from the internal circuitry and including a first charge dissipation element, and a first silicon controlled rectifier (SCR) laterally adjacent.

The application provides an electrostatic discharge protection device and a chip. The device comprises a substrate, a P-type region and an N-type region in the substrate, a first N-type doped region, a second N-type doped region, a first P-type doped region and a second P-type doped region in the P-type region, the second P-type doped region being between the first N-type doped region and the second N-type doped region, and the first N-type doped region being between the first P-type doped region and the second P-type doped region, a third N-type doped region and a third P-type doped region in the N-type region, and a gate above a region between the first N-type doped region and the second P-type doped region. The gate is connected with the second P-type doped region, the second N-type doped region is connected with the first P-type doped region as a negative electrode of the electrostatic discharge protection device, and the first N-type doped region, the third N-type doped region and the third P-type doped region are connected as a positive electrode of the electrostatic discharge protection device. The application can reduce the triggering voltage of the device and improve the holding current.

Structures including an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate having a top surface, an electrostatic discharge protection device including a base in the semiconductor substrate, and first and second trench isolation regions disposed in the base of the electrostatic discharge protection device. The first trench isolation region extends from the top surface of the semiconductor substrate to a first depth in the base, the second trench isolation region extends from the top surface of the semiconductor substrate to a second depth in the base, and the second depth greater than the first depth.

The invention provides an electrostatic discharge protection device which is used for protecting a core circuit coupled between a first power rail line and a second power rail line. The electrostatic discharge protection device comprises a first electrostatic discharge clamping circuit, a second electrostatic discharge clamping circuit and a pull-up assembly. The first electrostatic discharge clamping circuit is coupled between the first power rail and the common node. The second electrostatic discharge clamp circuit is coupled between the common node and the second power rail. The first end of the pull-up component is coupled to the common node. The second end of the pull-up assembly is coupled to the signal transmission wire. The core circuit is coupled to the signal connection pad through the signal transmission wire.

A circuit includes an electrostatic discharge protection circuit disposed along a major surface of a substrate, an internal circuit also disposed along the major surface but laterally spaced from the electrostatic discharge protection circuit, and a coupling capacitor operatively coupled and physically disposed between the electrostatic discharge protection circuit and the internal circuit. The coupling capacitor includes a first metal element formed in a first one of a plurality of metallization layers disposed over the major surface, and a second metal element also formed in the first metallization layer. A number of the metallization layers vertically disposed between the first metallization layer and the major surface is equal to or less than 1.

An electrostatic discharge protection device is provided. The electrostatic discharge protection device includes an N-type deep well region (DNW), first and second high-voltage P- and N-type well regions (first and second HVPW and HVNW), a low-voltage N-type well region (LVNW), first and second P- and first N-type doped regions in a P-type semiconductor substrate, and a gate structure. The first and second HVPW and HVNW are located on the DNW. The LVNW is located on the first HVPW. The first P- and N-type doped regions and second P-type doped region are located on the LVNW and the second HVNW and HVPW. The first P-type doped region is electrically connected to a first voltage source. The gate structure on the first and second HVPW and the first HVNW, the second P-type doped region and the first N-type doped region are electrically connected to a second voltage source.

A segmented bottom-emitting OLED device compromising an array of multiple OLED segments arranged on a common transparent substrate, where the array forms an emitting area where each segment is separated by a non-emitting gap; wherein each OLED segment is defined by a transparent bottom electrode segment, organic layers for light emission, and a top electrode; wherein between the bottom electrode and the substrate in at least one OLED segment, there is a transparent insulating layer that is closer to the bottom electrode segment and a transparent conductive layer that is closer to the substrate.

This application illustrates an electro-static discharge protection structure and an electronic device. One end of a pressure-sensitive elastic component is connected to a metal housing, the other end of the pressure-sensitive elastic component extends in a direction away from the metal housing. A border frame includes a connection part—and a first side edge. A conductive layer is disposed on a side, facing the pressure-sensitive elastic component, of the connection part. The one end of the pressure-sensitive elastic component—is connected to the conductive layer, and the other end of the pressure-sensitive elastic component is connected to the metal housing.

The invention provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is coupled between the first pad and the second pad. The electrostatic discharge protection circuit comprises a substrate, a second conductive transistor structure, a resistor structure and a silicon controlled rectifier structure. The substrate has a first conductivity type. The second conductive type transistor structure is located in the substrate and is provided with a gate end. The resistive structure is in the substrate and includes a first resistor. A gate terminal of the second conductivity type transistor structure is coupled to the second pad through the resistive structure. The silicon-controlled rectifier structure is located in the substrate and is provided with a first end, a second end and a third end. A first terminal of the silicon controlled rectifier structure is coupled to the first pad, a second terminal of the silicon controlled rectifier structure is coupled to the second pad, and a third terminal of the silicon controlled rectifier structure is coupled to a gate terminal of the second conductivity type transistor structure.

The invention provides an input / output driver which comprises an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is provided with a silicon controlled rectifier and comprises first to fourth heavily doped regions which are respectively arranged in surface layer regions of first to fourth well regions of a substrate. The first well region to the fourth well region are sequentially arranged along the first direction and are adjacent to each other. The first well region, the third well region, the first heavily doped region and the third heavily doped region have a first conductivity type. The second well region, the fourth well region, the second heavily doped region and the fourth heavily doped region have a second conductivity type. The second heavily doped region further extends into the first well region and the third well region and is next to the first heavily doped region and the third heavily doped region, and the fourth heavily doped region further extends into the third well region and is next to the third heavily doped region.

The invention discloses an electrostatic discharge protection device, which comprises a clamping bipolar junction transistor and at least one electrostatic discharge circuit, and the electrostatic discharge circuit is coupled between a first voltage rail and a second voltage rail. The electrostatic discharge circuit comprises a silicon controlled rectifier and a diode. An anode and a cathode of the silicon controlled rectifier are respectively coupled to an input / output (I / O) port and a first voltage rail. The cathode of the diode is coupled to the anode of the silicon controlled rectifier and the I / O port. An anode of the diode is coupled to the second voltage rail. The absolute value of the reverse breakdown voltage of the diode is larger than the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier, and the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier is larger than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

ESD Protection Circuit This description relates to an electrostatic discharge protection circuit (Cesd2). An electrostatic discharge dissipation component (Cesd1) has a first conduction terminal (A1), a second conduction terminal (A2), and a control terminal (C). Identical first and second devices (Dev1, Dev2) each have first (A3) and second (A4) conduction terminals, with the respective first terminals (A3; A3') of the first and second devices (Dev1, Dev2; Dev1', Dev2') connected to the control terminal (C) of the component, and the respective second terminals (A4) of the first and second devices (Dev1, Dev2) connected to the component's first terminal (A1; A1') and second terminal (A2), respectively. Figure for the abstract: Fig. 2

An electrostatic discharge (ESD) protection device is proposed. The ESD protection device may include a semiconductor substrate, an epitaxial region formed on the semiconductor substrate, a well region formed on the epitaxial region, and a P+ diffusion region formed on the well region. The ESD protection device may also include an N+ diffusion region formed on the well region, an anode connected to the P+ diffusion region, a cathode connected to the N+ diffusion region, and a first ESD mask formed on the well region. P+ ions having predefined concentration and energy are injected through the first ESD mask.