718 results about "Silicide" patented technology

The invention relates to a high-temperature-resistant light stealth coating material and a preparation method thereof, and belongs to the technical field of functional materials, the high-temperature-resistant light stealth coating material comprises the following raw materials: boride, silicide, a titanate fluxing agent, metal coated carbide, a zinc oxide coated nano carbon material and a sintering aid; according to the prepared high-temperature-resistant light stealth coating material, the infrared emissivity at the wavelength of 3-5 [mu] m is 0.231-0.245, the infrared emissivity at the wavelength of 8-14 [mu] m is 0.424-0.441, the tensile bonding strength is 40.8-46.4 MPa, and the thermal shock resistance frequency is 153-167.

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

The invention relates to the technical field of brake discs, in particular to a carbon-ceramic brake disc with a composite functional layer and a preparation method of the carbon-ceramic brake disc. The problems that a brake disc is insufficient in strength and poor in ablation resistance are solved. The preparation method comprises the following steps: carrying out low-temperature plasma treatment and silicon dioxide sol impregnation on carbon fibers, and inserting a graphene oxide film between woven layers, so as to obtain a carbon fiber preform; primary densification is carried out through pretreatment activation, low-temperature permeation and high-temperature permeation, and two graphitization treatments are combined; siliconizing is carried out through low-pressure permeation, high-pressure strengthening and laser cladding, and secondary densification is carried out through precursor impregnation and cracking; the titanium zirconium silicide-nano aluminum oxide composite layer generated through the embedding process forms a compact oxidation film at high temperature, and the silicon carbide nano crystal whiskers are subjected to chemical vapor deposition, so that the strength and ablation resistance of the prepared carbon ceramic brake disc are improved.

The invention provides a silicon-carbon negative electrode material with a core-shell structure and a preparation method and application of the silicon-carbon negative electrode material. The preparation method comprises the following steps: sequentially preparing a sacrificial layer and a carbon coating layer for coating silicon particles on the surfaces of the silicon particles to form a carbon-coated silicon material; etching the carbon-coated silicon material by adopting an etching agent capable of etching the sacrificial layer, and removing the sacrificial layer in the carbon-coated silicon material to form a silicon-carbon material; dipping the silicon-carbon material in a metal precursor solution, taking out the silicon-carbon material, and drying the silicon-carbon material, wherein simple substances of metal elements in the metal precursor and / or silicides of the metal elements can catalyze the generation of the carbon nanotubes; heating the dried silicon-carbon material in a reducing gas atmosphere to form a catalyst on the surfaces of the silicon particles, the catalyst comprising simple substances of metal elements and / or silicides thereof; and depositing carbon nanotubes on the basis of the elementary substance of the metal element and / or the silicide thereof. The high-rate cycle performance of a battery prepared from the core-shell structure silicon-carbon negative electrode material is obviously improved.

The present invention provides a multi-layer doping source structure, and a high-quality emitter and a controllable preparation method therefor. The multi-layer doping source structure comprises a dielectric layer, a nitrogen silicide layer and a doping source layer, which are stacked on the front surface of a crystalline silicon substrate, wherein the dielectric layer is a silicon oxide film or a silicon oxynitride film, the doping source layer is boron-doped amorphous silicon doped with functional elements or phosphorus-doped amorphous silicon doped with functional elements, and the functional elements doped in the doping source layer are carbon and / or nitrogen. In the present invention, the doping source structure is composed of the dielectric layer, a nitrogen silicide and boron- / phosphorus-doped amorphous silicon doped with functional elements; the multi-layer doping source structure has both a strong laser absorption capability and a high boron or phosphorus doping concentration, thereby facilitating a reduction in the laser power and the illumination time required by a laser selective emitter technique; moreover, such a multi-layer doping source structure is favorable for reducing the surface boron concentration, decreasing defects and improving the passivation effect of an emitter, and therefore an improvement in battery efficiency can be promoted.

The invention discloses solar conductive silver paste and a preparation method and application thereof, and the preparation raw materials of the solar conductive silver paste comprise the following components in parts by weight: 65-92 parts of silver powder, 2-30 parts of silicide powder, 1-5 parts of glass powder and 4-15 parts of an organic carrier. By selecting the silicide powder and controlling the mass ratio of the silicide to the silver powder to be within the range, on one hand, the silver-silicon contact quality of a solar cell is improved, and the solar conductive silver paste capable of improving the photoelectric conversion efficiency is developed.

The invention provides an OPC (Optical Proximity Correction) method for regulating and controlling the resistance of a high-resistance sheet, which comprises the following steps of: 1, delimiting a layout area where a high-resistance layer and a silicide barrier layer are located in an original layout, and determining the resistance value of the high-resistance sheet according to the layout area; and 2, according to the resistance value of the sheet resistor of the high-resistance layer determined in the step 1, reducing the width of the overlapped part of the high-resistance layer and the silicide barrier layer. The resistance value of the high-resistance layer sheet resistor is regulated and controlled by changing the shape of the high-resistance layer in the layout, the position of a contact hole does not need to be adjusted, and more flexible layout design elasticity under different manufacturing processes is provided.

A pellicle including a pellicle membrane with improved stability to hydrogen plasma is provided. The pellicle membrane includes a plurality of carbon nanotubes (CNTs), where at least one carbon nanotube (CNT) of the plurality of CNTs is coated by a protection coating. The protection coating includes a plurality of nanostructures that includes a transition metal or an oxide, nitride, silicide or carbide thereof on a surface of the at least one CNT of the plurality of CNTs, a carbon-based diffusion barrier layer over at least the plurality of nanostructures, and a capping layer over at least the carbon-based diffusion barrier layer. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

The invention discloses a preparation method of an ultrahigh-temperature ceramic matrix modification and coating integrated carbon-based composite material, and belongs to the technical field of matrix modification and coating integrated carbon-based composite material preparation. Two functional materials are laid on the surface of low-density carbon / carbon (C / C) in a layered mode, infiltration powder on the inner layer is used for matrix modification, and coating powder on the outer layer is used for in-situ coating generation. And finally, applying pressure in a vacuum environment through an SPS process, so that the silicide alloy melt permeates into the C / C matrix under the assistance of the molten salt to generate carbide, and meanwhile, the outer-layer powder is converted into a compact ceramic coating in situ. The method is based on the SPS technology, and matrix modification and coating in-situ generation are synchronously achieved through a one-step method. According to the method, the thickness of the coating is controlled by regulating and controlling the quality of powder, and strong interface bonding of the coating and a modified matrix is achieved through melt permeation and interface mechanical occlusion.

The invention provides a semiconductor structure and a preparation method thereof. A through hole is formed in a glass substrate based on a through hole layout pattern; respectively forming a first metal layer and a second metal layer on the first surface and the second surface, and forming a connecting metal layer in the through hole; etching the first metal layer and the second metal layer at the same time to obtain a first patterned metal layer and a second patterned metal layer; forming a first dielectric layer on the first patterned metal layer; the first dielectric layer is made of silicide; performing etching processing on the first dielectric layer based on the through hole layout pattern, so that the connecting metal layer in the through hole is exposed in the first dielectric layer; and forming a connection structure above the connection metal layer to obtain a first semiconductor structure. The semiconductor structure can have a low thermal expansion coefficient, the semiconductor structure can be prevented from being damaged when the semiconductor structure is subjected to annealing and other processes with large temperature differences, stress changes on the surfaces of the two sides of the glass substrate can be more consistent, and the product yield of the semiconductor structure is increased.

The invention discloses high-entropy aluminum silicide ceramic as well as a preparation method and application thereof. The preparation method of the high-entropy aluminum silicide ceramic comprises the following steps: 1) fully and uniformly mixing transition metal powder, aluminum powder and silicon powder to prepare mixed powder; 2) pressing the mixed powder into a green body, and then performing electric field sintering, crushing and screening to obtain high-entropy aluminum silicide powder; and 3) pressing the high-entropy aluminum silicide powder into a green body, and carrying out spark plasma sintering to obtain the high-entropy aluminum silicide ceramic. The high-entropy aluminum silicide ceramic disclosed by the invention has excellent oxidation resistance and ablation resistance under an ultra-high-temperature condition, is suitable for being used as a hot end part protection material of a hypersonic aircraft, and is simple and convenient in preparation process, simple to operate, short in reaction time and suitable for large-scale industrial production and application.

A semiconductor device including a substrate having an insulating pattern, a channel pattern disposed on the insulating pattern a source / drain pattern disposed adjacent to the plurality of semiconductor patterns, a gate electrode disposed on the plurality of semiconductor patterns, a lower power line disposed in a lower portion of the substrate, a lower insulating pattern disposed between the source / drain pattern and the insulating pattern, a backside active contact disposed below the source / drain pattern, and a backside silicide pattern disposed between the source / drain pattern and the backside active contact. In one aspect, the backside active contact penetrates the substrate and the lower insulating pattern and is electrically connects the lower power line and the source / drain pattern. In one aspect, the backside active contact and the backside silicide pattern are vertically overlapped with the doping layer.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate comprising a high-resistance region, and forming a high-resistance region groove in the high-resistance region; a first dielectric layer and a high-resistance component are sequentially formed in the high-resistance region groove, the first dielectric layer is formed at the bottom of the high-resistance region groove, the surface of the first dielectric layer is lower than the surface of the substrate, the high-resistance component is located on the first dielectric layer, and the top surface of the high-resistance component is higher than the surface of the substrate; forming a silicide barrier layer on the substrate and the high-resistance component, wherein the silicide barrier layer at least exposes part of the top surface of the high-resistance component; forming a silicide layer on the exposed high-resistance part; a high-resistance region connecting piece connected with the high-resistance structure is formed in the high-resistance region, the high-resistance structure comprises a first dielectric layer located in the high-resistance region groove, a high-resistance component and a silicide layer located on the high-resistance component, and the high-resistance region connecting piece is connected with the silicide layer on the high-resistance component. According to the invention, the technological process is optimized, the quality of the high-resistance region connecting piece is improved, and the contact resistance is reduced.

The invention provides a micron-scale high-melting-point oxide sheet layer enhanced ultra-high-temperature ceramic-based anti-ablation composite coating and a preparation method thereof.The preparation method comprises the steps that ultra-high-temperature carbide / boride ceramic powder, silicide powder and high-melting-point metal oxide powder are mechanically mixed, and spraying mixed powder with uniform components is obtained; the mixed powder is sprayed on the surface of a base body in a plasma spraying mode, and the ultra-high-temperature ceramic-based anti-ablation composite coating containing a micron-scale oxide lamellar structure is obtained; the lamellar high-melting-point oxide phase is introduced into the ultrahigh-temperature ceramic-based composite silicide coating, so that the problem that the silicon-containing glass phase is easy to lose and splash under high-heat-flow scouring is effectively solved. The high-melting-point oxide sheet layer serves as a physical barrier, can effectively limit flowing of a silicon-containing glass liquid phase in the ablation process and allows gaseous oxidation products to escape at the same time, so that a firmly-attached composite oxide layer is formed, and the oxidation resistance and the anti-scouring and anti-stripping capacity of the coating are greatly improved.

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source / drain features on opposite sides of the dummy gate structures and over the first fin, forming second source / drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source / drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source / drain features, and forming second silicide features over the second source / drain features.

The method comprises the following steps: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric over the contact etch stop layer; and performing an etching process to form contact openings in the interlayer dielectric and the contact etch stop layer. The source / drain region is exposed to the contact opening. A silicide formation process is performed to form a silicide region on a surface of the source / drain region. An etch process is performed to remove metal deposited on the dielectric region, where the dielectric region is exposed during the first silicide formation process. A contact plug is formed in the contact opening. The embodiment of the invention also relates to a method for forming the semiconductor device.

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

The invention relates to the field of metal materials, in particular to an Nb-Si-Ni-Ti series novel ultrahigh-temperature structural material and a rapid directional solidification preparation method thereof. The preparation method provided by the invention is a rapid directional solidification preparation method of an Nb4NiSi-reinforced Nb-Si-Ni-Ti series novel ultra-high-temperature structural material, the alloy is mainly composed of an Nb4NiSi phase and an Nb solid solution phase through component design, and a laser direct deposition method controlled by a temperature field is adopted to prepare the Nb4NiSi-Ni-Ti series ultra-high-temperature structural material. The microstructure of the Nb-Si-Ni-Ti series novel ultra-high-temperature structural material is formed by alternately and directionally arranging Nb4NiSi and Nb solid solutions. According to the alloy, the high-temperature strength of the alloy is provided by the Nb4NiSi ternary silicide, the room-temperature ductility and toughness of the alloy are provided by the Nb-based solid solution, and the alloy is arranged in a fine directional structure, has relatively excellent room-high-temperature mechanical property and can be applied to application scenes such as aero-engine turbine blades needing ultrahigh-temperature structural materials.

A method includes forming a first semiconductor fin on a substrate, forming a source / drain region in the first semiconductor fin, depositing a capping layer on the source / drain region, where the capping layer includes a first boron concentration higher than a second boron concentration of the source / drain region, etching an opening through the capping layer, the opening exposing the source / drain region, forming a silicide layer on the exposed source / drain region and forming a source / drain contact on the silicide layer.

According to the Ta-based refractory alloy reinforced by the silicide phase eutectic structure and the preparation method of the Ta-based refractory alloy reinforced by the silicide phase eutectic structure, nanoscale HfSi2 powder is introduced, and the alloy reinforced by the silicide phase eutectic structure is formed in the Ta-based alloy. According to the alloy, particles or powder of refractory metal elements such as Ta serves as a matrix raw material, nanoscale HfSi2 powder is introduced into the matrix raw material, an alloy ingot is prepared through a smelting process, and the alloy material is subjected to sufficient deformation recovery and homogenization through multiple times of pressure processing and high-temperature vacuum annealing treatment. A multi-level spherical eutectic structure exists in the alloy prepared through the method, the silicide phase serves as a strengthening phase, dislocation movement can be effectively inhibited, and the room-temperature mechanical property of the alloy is remarkably enhanced. The room temperature tensile elongation is about 30%, the yield strength is about 600 MPa, the tensile strength is about 700 MPa, and compared with a traditional Ta-based alloy, the tensile strength is obviously improved. The alloy of the system can be widely applied to structural parts by means of plastic deformation processing, heat treatment and the like.

A method of manufacturing a semiconductor memory device includes forming, on a substrate, a channel structure including a channel pattern; forming, on the channel structure, a silicide material layer including an alloy of a semiconductor material and a metal including a eutectic composition; forming a sacrificial semiconductor layer between the channel structure and the silicide material layer and forming a mold layer surrounding the sacrificial semiconductor layer; forming a capacitor hole by removing the sacrificial semiconductor layer; forming a lower electrode that fills the capacitor hole; removing the mold layer; forming a capacitor dielectric layer that covers a surface of the lower electrode; and forming an upper electrode that covers the capacitor dielectric layer.

A method for forming a semiconductor device including forming a stack of alternating channel layers and sacrificial layers over a substrate, forming a gate structure over a portion of the stack to define a channel region, etching the stack in a region adjacent to the gate structure to form a source / drain recess, forming an epitaxial bottom layer along a bottom surface and opposing sidewalls of the source / drain recess, wherein the epitaxial bottom layer contacts the channel layers and a dielectric spacer adjacent to the gate structure. The method also includes depositing an etch stop layer over the epitaxial bottom layer, the etch stop layer having a germanium concentration higher than the epitaxial bottom layer, filling the remaining portion of the source / drain recess with a sacrificial semiconductor layer, removing and replacing the gate structure with a replacement gate stack, selectively removing the sacrificial semiconductor layer to expose the etch stop layer, reacting the etch stop layer to form a silicide layer, and forming a source / drain contact to fill the source / drain recess, wherein the source / drain contact is a bar-shaped plug extending vertically between adjacent channel regions, the source / drain contact is enclosed on a bottom and at least two opposing sides by the silicide layer and the epitaxial bottom layer, and the silicide layer comprises an upper portion in contact with the source / drain contact and a lower portion in contact with the epitaxial bottom layer.

Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

Backside and frontside contact structures wrapping around source / drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source / drain regions provides source / drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source / drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

A semiconductor device includes a lower interlayer insulating layer, an insulating pattern extending in a first horizontal direction on a top surface of the lower interlayer insulating layer, first, second, and third gate electrodes extending in a second horizontal direction and arranged in the first horizontal direction, a first source / drain region between the first and second gate electrodes and a second source / drain region between the second and third gate electrodes on the insulating pattern, a lower source / drain contact extending into the second source / drain region by vertically penetrating the lower interlayer insulating layer and the insulating pattern, a top of the lower source / drain contact being higher than a top surface of the insulating pattern, a first insulating liner layer on both sidewalls of the lower source / drain contact, and a lower silicide layer between the second source / drain region and the lower source / drain contact.

An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source / drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source / drain region and extending vertically along a sidewall of the silicide. A source / drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.

The disclosure relates to improved design and fabrication of power devices. A device and a method of forming the same are described. A device includes a unit cell formed at least partially within a SiC substrate, the unit cell including: a trench defined in an upper surface of the SiC substrate; a silicide layer disposed on at least one surface of the trench; a first conductivity type drift region formed in the SiC substrate and having a first thickness; a first conductivity type source region formed within the SiC substrate and having a second thickness; the second thickness is smaller than the first thickness; the second conductive type well region is formed in the SiC substrate; wherein the device includes a vertical SiC DMOSFET including a drain terminal disposed on a backside of the SiC substrate and a source terminal disposed on a top surface of the SiC substrate and in a trench, such that a portion of the source terminal outside the trench is disposed over and conductively coupled to a non-trench surface of the source region; the source region is disposed adjacent to and between the trench and the well region.