504 results about "Silicide" patented technology

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

The invention provides a silicon-carbon negative electrode material with a core-shell structure and a preparation method and application of the silicon-carbon negative electrode material. The preparation method comprises the following steps: sequentially preparing a sacrificial layer and a carbon coating layer for coating silicon particles on the surfaces of the silicon particles to form a carbon-coated silicon material; etching the carbon-coated silicon material by adopting an etching agent capable of etching the sacrificial layer, and removing the sacrificial layer in the carbon-coated silicon material to form a silicon-carbon material; dipping the silicon-carbon material in a metal precursor solution, taking out the silicon-carbon material, and drying the silicon-carbon material, wherein simple substances of metal elements in the metal precursor and / or silicides of the metal elements can catalyze the generation of the carbon nanotubes; heating the dried silicon-carbon material in a reducing gas atmosphere to form a catalyst on the surfaces of the silicon particles, the catalyst comprising simple substances of metal elements and / or silicides thereof; and depositing carbon nanotubes on the basis of the elementary substance of the metal element and / or the silicide thereof. The high-rate cycle performance of a battery prepared from the core-shell structure silicon-carbon negative electrode material is obviously improved.

The invention discloses solar conductive silver paste and a preparation method and application thereof, and the preparation raw materials of the solar conductive silver paste comprise the following components in parts by weight: 65-92 parts of silver powder, 2-30 parts of silicide powder, 1-5 parts of glass powder and 4-15 parts of an organic carrier. By selecting the silicide powder and controlling the mass ratio of the silicide to the silver powder to be within the range, on one hand, the silver-silicon contact quality of a solar cell is improved, and the solar conductive silver paste capable of improving the photoelectric conversion efficiency is developed.

Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

The invention provides a micron-scale high-melting-point oxide sheet layer enhanced ultra-high-temperature ceramic-based anti-ablation composite coating and a preparation method thereof.The preparation method comprises the steps that ultra-high-temperature carbide / boride ceramic powder, silicide powder and high-melting-point metal oxide powder are mechanically mixed, and spraying mixed powder with uniform components is obtained; the mixed powder is sprayed on the surface of a base body in a plasma spraying mode, and the ultra-high-temperature ceramic-based anti-ablation composite coating containing a micron-scale oxide lamellar structure is obtained; the lamellar high-melting-point oxide phase is introduced into the ultrahigh-temperature ceramic-based composite silicide coating, so that the problem that the silicon-containing glass phase is easy to lose and splash under high-heat-flow scouring is effectively solved. The high-melting-point oxide sheet layer serves as a physical barrier, can effectively limit flowing of a silicon-containing glass liquid phase in the ablation process and allows gaseous oxidation products to escape at the same time, so that a firmly-attached composite oxide layer is formed, and the oxidation resistance and the anti-scouring and anti-stripping capacity of the coating are greatly improved.

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source / drain features on opposite sides of the dummy gate structures and over the first fin, forming second source / drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source / drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source / drain features, and forming second silicide features over the second source / drain features.

The method comprises the following steps: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric over the contact etch stop layer; and performing an etching process to form contact openings in the interlayer dielectric and the contact etch stop layer. The source / drain region is exposed to the contact opening. A silicide formation process is performed to form a silicide region on a surface of the source / drain region. An etch process is performed to remove metal deposited on the dielectric region, where the dielectric region is exposed during the first silicide formation process. A contact plug is formed in the contact opening. The embodiment of the invention also relates to a method for forming the semiconductor device.

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

A method includes forming a first semiconductor fin on a substrate, forming a source / drain region in the first semiconductor fin, depositing a capping layer on the source / drain region, where the capping layer includes a first boron concentration higher than a second boron concentration of the source / drain region, etching an opening through the capping layer, the opening exposing the source / drain region, forming a silicide layer on the exposed source / drain region and forming a source / drain contact on the silicide layer.

According to the Ta-based refractory alloy reinforced by the silicide phase eutectic structure and the preparation method of the Ta-based refractory alloy reinforced by the silicide phase eutectic structure, nanoscale HfSi2 powder is introduced, and the alloy reinforced by the silicide phase eutectic structure is formed in the Ta-based alloy. According to the alloy, particles or powder of refractory metal elements such as Ta serves as a matrix raw material, nanoscale HfSi2 powder is introduced into the matrix raw material, an alloy ingot is prepared through a smelting process, and the alloy material is subjected to sufficient deformation recovery and homogenization through multiple times of pressure processing and high-temperature vacuum annealing treatment. A multi-level spherical eutectic structure exists in the alloy prepared through the method, the silicide phase serves as a strengthening phase, dislocation movement can be effectively inhibited, and the room-temperature mechanical property of the alloy is remarkably enhanced. The room temperature tensile elongation is about 30%, the yield strength is about 600 MPa, the tensile strength is about 700 MPa, and compared with a traditional Ta-based alloy, the tensile strength is obviously improved. The alloy of the system can be widely applied to structural parts by means of plastic deformation processing, heat treatment and the like.

A method for forming a semiconductor device including forming a stack of alternating channel layers and sacrificial layers over a substrate, forming a gate structure over a portion of the stack to define a channel region, etching the stack in a region adjacent to the gate structure to form a source / drain recess, forming an epitaxial bottom layer along a bottom surface and opposing sidewalls of the source / drain recess, wherein the epitaxial bottom layer contacts the channel layers and a dielectric spacer adjacent to the gate structure. The method also includes depositing an etch stop layer over the epitaxial bottom layer, the etch stop layer having a germanium concentration higher than the epitaxial bottom layer, filling the remaining portion of the source / drain recess with a sacrificial semiconductor layer, removing and replacing the gate structure with a replacement gate stack, selectively removing the sacrificial semiconductor layer to expose the etch stop layer, reacting the etch stop layer to form a silicide layer, and forming a source / drain contact to fill the source / drain recess, wherein the source / drain contact is a bar-shaped plug extending vertically between adjacent channel regions, the source / drain contact is enclosed on a bottom and at least two opposing sides by the silicide layer and the epitaxial bottom layer, and the silicide layer comprises an upper portion in contact with the source / drain contact and a lower portion in contact with the epitaxial bottom layer.

Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

Backside and frontside contact structures wrapping around source / drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source / drain regions provides source / drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source / drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source / drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source / drain region and extending vertically along a sidewall of the silicide. A source / drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.

The disclosure relates to improved design and fabrication of power devices. A device and a method of forming the same are described. A device includes a unit cell formed at least partially within a SiC substrate, the unit cell including: a trench defined in an upper surface of the SiC substrate; a silicide layer disposed on at least one surface of the trench; a first conductivity type drift region formed in the SiC substrate and having a first thickness; a first conductivity type source region formed within the SiC substrate and having a second thickness; the second thickness is smaller than the first thickness; the second conductive type well region is formed in the SiC substrate; wherein the device includes a vertical SiC DMOSFET including a drain terminal disposed on a backside of the SiC substrate and a source terminal disposed on a top surface of the SiC substrate and in a trench, such that a portion of the source terminal outside the trench is disposed over and conductively coupled to a non-trench surface of the source region; the source region is disposed adjacent to and between the trench and the well region.

A molybdenum silicide layer is formed on a bottom surface in a recessed feature in a silicon or silicon-germanium substrate. The bottom surface may be a silicon or silicon-germanium. A first molybdenum lay er may be deposited on or over the molybdenum silicide layer to fill the recessed feature. In some cases, a second molybdenum layer may be formed on the molybdenum silicide layer. In some cases, the second molybdenum layer may be exposed to nitrogen radicals or nitrogen-containing radicals, forming a molybdenum nitride layer on the second molybdenum layer.

An exemplary device includes a frontside power rail disposed over a frontside of a substrate, a backside power rail disposed over a backside of the substrate, an epitaxial source / drain structure disposed between the frontside power rail and the backside power rail. The epitaxial source / drain structure is connected to the frontside power rail by a frontside source / drain contact. The epitaxial source / drain structure is connected to the backside power rail by a backside source / drain via. The backside source / drain via is disposed in a substrate, and a dielectric layer is disposed between the substrate and the backside power rail. The backside source / drain via extends through the dielectric layer and the substrate. A frontside silicide layer may be between the frontside source / drain contact and the epitaxial source / drain structure, and a backside silicide layer may be between the backside source / drain contact and the epitaxial source / drain structure, such that the epitaxial source / drain structure between silicide layers.

A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source / drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source / drain contact electrically connected to, and on, the source / drain region, and a silicide layer between the source / drain region and the source / drain contact which contacts contact with the second doping layer and extends to an upper surface of the source / drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source / drain region along side walls of the silicide layer.

The invention provides a dry etching method for a molybdenum silicide layer, and relates to the field of semiconductor mask plates. The method is used for performing dry etching pattern transfer on the molybdenum silicide phase shift layer in the phase shift mask. The method comprises the following steps of: 1, putting a patterned molybdenum silicide layer into an ICP (Inductively Coupled Plasma) dry etching machine; 2, mixed SF6 gas and Ar gas are introduced into the etching cavity; and 3, the plasma concentration is regulated and controlled by controlling the ICP source, the plasma bombardment kinetic energy is regulated and controlled through the RF source, and etching of the molybdenum silicide layer is completed. According to the dry etching method, SF6 and Ar are adopted as etching gas, a good etching selection ratio and good morphology can be obtained by controlling the gas proportion, the ICP power and the RF power, and the dry etching method has the advantages of being good in safety, low in production cost and the like.

A semiconductor structure includes a dielectric strip disposed between a first source drain region and a second source drain region and physically separating the first source drain region from the second source drain region; a first silicide liner (160) located directly below the first source drain region; and a second silicide liner located directly below the second source drain region, where the first silicide liner is a different material than the second silicide liner.

The invention relates to the technical field of coating preparation, in particular to a niobium alloy surface thermal spraying coating, a preparation method and application, according to the method, a silicide coating is prepared on the niobium alloy surface, halide reaction embedding siliconizing treatment is conducted, and the niobium alloy surface thermal spraying coating is obtained; the silicide coating is prepared on the surface of the niobium alloy through the thermal spraying technology, the rough surface can be formed, anchoring sites are provided for follow-up halide reaction embedding siliconizing treatment, in the follow-up halide reaction embedding siliconizing treatment process, silicon is diffused to a base body to react to form a siliconizing diffusion layer, and metallurgical bonding of a coating-base body interface is achieved. In addition, a continuous transition area is formed between the siliconizing diffusion layer and the silicide coating, stress concentration caused by component mutation is reduced, the risk of interface cracking is effectively reduced, the service life of the coating is prolonged, and the problems that in the prior art, the interface bonding force between a thermal spraying MoSi2-based silicide coating and a base body is poor, and the service life is short are solved.

Method for manufacturing a semiconductor device comprising the following steps: Exposing a source / drain region (82) through a first dielectric layer (88) and a second dielectric layer (87), wherein the source / drain region (82) is at least partially arranged in a semiconductor fin (52); after exposing the source / drain region (82) through the first dielectric layer (88) and the second dielectric layer (87), implanting (122) dopants into the second dielectric layer (87), wherein, in the implantation (122) of the dopants into the second dielectric layer (87), the dopants are also implanted along side walls of the first dielectric layer (88); after implanting (122) the dopants, recessing (129) the second dielectric layer (87) beneath the first dielectric layer (88); and Forming a silicide region (133) on the source / drain region (82), wherein the silicide region (133) is arranged in a direction perpendicular to the semiconductor fin (52) after the formation of the silicide region (133) between the source / drain region (82) and the first dielectric layer (88).

The application provides a ceramic composition, a silicon nitride and a preparation method thereof, and a ceramic product. According to mass parts, the ceramic composition comprises 80-100 parts of silicon nitride, 1-10 parts of a first sintering aid, 1-10 parts of a second sintering aid, 0.5-20 parts of a dispersing agent, 10-40 parts of a binder and 0.5-2 parts of an antifoaming agent. The first sintering aid is a non-oxidized magnesium-containing compound, and the second sintering aid is a rare earth silicide. When the raw material comprising the ceramic composition is used to prepare the silicon nitride ceramic, the thermal conductivity and the bending strength of the prepared silicon nitride ceramic can be simultaneously improved.

The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor device and methods of manufacture. The structure includes: a gate structure including a gate dielectric material and a gate electrode with a stepped feature; sidewall spacers on sidewalls of the gate electrode, the sidewall spacers including a notched feature adjacent to the gate electrode; and a silicide contact on a surface of the gate electrode, the silicide contact being free of breaks on the surface of the gate electrode.

A method for forming a contact for a source-drain of a gate all around structure incorporates exposing at least a portion of a nanosheet during formation of the contact. A method may include removing a source-drain material to form an exposed portion of a nanosheet material of at least one nanosheet, forming epitaxial contact layers on the source-drain material and the exposed portion of the nanosheet material, forming a silicide contact layer on at least the epitaxial contact layers, and forming a contact with a metal material on the silicide contact layer. In some embodiments, an exposed portion of the nanosheet material comprises an entire end of at least one nanosheet alone or in conjunction with at least a portion of another nanosheet or in conjunction with an entire end of at least one other nanosheet.

The invention relates to a continuous high doping concentration in an epitaxial region. A method includes forming a plurality of semiconductor nanostructures. An upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, where the source / source recess has an intermediate vertical line. A first semiconductor layer is formed from a plurality of semiconductor nanostructures, where the first semiconductor layer includes dopants having a conductivity type, and the conductivity type is p-type or n-type. A second semiconductor layer is formed over the first semiconductor layer, where the second semiconductor has a vertical and elongated high dopant region aligned with an intermediate vertical line. A silicide region coupled with the second semiconductor layer is formed over the second semiconductor layer.

The invention discloses a solid solution precursor-silicide synergistic infiltration modified C / C composite material and a preparation method thereof, and belongs to the field of thermal protection C / C composite material matrix modification. The method comprises the following steps: embedding a low-density C / C composite material in a solvent-free solid-state fusible organic precursor, and heating at low temperature under a vacuum condition to melt the organic precursor and infiltrate into the C / C composite material to form an interface layer. The preparation method comprises the following steps: mixing a solid fusible organic precursor with silicide powder, heating to melt the organic precursor and wrap the silicide powder, embedding a C / C composite material containing an interface layer in the obtained precursor-silicide powder, and realizing synergistic infiltration under a vacuum high-temperature condition, so as to prepare the ceramic modified C / C composite material. The preparation method has the advantages that the period is short, the ceramic phase distribution is uniform, the infiltration agent reaction is complete, and the obtained composite material has the advantages of bearing, scouring resistance and ablation resistance.

A spin orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having a (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or a combination thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or a combination thereof, where M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

A method includes positioning a substrate within a processing chamber that comprises a feature formed within a dielectric layer formed over an underlayer, delivering an RF power to the processing chamber to generate a plasma over the substrate including: delivering a processing gas during a first time period, delivering a reactive gas into a flow of the processing gas during a second time period to form a pretreatment gas, delivering a deposition gas during a third time period, the deposition gas comprising a precursor gas and the pretreatment gas; and delivering a post-treatment gas during a fourth time period comprising halting the delivering of the precursor gas during the fourth time period, halting the delivering of the RF power and delivering the precursor gas into a flow of the post-treatment gas during a fifth time period, and purging the processing chamber during a sixth time period.

A semiconductor device includes a source / drain region, a source / drain silicide layer formed on the source / drain region, and a first contact disposed over the source / drain silicide layer. The first contact includes a first metal layer, an upper surface of the first metal layer is at least covered by a silicide layer, and the silicide layer includes a same metal element as the first metal layer.