891 results about "Silicide" patented technology

The invention provides a method for manufacturing a semiconductor device and a vertically stacked semiconductor device, which can be applied to the technical field of semiconductors. The manufacturing method includes: disposing a lower field effect transistor and an upper field effect transistor on a substrate, the lower field effect transistor and the upper field effect transistor being stacked in a vertical direction; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer; forming a full silicide layer on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer; patterning the full silicide layer to form an opening which exposes the lower surface of the lowermost gate stack in the lower field effect transistor, and forming silicide layer patterns which are arranged on the two sides of the opening in the first direction and are connected with the lower surface of a source / drain layer in the lower field effect transistor at the same time; filling a dielectric material in the opening so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; a contact hole is provided in contact with the silicification layer pattern.

A semiconductor device includes circuit cells having transistors. Each of the transistors includes nanostructures vertically stacked from each other in a Z-direction, a gate structure wrapping around the nanostructures and extending in a Y-direction, and source / drain features on opposite sides of the gate structure in an X-direction. The semiconductor device further includes silicide features over and in contact with the source / drain features. The silicide features extend lower than bottom surfaces of topmost nanostructures of the nanostructures. The semiconductor device further includes source / drain contacts over and in contact with the silicide features. Each of bottom surfaces of the source / drain contacts has a V-shape in an X-Z cross-sectional view.

The invention relates to a high-temperature-resistant light stealth coating material and a preparation method thereof, and belongs to the technical field of functional materials, the high-temperature-resistant light stealth coating material comprises the following raw materials: boride, silicide, a titanate fluxing agent, metal coated carbide, a zinc oxide coated nano carbon material and a sintering aid; according to the prepared high-temperature-resistant light stealth coating material, the infrared emissivity at the wavelength of 3-5 [mu] m is 0.231-0.245, the infrared emissivity at the wavelength of 8-14 [mu] m is 0.424-0.441, the tensile bonding strength is 40.8-46.4 MPa, and the thermal shock resistance frequency is 153-167.

A semiconductor device fabrication method is provided and includes executing front-end-of-line (FEOL) processing to form first and second source / drain (S / D) epitaxy, forming a middle-of-line (MOL) contact to the first S / D epitaxy, executing a self-aligned backside S / D cut to form an opening in which respective sides of each of the first and second S / D epitaxy are exposed, depositing metallic material along the respective sides of each of the first and second S / D epitaxy in the opening and forming silicide from the metallic material whereby the silicide at the first S / D epitaxy contacts the MOL contact and the sides of the first S / D epitaxy.

A method is provided for forming a light-shielding layer to block irradiation of light onto a light-sensitive storage region. The light-sensitive storage region is formed in a semiconductor substrate to store electric charges. A storage gate feature is formed over the light-sensitive storage region, and includes a polysilicon gate electrode that is disposed over the light-sensitive storage region. A metal layer is formed over the storage gate feature. A silicidation process is performed to transform a part of the metal layer that is in contact with the polysilicon gate electrode into a silicide light-shielding layer. A thermal process is performed to induce lateral growth of the silicide light-shielding layer to make the silicide light-shielding layer extend to cover a lateral surface of the storage gate feature. A process temperature of the thermal process is higher than that of the silicidation process.

An integrated circuit includes a transistor having a plurality of semiconductor nanostructures arranged in a stack and corresponding to channel regions of the transistor. The transistor includes a source / drain region in contact with the channel regions. The transistor includes a silicide that extends downward along a side of the source / drain region.

A semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer, a gate electrode, a silicide barrier, a source contact plug, a drain contact plug, and a field plate plug. The gate insulating layer, disposed between the drain region and the source region, includes a first gate insulating layer having a first thickness and a second gate insulating layer having a second thickness larger than the first thickness. A bottom surface of the first gate insulating layer and a bottom surface of the second gate insulating layer are parallel to each other. The gate electrode is disposed on the first and second gate insulating layers. The silicide barrier layer is disposed in contact with a top surface of the second gate insulating layer and a top surface of the gate electrode. The source contact plug is connected to the source region.

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer; a spacer structure disposed in the second dielectric layer; a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer, wherein the conductive structure is surrounded by the spacer structure; a liner layer separating the conductive structure from the first dielectric layer, the second dielectric layer, and the spacer structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer; an inner silicide portion disposed over the conductive structure; an outer silicide portion surrounding the inner silicide portion and covering the liner layer; and an upper plug disposed over the inner silicide portion and the outer silicide portion.

The invention relates to the technical field of brake discs, in particular to a carbon-ceramic brake disc with a composite functional layer and a preparation method of the carbon-ceramic brake disc. The problems that a brake disc is insufficient in strength and poor in ablation resistance are solved. The preparation method comprises the following steps: carrying out low-temperature plasma treatment and silicon dioxide sol impregnation on carbon fibers, and inserting a graphene oxide film between woven layers, so as to obtain a carbon fiber preform; primary densification is carried out through pretreatment activation, low-temperature permeation and high-temperature permeation, and two graphitization treatments are combined; siliconizing is carried out through low-pressure permeation, high-pressure strengthening and laser cladding, and secondary densification is carried out through precursor impregnation and cracking; the titanium zirconium silicide-nano aluminum oxide composite layer generated through the embedding process forms a compact oxidation film at high temperature, and the silicon carbide nano crystal whiskers are subjected to chemical vapor deposition, so that the strength and ablation resistance of the prepared carbon ceramic brake disc are improved.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the method comprises the steps: forming a first oxide layer on a substrate, the material of the first oxide layer being a silicon-rich oxide; performing nitrogen ion implantation and annealing process treatment on the first oxide layer to form a Si-N bond and an N-O bond in the first oxide layer, so that the relative dielectric constant of the first oxide layer is at least 4.2; a first nitride layer is formed on the first oxide layer, the first oxide layer and the first nitride layer form a silicide barrier layer, and the silicide barrier layer is located above a part of the gate structure of the substrate and on the substrate between the gate and the drain region; and forming a dielectric layer, which is higher than the first nitride layer, on the surface of the substrate, and forming a conductive structure at a preset position of the dielectric layer. According to the scheme of the invention, through a mode of improving the relative dielectric constant and the density of the first oxide layer, the damage of the first oxide layer is greatly reduced when the conductive structure is formed, and then the voltage endurance capability of the semiconductor device is improved.

The present invention is entitled "Method for Fabricating Memory Cells, High Voltage Devices and Logic Devices on a Substrate by Silicide on a Conductive Block". The present invention discloses a method for forming a semiconductor device, the method comprising: recessing the upper surface of a first region and a second region of a semiconductor substrate relative to a third region of the substrate; forming a pair of stacked structures in the first region, each stacked structure having a control gate above a floating gate; forming a first source region in the substrate between the pair of stacked structures; forming an erase gate above the first source region; forming a dummy material block in the third region; forming a select gate adjacent to the stacked structure; forming a high voltage gate in the second region; forming a first barrier layer above at least a portion of one of the high voltage gates; forming a silicide on the top surface of the high voltage gate that is not below the first barrier layer; and replacing the dummy material block with a metal material block.

The invention provides a silicon-carbon negative electrode material with a core-shell structure and a preparation method and application of the silicon-carbon negative electrode material. The preparation method comprises the following steps: sequentially preparing a sacrificial layer and a carbon coating layer for coating silicon particles on the surfaces of the silicon particles to form a carbon-coated silicon material; etching the carbon-coated silicon material by adopting an etching agent capable of etching the sacrificial layer, and removing the sacrificial layer in the carbon-coated silicon material to form a silicon-carbon material; dipping the silicon-carbon material in a metal precursor solution, taking out the silicon-carbon material, and drying the silicon-carbon material, wherein simple substances of metal elements in the metal precursor and / or silicides of the metal elements can catalyze the generation of the carbon nanotubes; heating the dried silicon-carbon material in a reducing gas atmosphere to form a catalyst on the surfaces of the silicon particles, the catalyst comprising simple substances of metal elements and / or silicides thereof; and depositing carbon nanotubes on the basis of the elementary substance of the metal element and / or the silicide thereof. The high-rate cycle performance of a battery prepared from the core-shell structure silicon-carbon negative electrode material is obviously improved.

The present invention provides a multi-layer doping source structure, and a high-quality emitter and a controllable preparation method therefor. The multi-layer doping source structure comprises a dielectric layer, a nitrogen silicide layer and a doping source layer, which are stacked on the front surface of a crystalline silicon substrate, wherein the dielectric layer is a silicon oxide film or a silicon oxynitride film, the doping source layer is boron-doped amorphous silicon doped with functional elements or phosphorus-doped amorphous silicon doped with functional elements, and the functional elements doped in the doping source layer are carbon and / or nitrogen. In the present invention, the doping source structure is composed of the dielectric layer, a nitrogen silicide and boron- / phosphorus-doped amorphous silicon doped with functional elements; the multi-layer doping source structure has both a strong laser absorption capability and a high boron or phosphorus doping concentration, thereby facilitating a reduction in the laser power and the illumination time required by a laser selective emitter technique; moreover, such a multi-layer doping source structure is favorable for reducing the surface boron concentration, decreasing defects and improving the passivation effect of an emitter, and therefore an improvement in battery efficiency can be promoted.

The invention discloses solar conductive silver paste and a preparation method and application thereof, and the preparation raw materials of the solar conductive silver paste comprise the following components in parts by weight: 65-92 parts of silver powder, 2-30 parts of silicide powder, 1-5 parts of glass powder and 4-15 parts of an organic carrier. By selecting the silicide powder and controlling the mass ratio of the silicide to the silver powder to be within the range, on one hand, the silver-silicon contact quality of a solar cell is improved, and the solar conductive silver paste capable of improving the photoelectric conversion efficiency is developed.

The invention relates to the field of batteries, in particular to an asphalt-based sodium ion electrode hard carbon negative electrode material and a preparation method thereof. The preparation method comprises the following steps: step 1, preparing hafnium silicide powder; step 2, preparing hafnium silicide amp; cobalt selenide composite microspheres; step 3, performing amp treatment on hafnium silicide; mixing the cobalt selenide composite microspheres, reduced graphene oxide and asphalt, and performing ball milling treatment to obtain an asphalt-based mixture; and 4, placing the asphalt-based mixture in a graphite furnace, introducing nitrogen as a protective gas, carrying out heating treatment, and cooling to obtain the hard carbon negative electrode material. According to the invention, hafnium silicide amp is used; the sodium ion electrode hard carbon negative electrode material is prepared by taking sodium selenide, cobalt selenide composite microspheres, reduced graphene oxide and asphalt as raw materials, and the negative electrode material not only has excellent performance in the aspects of specific capacity and coulombic efficiency, but also has the advantage of long cycle life.

Method to form low-contact-resistance contacts to source / drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source / drain feature and a surface of a p-type source / drain feature, selectively depositing a first silicide layer on the surface of the p-type source / drain feature while the surface of the n-type source / drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source / drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source / drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source / drain feature, and removing the self-assembly layer.

The invention provides an OPC (Optical Proximity Correction) method for regulating and controlling the resistance of a high-resistance sheet, which comprises the following steps of: 1, delimiting a layout area where a high-resistance layer and a silicide barrier layer are located in an original layout, and determining the resistance value of the high-resistance sheet according to the layout area; and 2, according to the resistance value of the sheet resistor of the high-resistance layer determined in the step 1, reducing the width of the overlapped part of the high-resistance layer and the silicide barrier layer. The resistance value of the high-resistance layer sheet resistor is regulated and controlled by changing the shape of the high-resistance layer in the layout, the position of a contact hole does not need to be adjusted, and more flexible layout design elasticity under different manufacturing processes is provided.

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and relates to the technical field of semiconductor structures. The preparation method of the semiconductor structure comprises the steps of forming a target to-be-etched layer and a first patterning layer, wherein the target to-be-etched layer comprises a first silicide layer, a first polycrystalline silicon layer and a second silicide layer which are stacked in sequence; etching the target layer to be etched to obtain a second patterned layer, the second patterned layer comprising a plurality of second patterns; side walls and second polycrystalline silicon layers are formed, the side walls cover the side walls of the second patterns, and gaps between the side walls are filled with the second polycrystalline silicon layers; removing the film layer structure above the first polycrystalline silicon layer and the side wall between the first polycrystalline silicon layer and the second polycrystalline silicon layer; and etching the substrate to obtain the semiconductor structure. The gap between the adjacent first polycrystalline silicon layer and second polycrystalline silicon layer can be controlled by controlling the formation parameters of the side wall, so that the line width of the semiconductor structure can be further reduced, and the device density of the semiconductor structure is improved.

A pellicle including a pellicle membrane with improved stability to hydrogen plasma is provided. The pellicle membrane includes a plurality of carbon nanotubes (CNTs), where at least one carbon nanotube (CNT) of the plurality of CNTs is coated by a protection coating. The protection coating includes a plurality of nanostructures that includes a transition metal or an oxide, nitride, silicide or carbide thereof on a surface of the at least one CNT of the plurality of CNTs, a carbon-based diffusion barrier layer over at least the plurality of nanostructures, and a capping layer over at least the carbon-based diffusion barrier layer. The pellicle further includes a pellicle border attached to the pellicle membrane along a peripheral region of the pellicle membrane and a pellicle frame attached to the pellicle border.

A microelectronic device including a substrate having a semiconductor material containing a laterally diffused metal oxide semiconductor (LDMOS) transistor, including a body region of a first conductivity type and a drift region of an opposite conductivity type. A gate dielectric layer over a channel region of the body, the gate dielectric extending over a junction between a body region and the drift region with a gate electrode on the gate dielectric and a drain contact in the drain drift region, having the second conductivity type. A field relief dielectric layer on the drain drift region extending from the drain region to the gate dielectric, having a thickness greater than the gate dielectric layer. A silicide-blocking layer extends from the drain region toward the gate, providing an unsilicided portion of the drift region at the substrate top surface between the drain region and the gate.

Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.

Methods of forming a molybdenum silicide layer on a surface of a substrate are disclosed. The method includes disposing a substrate within a reaction chamber, depositing a molybdenum metal layer on a surface of the substrate, and contacting the surface of the molybdenum metal layer with a silicon-containing gas, thereby converting at least a portion of the molybdenum metal layer to a molybdenum silicide layer.

The invention discloses a preparation method of an ultrahigh-temperature ceramic matrix modification and coating integrated carbon-based composite material, and belongs to the technical field of matrix modification and coating integrated carbon-based composite material preparation. Two functional materials are laid on the surface of low-density carbon / carbon (C / C) in a layered mode, infiltration powder on the inner layer is used for matrix modification, and coating powder on the outer layer is used for in-situ coating generation. And finally, applying pressure in a vacuum environment through an SPS process, so that the silicide alloy melt permeates into the C / C matrix under the assistance of the molten salt to generate carbide, and meanwhile, the outer-layer powder is converted into a compact ceramic coating in situ. The method is based on the SPS technology, and matrix modification and coating in-situ generation are synchronously achieved through a one-step method. According to the method, the thickness of the coating is controlled by regulating and controlling the quality of powder, and strong interface bonding of the coating and a modified matrix is achieved through melt permeation and interface mechanical occlusion.

The invention provides a semiconductor structure and a preparation method thereof. A through hole is formed in a glass substrate based on a through hole layout pattern; respectively forming a first metal layer and a second metal layer on the first surface and the second surface, and forming a connecting metal layer in the through hole; etching the first metal layer and the second metal layer at the same time to obtain a first patterned metal layer and a second patterned metal layer; forming a first dielectric layer on the first patterned metal layer; the first dielectric layer is made of silicide; performing etching processing on the first dielectric layer based on the through hole layout pattern, so that the connecting metal layer in the through hole is exposed in the first dielectric layer; and forming a connection structure above the connection metal layer to obtain a first semiconductor structure. The semiconductor structure can have a low thermal expansion coefficient, the semiconductor structure can be prevented from being damaged when the semiconductor structure is subjected to annealing and other processes with large temperature differences, stress changes on the surfaces of the two sides of the glass substrate can be more consistent, and the product yield of the semiconductor structure is increased.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source / drain regions disposed in a semiconductor substrate, where the source / drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source / drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source / drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

The invention belongs to the technical field of heat-engine plant unit circulation component surface corrosion prevention, and discloses a high-temperature-corrosion-resistant coating material, a coating and a preparation method and application thereof.The preparation method comprises the steps that by mass, 10%-20% of Cr, 1%-5% of Ni, 2%-10% of Fe, 10%-30% of molybdenum, 20%-40% of copper and 10%-20% of silicon are mixed to be uniform, a pipeline is embedded, heat treatment is conducted, and an initial chromium-rich infiltrated layer is formed; and then nitriding treatment is conducted on the initial chromium-rich nitriding layer, and the high-temperature-corrosion-resistant chromium-nitrogen composite coating is formed. The added silicon can form silicides in the coating, and the silicides can prevent the corrosion medium from permeating, so that the corrosion process is slowed down or prevented; the added molybdenum can effectively improve the stability of the composite coating in a corrosion medium rich in sulfate ions; and the added copper can form a protective layer consisting of copper sulfide or copper oxide on the surface of the steel, so that the corrosion of a corrosive medium is effectively prevented.

The embodiment of the invention discloses a metal oxide semiconductor transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a source region and a drain region in the substrate; forming a first dielectric structure exposing the drain region and the source region on the substrate, wherein the first dielectric structure comprises a gate dielectric layer located on the substrate and a first dielectric layer located on the gate dielectric layer; forming a gate conductor at a preset position of the gate dielectric layer, wherein the first dielectric layer at least exposes part of the upper surface of the gate conductor; forming a first field plate on the first dielectric layer; and after the first dielectric structure and the first field plate are formed, gate silicide, source silicide and drain silicide are respectively formed on the exposed gate conductor, the source region and the drain region. The first field plate is used as a partial etching barrier layer of the etching process for forming the opening for exposing the source region and the gate conductor, so that the process difficulty of forming the etching barrier layer is reduced.

The invention discloses high-entropy aluminum silicide ceramic as well as a preparation method and application thereof. The preparation method of the high-entropy aluminum silicide ceramic comprises the following steps: 1) fully and uniformly mixing transition metal powder, aluminum powder and silicon powder to prepare mixed powder; 2) pressing the mixed powder into a green body, and then performing electric field sintering, crushing and screening to obtain high-entropy aluminum silicide powder; and 3) pressing the high-entropy aluminum silicide powder into a green body, and carrying out spark plasma sintering to obtain the high-entropy aluminum silicide ceramic. The high-entropy aluminum silicide ceramic disclosed by the invention has excellent oxidation resistance and ablation resistance under an ultra-high-temperature condition, is suitable for being used as a hot end part protection material of a hypersonic aircraft, and is simple and convenient in preparation process, simple to operate, short in reaction time and suitable for large-scale industrial production and application.

A semiconductor device including a substrate having an insulating pattern, a channel pattern disposed on the insulating pattern a source / drain pattern disposed adjacent to the plurality of semiconductor patterns, a gate electrode disposed on the plurality of semiconductor patterns, a lower power line disposed in a lower portion of the substrate, a lower insulating pattern disposed between the source / drain pattern and the insulating pattern, a backside active contact disposed below the source / drain pattern, and a backside silicide pattern disposed between the source / drain pattern and the backside active contact. In one aspect, the backside active contact penetrates the substrate and the lower insulating pattern and is electrically connects the lower power line and the source / drain pattern. In one aspect, the backside active contact and the backside silicide pattern are vertically overlapped with the doping layer.

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate comprising a high-resistance region, and forming a high-resistance region groove in the high-resistance region; a first dielectric layer and a high-resistance component are sequentially formed in the high-resistance region groove, the first dielectric layer is formed at the bottom of the high-resistance region groove, the surface of the first dielectric layer is lower than the surface of the substrate, the high-resistance component is located on the first dielectric layer, and the top surface of the high-resistance component is higher than the surface of the substrate; forming a silicide barrier layer on the substrate and the high-resistance component, wherein the silicide barrier layer at least exposes part of the top surface of the high-resistance component; forming a silicide layer on the exposed high-resistance part; a high-resistance region connecting piece connected with the high-resistance structure is formed in the high-resistance region, the high-resistance structure comprises a first dielectric layer located in the high-resistance region groove, a high-resistance component and a silicide layer located on the high-resistance component, and the high-resistance region connecting piece is connected with the silicide layer on the high-resistance component. According to the invention, the technological process is optimized, the quality of the high-resistance region connecting piece is improved, and the contact resistance is reduced.