279 results about "Silicide" patented technology

The invention provides a micron-scale high-melting-point oxide sheet layer enhanced ultra-high-temperature ceramic-based anti-ablation composite coating and a preparation method thereof.The preparation method comprises the steps that ultra-high-temperature carbide / boride ceramic powder, silicide powder and high-melting-point metal oxide powder are mechanically mixed, and spraying mixed powder with uniform components is obtained; the mixed powder is sprayed on the surface of a base body in a plasma spraying mode, and the ultra-high-temperature ceramic-based anti-ablation composite coating containing a micron-scale oxide lamellar structure is obtained; the lamellar high-melting-point oxide phase is introduced into the ultrahigh-temperature ceramic-based composite silicide coating, so that the problem that the silicon-containing glass phase is easy to lose and splash under high-heat-flow scouring is effectively solved. The high-melting-point oxide sheet layer serves as a physical barrier, can effectively limit flowing of a silicon-containing glass liquid phase in the ablation process and allows gaseous oxidation products to escape at the same time, so that a firmly-attached composite oxide layer is formed, and the oxidation resistance and the anti-scouring and anti-stripping capacity of the coating are greatly improved.

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source / drain features on opposite sides of the dummy gate structures and over the first fin, forming second source / drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source / drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source / drain features, and forming second silicide features over the second source / drain features.

The method comprises the following steps: forming a source / drain region; forming a contact etch stop layer over the source / drain region; forming an interlayer dielectric over the contact etch stop layer; and performing an etching process to form contact openings in the interlayer dielectric and the contact etch stop layer. The source / drain region is exposed to the contact opening. A silicide formation process is performed to form a silicide region on a surface of the source / drain region. An etch process is performed to remove metal deposited on the dielectric region, where the dielectric region is exposed during the first silicide formation process. A contact plug is formed in the contact opening. The embodiment of the invention also relates to a method for forming the semiconductor device.

Disclosed are apparatuses including transistor and methods for fabricating the same. The transistor may include a drain substantially enclosed in a drain silicide layer, wherein an integral drain via portion of the drain silicide layer is coupled to a second drain contact and wherein a first drain via couples the drain silicide layer to a first drain contact. The transistor may include a source substantially enclosed in a source silicide layer, wherein an integral source via portion of the source silicide layer is coupled to a second source contact and wherein a first source via couples the source silicide layer to a first source contact. The transistor may include a gate disposed between the source and the drain.

Backside and frontside contact structures wrapping around source / drain regions provide increased contact areas for electrical connections and allow increased silicide areas. Sidewall metallization of epitaxially grown source / drain regions provides source / drain sidewall contacts that enable wrap-around contact formation on both the front side and the back side of a semiconductor device layer. Front side and back side contact metallization over the source / drain sidewall contacts allows wrap-around contact structures on both sides of the device layer.

The disclosure relates to improved design and fabrication of power devices. A device and a method of forming the same are described. A device includes a unit cell formed at least partially within a SiC substrate, the unit cell including: a trench defined in an upper surface of the SiC substrate; a silicide layer disposed on at least one surface of the trench; a first conductivity type drift region formed in the SiC substrate and having a first thickness; a first conductivity type source region formed within the SiC substrate and having a second thickness; the second thickness is smaller than the first thickness; the second conductive type well region is formed in the SiC substrate; wherein the device includes a vertical SiC DMOSFET including a drain terminal disposed on a backside of the SiC substrate and a source terminal disposed on a top surface of the SiC substrate and in a trench, such that a portion of the source terminal outside the trench is disposed over and conductively coupled to a non-trench surface of the source region; the source region is disposed adjacent to and between the trench and the well region.

A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source / drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source / drain contact electrically connected to, and on, the source / drain region, and a silicide layer between the source / drain region and the source / drain contact which contacts contact with the second doping layer and extends to an upper surface of the source / drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source / drain region along side walls of the silicide layer.

Method for manufacturing a semiconductor device comprising the following steps: Exposing a source / drain region (82) through a first dielectric layer (88) and a second dielectric layer (87), wherein the source / drain region (82) is at least partially arranged in a semiconductor fin (52); after exposing the source / drain region (82) through the first dielectric layer (88) and the second dielectric layer (87), implanting (122) dopants into the second dielectric layer (87), wherein, in the implantation (122) of the dopants into the second dielectric layer (87), the dopants are also implanted along side walls of the first dielectric layer (88); after implanting (122) the dopants, recessing (129) the second dielectric layer (87) beneath the first dielectric layer (88); and Forming a silicide region (133) on the source / drain region (82), wherein the silicide region (133) is arranged in a direction perpendicular to the semiconductor fin (52) after the formation of the silicide region (133) between the source / drain region (82) and the first dielectric layer (88).

The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor device and methods of manufacture. The structure includes: a gate structure including a gate dielectric material and a gate electrode with a stepped feature; sidewall spacers on sidewalls of the gate electrode, the sidewall spacers including a notched feature adjacent to the gate electrode; and a silicide contact on a surface of the gate electrode, the silicide contact being free of breaks on the surface of the gate electrode.

A method for forming a contact for a source-drain of a gate all around structure incorporates exposing at least a portion of a nanosheet during formation of the contact. A method may include removing a source-drain material to form an exposed portion of a nanosheet material of at least one nanosheet, forming epitaxial contact layers on the source-drain material and the exposed portion of the nanosheet material, forming a silicide contact layer on at least the epitaxial contact layers, and forming a contact with a metal material on the silicide contact layer. In some embodiments, an exposed portion of the nanosheet material comprises an entire end of at least one nanosheet alone or in conjunction with at least a portion of another nanosheet or in conjunction with an entire end of at least one other nanosheet.

The invention relates to a continuous high doping concentration in an epitaxial region. A method includes forming a plurality of semiconductor nanostructures. An upper semiconductor nanostructure of the plurality of semiconductor nanostructures overlaps a corresponding lower semiconductor nanostructure of the plurality of semiconductor nanostructures. The method further includes forming a source / drain recess alongside the plurality of semiconductor nanostructures, where the source / source recess has an intermediate vertical line. A first semiconductor layer is formed from a plurality of semiconductor nanostructures, where the first semiconductor layer includes dopants having a conductivity type, and the conductivity type is p-type or n-type. A second semiconductor layer is formed over the first semiconductor layer, where the second semiconductor has a vertical and elongated high dopant region aligned with an intermediate vertical line. A silicide region coupled with the second semiconductor layer is formed over the second semiconductor layer.

A spin orbit torque (SOT) magnetic tunnel junction (MTJ) device includes a substrate, a seed layer over the substrate, and a bismuth antimony (BiSb) layer having a (0120) orientation on the seed layer. The seed layer includes a silicide layer and a surface control layer. The silicide layer includes a material of NiSi, NiFeSi, NiFeTaSi, NiCuSi, CoSi, CoFeSi, CoFeTaSi, CoCuSi, or a combination thereof. The surface control layer includes a material of NiFe, NiFeTa, NiTa, NiW, NiFeW, NiCu, NiCuM, NiFeCu, CoTa, CoFeTa, NiCoTa, Co, CoM, CoNiM, CoNi, NiSi, CoSi, NiCoSi, Cu, CuAgM, CuM, or a combination thereof, where M is Fe, Cu, Co, Ta, Ag, Ni, Mn, Cr, V, Ti, or Si.

The application discloses a device and method for synthesizing and separating cerium silicide, and belongs to the technical field of crystal growth. The device for synthesizing and separating cerium silicide comprises a crucible main body, an inner cavity of the crucible main body being a circular truncated cone cavity with a cross-sectional size gradually decreasing from top to bottom, an ejection rod arranged at the bottom of the inner cavity of the crucible main body, and a base used for bearing the crucible main body and provided with a through hole through which the ejection rod passes, wherein the ejection rod is configured to be driven through the through hole to eject the solidified cerium silicide ingot in the inner cavity of the crucible main body in the axial direction. The application can realize lossless and efficient taking out of the synthesized product of cerium silicide by designing the crucible main body with the circular truncated cone cavity and integrating the ejection mechanism, and radial separation force is generated in the ejection process.

The present invention provides a heat exchanger capable of stably and continuously recovering heat over a long period of time, even when the target gas for heat recovery is an extremely corrosive gas, and an exhaust gas treatment device using such a heat exchanger. [Solution] The heat exchanger of the present invention is characterized by comprising a partition plate (14) made of refractory castable material that divides the inside of the casing (12) so that the low-temperature side fluid (LF) and the high-temperature side fluid (HF) flow in countercurrents, and a plurality of solid heat transfer rods (16) made of at least one ceramic selected from the group consisting of alumina, zirconia, silicon carbide, silicon nitride, molybdenum silicide, and lanthanum chromite, which are arranged to airtightly penetrate the front and back surfaces of the partition plate (14) and cross the flow paths of the low-temperature side fluid (LF) and the high-temperature side fluid (HF).

A method comprises the formation of multiple semiconductor nanostructures. Upper semiconductor nanostructures overlap lower semiconductor nanostructures. The method further comprises the formation of a source / drain cavity adjacent to the semiconductor nanostructures, the source / drain cavity having a central vertical line. A first semiconductor layer is formed from the semiconductor nanostructures, the first semiconductor layer having a dopant of a conductivity type, and the conductivity type being either p-type or n-type. A second semiconductor layer is formed above the first semiconductor layer, the second semiconductor layer having a vertically and elongated heavily doped region aligned with the central vertical line. A silicide region is formed above and electrically coupled to the second semiconductor layer.

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a substrate having a trench and a gate structure in the trench. The gate structure includes a lower gate electrode, an upper gate electrode disposed over the lower gate electrode, and a silicide layer contacting the upper gate electrode.

A three-dimensional memory device is provided. The three-dimensional memory device can include a substrate, a cell stack, a string select line gate electrode, a lower vertical channel structure, an upper vertical channel structure, and a bit line. The string select line gate electrode can include a lower string select line gate electrode and an upper string select line gate electrode formed on an upper surface of the lower string select line gate electrode. The lower string select line gate electrode can include N-doped polysilicon. The upper string select line gate electrode can include a silicide.

A photodiode and a manufacturing method thereof are provided. The photodiode comprises a first conductive type semiconductor layer, an intrinsic layer, a second conductive type semiconductor layer, and a silicide layer. The intrinsic layer is disposed on the first conductive type semiconductor layer and designed to generate a photocurrent in response to receiving a light of a specific wavelength. The second conductive type semiconductor layer is disposed on a central region of the intrinsic layer for exposing an outer peripheral region of the intrinsic layer surrounding the central region. The silicide layer is disposed at an edge of the outer peripheral region of the intrinsic layer to reduce a portion of the light that passes through the edge and enters the intrinsic layer for thereby preventing it from being absorbed by the intrinsic layer.

The invention relates to a manufacturing method of a trench Schottky diode with an adjustable forward voltage. A Schottky diode includes a substrate having an active region. The grooves extend into the substrate epitaxial layer, the side walls and the bottom surfaces of the grooves are lined with insulating layers, and the rest part of each groove is filled with polycrystalline silicon (polycrystalline silicon) filler. A doped region having a dopant of the same conductivity type as the semiconductor substrate is implanted in the epitaxial layer at a position between adjacent trenches. A silicide is provided at each polysilicon filler and a Schottky barrier is provided at each doped region. An anode contact of the diode contacts the silicide and the Schottky barrier, and a cathode contact of the diode contacts the lower surface of the substrate. The dopant concentration level of the selected doped region controls the setting of the forward voltage (VF) level of the Schottky diode.

The invention relates to the technical field of metal-based composite materials, in particular to a preparation method of a titanium-based composite material with a bimodal non-uniform net structure. The invention provides a preparation method of a titanium-based composite material with a bimodal non-uniform net structure, which comprises the following steps: mixing titanium alloy metal powder as a base material with nano titanium diboride, lanthanum hexaboride and a silicon powder reinforcement material through high-energy ball milling to obtain composite powder; a field-assisted sintering technology (FHP) is utilized, and a non-continuous reinforced titanium-based composite material (DRTiMCs) sintered blank is obtained; and carrying out heat preservation in a vacuum heat treatment furnace, and then carrying out a hot rolling experiment to obtain the DRTiMCs with the bimodal non-uniform network structure. The bimodal non-uniform net structure is composed of micron TiBw, nano TiBw, nano La2O3 and nano silicide, DRTiMCs of the bimodal non-uniform net structure have excellent strength and ductility, the tensile strength reaches 1544 MPa and 1560 MPa, and the percentage elongation after fracture is 7.7% and 10.2%. The DRTiMCs provide a good working idea for further development and engineering application of the composite material in the fields of aviation and aerospace.

A method for processing a substrate includes positioning a silicon substrate in a deposition chamber. One or more intermediate layers are deposited on a surface of the silicon. The one or more intermediate layers can include strontium, which combines with the silicon to form strontium silicide. Alternatively, the one or more intermediate layers comprise germanium. A layer of amorphous strontium titanate is deposited on the one or more intermediate layers in a transient environment in which oxygen pressure is reduced while temperature is increased. The substrate is then exposed to an oxidizing and annealing atmosphere that oxidizes the one or more intermediate layers and converts the layer of amorphous strontium titanate to crystalline strontium titanate.

The invention discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device in an FDSOI process, which is formed on a mixed region semiconductor substrate and comprises a channel region, a drift region and a gate structure, and the gate structure is formed on the top surface of the channel region and extends to the top surface of the adjacent drift region. The source region and the drain region are formed in the first lifting epitaxial layer and the second lifting epitaxial layer respectively, the second lifting epitaxial layer is formed on the top surface of the drift region, and a first spacer region is arranged between the second lifting epitaxial layer and the second side face of the gate structure. And a refractory silicide barrier layer is formed on the top surface of the drift region of the first spacer region. A high-resistance layer is further formed in the first spacer region, and the bottom surface of the high-resistance layer is in direct contact with the top surface of the refractory silicide barrier layer or an interlayer film is arranged between the bottom surface of the high-resistance layer and the top surface of the refractory silicide barrier layer in a spaced mode. The invention further discloses a manufacturing method of the LDMOS device in the FDSOI process. The on-state resistance of the device can be reduced, and meanwhile the breakdown voltage of the device is not reduced.

The invention relates to a thermal management-ablation resistance integrated ceramic matrix composite based on a shell silicide gradient structure and a preparation method thereof. According to the material, a carbon fiber preform is used as a reinforcing framework, and an interface layer is deposited on the surface; zrC-SiC ceramic is used as a matrix; zrSi2, MoSi2 and WSi2 high-melting-point silicides coated by the HfC shell layer are used as phase change heat absorption functional phases in gradient distribution, and when different silicides absorb instantaneous high heat flow step by step, the HfC shell layer can form an HfO2 high-melting-point anti-oxidation diffusion barrier after high-temperature oxidation to inhibit functional phase oxidation. According to the invention, a gradient structure of which the melting point of a functional phase is gradually increased along the thickness direction is realized through a gradient impregnation-curing-cracking combined reactive infiltration process, so that the problems of phase change medium volatilization, insufficient heat absorption capacity and interface mismatch failure of a traditional passive heat-proof structure at the temperature of 2000 DEG C or above are solved; and the service requirements of light weight, extreme thermal shock and long-time oxidation ablation resistance of high-speed aircrafts are met.

This invention provides a method, system, and nozzle for quantitative evaluation of the appearance of space engine nozzle coatings. The method includes: dividing the silicide coatings on the inner and outer surfaces of the nozzle into regions corresponding to different acceptance levels based on the operating temperature, thermal stress, and high-temperature gas erosion intensity of various parts of the nozzle; conducting full-area observation of the inner and outer wall coatings of the nozzle; identifying the regions where defects to be tested are located according to predefined zoning rules; comparing the observed defects with a pre-established standard defect map library to classify the defects; measuring the parameters of each defect based on the classified defects; comparing the measured defect parameters with the acceptance level corresponding to the region; and outputting a clear conclusion including whether the product is deliverable based on the comparison results. This invention provides an executable and quantifiable method for evaluating the appearance quality of coatings prepared by slurry sintering and embedding / infiltration methods.

The invention provides a method for improving electric leakage of an isolation region of a high-voltage device, which comprises the following steps of: 1, providing a substrate, dividing the substrate into a low-voltage device region, a medium-voltage device region and a high-voltage device region by an isolation region formed in the substrate, and forming a medium-voltage device oxide layer on the substrate; 2, removing a part of the medium-voltage device oxide layer, and only reserving the medium-voltage device oxide layer in a high-voltage device isolation region in the medium-voltage device region and the isolation region; 3, forming a high-voltage device grid side wall material layer on the substrate; 4, removing a part of the high-voltage device grid side wall material layer, and only reserving the high-voltage device grid side wall material layer in the high-voltage device grid groove and the high-voltage device isolation region; and step 5, forming a refractory silicide barrier layer in a designated area of the substrate, wherein the designated area does not contain a high-voltage device isolation area. Under the condition that the chip area is not increased and data is not modified, the isolation effect electric leakage level which is the same as that of removing the active area auxiliary layer is achieved, the method is compatible with an existing process, and no newly-added mask is needed.

A semiconductor structure having a high-temperature silicide contact for backside source / drain (S / D) contacts and method for making the same is disclosed. In an aspect, the semiconductor structure comprises a substrate; a source / drain (S / D) structure comprising a lower S / D portion disposed above the substrate and an upper S / D portion disposed above the lower S / D portion, the lower S / D portion comprising a high temperature silicide structure and an etch stop material structure surrounding at least a portion of the high temperature silicide structure, the upper S / D portion comprising an epitaxial (EPI) material in contact with the high temperature silicide structure; and a backside metal structure that extends through the substrate and is in contact with the high temperature silicide structure.

A temperature sensing system using a molybdenum di-silicide (MoSi2) sensing element. The MoSi2 sensing element can be positioned at a sensing location and the resistance of the sensing element can be detected and converted into temperature value representing the temperature at the sensing location. The sensing system can be used to provide temperature sensing in environments experiencing very high temperatures (e.g. greater than 1,200° C.) with low-cost sensing elements. The sensing system can also provide accurate temperature sensing across a large range of temperatures.

A semiconductor memory device includes: a plurality of first conductive layers arranged in a first direction and extending in a second direction intersecting with the first direction and a third direction intersecting with the first direction and the second direction; and a memory structure extending in the first direction, the memory structure including a first semiconductor layer opposed to the plurality of first conductive layers and a gate insulating layer disposed between the first semiconductor layer and the plurality of first conductive layers. The first semiconductor layer contains single-crystallized silicon and an impurity. The impurity contain: a first metallic element that is able to form silicide; and a second metallic element constituting a metal material having a linear expansion coefficient larger than a linear expansion coefficient of a silicon material.

The present disclosure relates to an electrical fuse having a fuse link along a sidewall of a non-active gate structure. An electronic fuse includes a non-active gate structure located over a substrate and a fuse link along at least one sidewall of the non-active gate structure. A first terminal is located at a first end of the fuse link and a second terminal is located at a second end of the fuse link. The fuse link takes the form of a conductive metal spacer along at least one sidewall of the non-active gate structure and can be formed without a silicide process. Although the e-fuse can be used with any semiconductor device, use with, for example, a III-V semiconductor device is advantageous. The method of manufacturing the e-fuse does not require any additional masks and provides a fuse link with sub-lithographic level width dimensions.

Semiconductor devices including a silicided substrate contact are described. In one example, a semiconductor device comprises a semiconductor substrate and a heterojunction structure over the semiconductor substrate, where the heterojunction structure includes a III-N buffer layer over the semiconductor substrate and a III-N barrier layer over the III-N buffer layer. A substrate contact extends through the heterojunction structure and to the semiconductor substrate, where the substrate contact includes a silicide layer contacting the semiconductor substrate.