268 results about "Bipolar junction transistor" patented technology

The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a pedestal dielectric layer, a collector layer, a base layer, and an emitter layer. The semiconductor substrate includes a bipolar junction transistor region. The pedestal dielectric layer is in the bipolar junction transistor region and is over an upper surface of the semiconductor substrate. The collector layer is on the upper surface of the semiconductor substrate and is through the pedestal dielectric layer. The base layer is on the collector layer and an upper surface of the pedestal dielectric layer. The pedestal dielectric layer extends laterally over the upper surface of the semiconductor substrate from the base layer. The emitter layer is on the base layer.

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

A semiconductor device includes a semiconductor body having opposing first and second surfaces along a vertical direction, and a bipolar junction transistor that includes an emitter region electrically connected to an emitter contact at the first surface, a base region electrically connected to a base contact at the first surface, and a collector region electrically connected to a collector contact. A dielectric isolation structure extends into the semiconductor body from the first surface and includes a first sub-structure arranged, along a first lateral direction, between the emitter contact and the base contact. A field plate structure including a field plate dielectric and a field plate electrode is arranged on the field plate dielectric. A first part of the field plate structure is arranged on the first surface of the semiconductor body. A second part of the field plate structure is arranged on the first sub-structure of the dielectric isolation structure.

Operating a double-sided double-base bipolar junction transistor. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly, into an upper collector-emitter of a double-sided double-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through a lower collector-emitter of the DSDB-BJT, and then through a lower terminal of the switch assembly; and then ceasing conduction of the forward load current. The ceasing conduction of the forward load current may be by: coupling a lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce reverse recovery current through the lower base.

A bipolar junction transistor has a collector over a substrate and a base structure over the collector, the base including a III-V ternary semiconductor alloy, the base having a base contact formed thereon. An emitter is over the base structure, and a ledge between the emitter structure and the base contact is 0.3 μm or less.

The invention relates to the technical field of oscillators, and discloses a low-noise broadband voltage-controlled oscillator based on a cross coupling differential structure, which comprises a resonant cavity, a differential negative resistance circuit and a current bias circuit, and is characterized in that the resonant cavity adopts an LC resonant structure and is used for determining frequency selection and phase characteristics of the low-noise broadband voltage-controlled oscillator; the differential negative resistance circuit adopts a cross coupling differential pair structure formed by two bipolar junction transistors and is used for providing enough gain and positive feedback so as to generate a negative resistance effect; the current bias circuit uses a bipolar junction transistor to construct a bias circuit structure and is used for providing stable bias current and ensuring that the bipolar junction transistor in the differential negative resistance circuit works in an amplification region.

The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.

The invention provides a capacitor capacitance value on-line monitoring method, device and system and an auxiliary discharge network, and the method comprises the steps: when a power converter is in an on-line operation state, collecting the voltage of a DC power supply for many times and recording a time point at a stage that a bipolar junction transistor is disconnected and a resistor is put into operation; determining the capacitance values of the first aluminum electrolytic capacitor and the second aluminum electrolytic capacitor according to the starting time point when the bipolar junction transistor is disconnected and the resistor is put into operation, the total output current of the first aluminum electrolytic capacitor and the second aluminum electrolytic capacitor, the resistance value of the resistor, the direct-current power supply voltage and the time point; the first and second capacitor branches are connected in parallel with the direct-current power supply; the first capacitor branch comprises a resistor and a first aluminum electrolytic capacitor which are connected in series; the second capacitance branch comprises a second aluminum electrolytic capacitor; the bipolar junction transistor is connected in parallel with the resistor. The capacitance value of the capacitor can be monitored on line, and the reliability of capacitor state monitoring is improved.

A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path and a second path, the first path including a first resistor, and the second path including a second resistor and a first bipolar junction transistor connected in series; and a switch controller that generates a switch control signal for controlling switches included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switch level voltage has a slope with respect to temperature that is greater than a base-emitter voltage of the first bipolar junction transistor.

A hybrid switch circuit for coupling two circuit terminals together is disclosed. The hybrid switch circuit includes a set of bidirectional switch devices coupled between a first circuit terminal and a second circuit terminal. The hybrid switch circuit also includes a set of unidirectional switch devices that are also coupled between the first circuit terminal and the second circuit terminal. In some cases, the set of bidirectional switch devices may be implemented using bidirectional double-base bipolar junction transistors, while the set of unidirectional switch devices may be implemented using wide bandgap transistors. In response to a de-assertion of a switch signal, a control circuit may open the set of bidirectional switch devices and, after a period of time has elapsed, open the set of unidirectional switch devices.

A display comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the control circuitry of the silicon-based backplane comprises at least one driving transistor where a first terminal of the driving transistor is electrically connected to an external power source VDD, and the second terminal of the driving transistor is electrically connected to the bottom electrode of the OLED stack; wherein the gate of the driving transistor is controlled by a data signal which supplied by a scan transistor controlled by a signal from select line SELECT1; and the control circuitry additionally comprises a protection circuit comprising a bipolar junction transistor. There can be a switch transistor between the scan transistor and the gate of the driving transistor for microdisplay applications. The OLED stack can comprise two or more OLED light-emitting units.

A bipolar junction transistor a base over a collector, the base including a III-V ternary semiconductor alloy including first, second, and third elements. The LI-V ternary semiconductor alloy has a narrower bandgap than a binary semiconductor alloy including only the first and second elements. A ledge between an emitter and a base contact being 0.5 μm or less.

A bipolar junction transistor has a collector over a substrate and a multi-layer base structure over the collector, and an emitter over the base structure. The multi-layer base structure includes a first layer having a first III-V semiconductor alloy and a second layer having a second III-V semiconductor alloy having a different composition of elements than the first III-V semiconductor alloy. The second layer has a narrower bandgap than the first layer. The first layer is positioned between the collector and the second layer.

A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path including a first resistor and a second path including a second resistor; the second path comprises a second resistor and a first bipolar junction transistor which are connected in series; and a switch controller that generates a switch control signal for controlling a switch included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switching level voltage has a slope with respect to temperature greater than a slope with respect to temperature of a base-emitter voltage of the first bipolar junction transistor.

A bipolar junction transistor has a collector over a substrate, a base over the collector, and an emitter over the base. The base includes a III-V ternary semiconductor alloy including first, second, and third elements, and having a narrower bandgap than a binary semiconductor alloy including only the first and second elements. At least a portion of the base has a differential concentration of the third element such that a concentration of the third element at a first location in the base is greater than at a second location in the base, the second location between the first location and the collector.

The present invention provides a reference voltage generation circuit (30) and an automotive-grade chip. The reference voltage generation circuit (30) includes a biasing and voltage-limiting circuit (34), a PTAT current generation circuit (31), a zero-temperature coefficient reference voltage generation circuit (32), and a start-up circuit (33). The PTAT current generation circuit (31) includes a first P-channel MOS transistor (MP1), a second P-channel MOS transistor (MP2), a first N-channel MOS transistor (MN1), a second N-channel MOS transistor (MN2), and a first resistor (R1). An output end of the start-up circuit (33) is connected to a drain of the first N-channel MOS transistor (MN1). The biasing and voltage-limiting circuit (34) is connected to the drain of the first N-channel MOS transistor (MN1) to limit an operating voltage of the first N-channel MOS transistor (MN1). The zero-temperature coefficient reference voltage generation circuit (32) includes a second resistor (R2) and a bipolar junction transistor (B1). A PTAT current generated by the PTAT current generation circuit (31) flows through the second resistor (R2) to generate a PTAT voltage, and the PTAT voltage is superposed with a negative temperature coefficient voltage between a base electrode and an emitter electrode of the bipolar junction transistor (B1) to generate a zero-temperature coefficient reference voltage.

A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the light emitting OLED stack has three or more OLED units between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane comprises at least two transistors with their channels connected in series between an external power source VDD, and the bottom electrode of the OLED stack. The light-emitting OLED stack preferably has a Vth of at least 7.5V or more. The control circuit can include a protection circuit comprised of a p-n diode, preferably a bipolar junction transistor.

Embodiments of a power amplification device are disclosed. The power amplification device includes a power amplification circuit configured to amplify a radio frequency (RF) input signal and generate an amplified RF output signal. The power amplification device also includes a bias circuit. The bias circuit is provided in a closed loop configuration that has a bipolar junction transistor (BJT) that generates the bias voltage applied to the RF input signal. The BJT is provided in a common emitter configuration. This allows for the bias voltage generated by the bias circuit to be generated with a power voltage having a lower voltage level.

Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.

The invention provides a band-gap reference circuit and a compensation circuit, and is applied to the technical field of band-gap reference circuits, a high-order curvature compensation branch and / or a current compensation branch are / is adopted to compensate the band-gap reference circuit, the high-order curvature compensation branch is used for generating a corresponding first compensation amount, and the current compensation branch is used for generating a second compensation amount. The current compensation branch is used for generating a corresponding second compensation amount, and the first compensation amount is superposed on a base-emitter voltage of a bipolar junction transistor in the band-gap reference circuit according to a preset first proportion; the second compensation amount is superposed on a base-emitter voltage of a bipolar junction transistor in the band-gap reference circuit according to a preset second proportion, so that the high-order term component of a band-gap reference voltage temperature coefficient is eliminated by using the first compensation amount; and eliminating the base-emitter voltage change of the bipolar junction transistor caused by the stress influence of the band-gap reference circuit by using the second compensation amount. After compensation, the stability and accuracy of the reference can be kept, and the high-precision requirement is met.

A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path and a second path, the first path including a first resistor, and the second path including a second resistor and a first bipolar junction transistor connected in series; and a switch controller that generates a switch control signal for controlling switches included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switch level voltage has a slope with respect to temperature that is greater than a base-emitter voltage of the first bipolar junction transistor.

Embodiments provide bipolar junction transistors (BJTs) which are formed from GAA or FinFET transistors and methods of forming the BJTs. The BJTs include dielectric isolation structures formed between gates of the GAA or FinFET transistors. The dielectric isolation structures reduce spacing between transistors of neighboring terminals of the BJTs. The dielectric isolation structures allow the BJTs to use the nominal gate spacing (Lg) as logic device, thereby, compatible with the GAA or FinFET processes.

The present invention discloses an input-output circuit and an electrostatic discharge protection circuit. The electrostatic discharge protection circuit is suitable for a component charging model. The electrostatic discharge protection circuit includes a bipolar junction transistor. The bipolar junction transistor has a first end coupled to an input end of an input buffer and an output end of an output buffer. The second end of the bipolar junction transistor is coupled to a first ground rail. The control end of the bipolar junction transistor is coupled to one of a first power rail, a second power rail, a first ground rail, and a second ground rail.

Various techniques to eliminate the error caused by variable β coupled with a series resistance in BJTs are described. Multiple known currents are applied to a terminal of the BJT and a corresponding VBE is generated. A resistor R is coupled in series with a base or emitter of the BJT and an analog-to-digital converter (ADC) is used to measure the voltage across the resistor R for each of the known currents. These voltages are used to determine ratios of β change, which are then used to determine a temperature of the BJT.

An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.

The present disclosure relates to a lateral bipolar junction transistor device and a method of manufacturing such a device. A non-uniform base width bipolar junction transistor (BJT) device includes a semiconductor substrate having an upper surface, and a BJT device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

The invention discloses an electrostatic discharge protection device, which comprises a clamping bipolar junction transistor and at least one electrostatic discharge circuit, and the electrostatic discharge circuit is coupled between a first voltage rail and a second voltage rail. The electrostatic discharge circuit comprises a silicon controlled rectifier and a diode. An anode and a cathode of the silicon controlled rectifier are respectively coupled to an input / output (I / O) port and a first voltage rail. The cathode of the diode is coupled to the anode of the silicon controlled rectifier and the I / O port. An anode of the diode is coupled to the second voltage rail. The absolute value of the reverse breakdown voltage of the diode is larger than the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier, and the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier is larger than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

A bandgap voltage reference circuit comprises a current mirror circuit, a first sub-circuit and an output circuit. The current mirror circuit is coupled between an input source and a ground, is configured to generate a first current, and comprises first and second bipolar junction transistors (BJTs) and a first resistor. The two BJTs' bases are coupled together. The first resistor is coupled between the first BJT's emitter and the ground. The first sub-circuit comprises a transistor coupled to the first BJT's base and collector, comprises a second resistor coupled between the transistor and the ground, and is configured to generate a second current based on the second resistor and a base-emitter potential difference of the second BJT. The output circuit is coupled between the input source and the ground, and is configured to generate an output reference voltage based on the first, second currents and a third resistor.