166 results about "Bipolar junction transistor" patented technology

The invention relates to a folded cascode low noise amplifier. The disclosed low noise amplifiers (LNAs) include a common emitter amplifier (CE-A), a common gate amplifier (CG-A), and various passive devices located in CE-A and CG-A. The CE-A includes an NPN type bipolar junction transistor (BJT) having emitter and collector (E / C) regions, and a base region located between the E / C regions and connected to an input node. The CG-A includes a P-channel field effect transistor (PFET) having source and drain (S / D) regions, a channel region between the S / D regions, and a gate adjacent to the channel region. A drain region of the PFET is connected to the output node. Further, the common inductor, the collector region of the BJT, and the source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) in which the BJT and the FET are located on different chips and the passive device is located in a back-end-of-line region between the BJT and the FET.

A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E / C) regions and a base region between the E / C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S / D) regions, a channel region between the S / D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.

Operating a double-sided double-base bipolar junction transistor. At least one example is a method of operating a switch assembly, the method comprising: conducting a forward load current from an upper terminal of the switch assembly, into an upper collector-emitter of a double-sided double-base bipolar junction transistor (DSDB-BJT), through the DSDB-BJT, out through a lower collector-emitter of the DSDB-BJT, and then through a lower terminal of the switch assembly; and then ceasing conduction of the forward load current. The ceasing conduction of the forward load current may be by: coupling a lower base of the DSDB-BJT to the lower terminal; and driving a pinch-off voltage to the lower collector-emitter of the DSDB-BJT to reduce reverse recovery current through the lower base.

The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.

Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a bipolar junction transistor including a base, a first terminal having a first raised semiconductor layer over the base, and a second terminal having a second raised semiconductor layer over the base. The first raised semiconductor layer is spaced in a lateral direction from the second raised semiconductor layer. The structure further comprises a resistive memory element including a first electrode, a second electrode, and a switching layer between the first electrode and the second electrode. The first electrode of the resistive memory element is coupled to the first terminal of the bipolar junction transistor.

A semiconductor device including a bandgap reference generator that generates a reference voltage; a switch control voltage generator that generates a first reference current based on the reference voltage, and generates an adaptive switch level voltage by distributing the first reference current to a first path and a second path, the first path including a first resistor, and the second path including a second resistor and a first bipolar junction transistor connected in series; and a switch controller that generates a switch control signal for controlling switches included in the bandgap reference generator based on the adaptive switch level voltage. The adaptive switch level voltage has a slope with respect to temperature that is greater than a base-emitter voltage of the first bipolar junction transistor.

Various techniques to eliminate the error caused by variable β coupled with a series resistance in BJTs are described. Multiple known currents are applied to a terminal of the BJT and a corresponding VBE is generated. A resistor R is coupled in series with a base or emitter of the BJT and an analog-to-digital converter (ADC) is used to measure the voltage across the resistor R for each of the known currents. These voltages are used to determine ratios of β change, which are then used to determine a temperature of the BJT.

The present disclosure relates to a lateral bipolar junction transistor device and a method of manufacturing such a device. A non-uniform base width bipolar junction transistor (BJT) device includes a semiconductor substrate having an upper surface, and a BJT device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

The invention discloses an electrostatic discharge protection device, which comprises a clamping bipolar junction transistor and at least one electrostatic discharge circuit, and the electrostatic discharge circuit is coupled between a first voltage rail and a second voltage rail. The electrostatic discharge circuit comprises a silicon controlled rectifier and a diode. An anode and a cathode of the silicon controlled rectifier are respectively coupled to an input / output (I / O) port and a first voltage rail. The cathode of the diode is coupled to the anode of the silicon controlled rectifier and the I / O port. An anode of the diode is coupled to the second voltage rail. The absolute value of the reverse breakdown voltage of the diode is larger than the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier, and the absolute value of the trigger voltage from the anode to the cathode of the silicon controlled rectifier is larger than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

A bandgap voltage reference circuit comprises a current mirror circuit, a first sub-circuit and an output circuit. The current mirror circuit is coupled between an input source and a ground, is configured to generate a first current, and comprises first and second bipolar junction transistors (BJTs) and a first resistor. The two BJTs' bases are coupled together. The first resistor is coupled between the first BJT's emitter and the ground. The first sub-circuit comprises a transistor coupled to the first BJT's base and collector, comprises a second resistor coupled between the transistor and the ground, and is configured to generate a second current based on the second resistor and a base-emitter potential difference of the second BJT. The output circuit is coupled between the input source and the ground, and is configured to generate an output reference voltage based on the first, second currents and a third resistor.

Integrated circuit devices including a bipolar junction transistor (BJT) and / or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

This invention provides a simulation method for a DC output characteristic model of a van der Waals bipolar junction transistor (VJT), relating to the field of semiconductor device technology. The method includes: acquiring a target VJT and experimentally measuring its output characteristic curve; constructing a DC output characteristic model of the target VJT based on the output characteristic curve and obtaining initial parameters for the DC output characteristic model; iteratively optimizing the initial parameters using existing mathematical software to obtain optimized parameters; constructing a simulation module based on the DC output characteristic model and setting simulation parameters based on the optimized parameters; and performing simulation calculations using the simulation module to obtain simulation data and simulation curves for the target VJT, thus completing the simulation. This invention enables rapid judgment of the characteristics of a target VJT by constructing a simulation module for the target VJT and performing simulation calculations using the simulation module to obtain simulation data and simulation curves.

A temperature sensor system includes two P-type bipolar junction transistors (BJTs) configured as diodes and current sources operating the diodes at different current densities. The system includes a voltage reference, a multiplexer, a voltage ramp generating circuit, a comparator, an XOR circuit, a counter, and a second logic circuit (math unit). The sensor system measures temperatures by comparing the various voltages with the ramp voltage. The counter is enabled by performing an XOR function on a Start signal and the counter output or by performing an XOR function on outputs of multiple counters.

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

A multilayer semiconductor device includes: a substrate comprising silicon carbide (SiC); and an epitaxial transition layer on the substrate, the epitaxial transition layer comprising a first epitaxial oxide material or SiC. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed over the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT).

An electrostatic discharge protection device includes a clamping bipolar junction transistor and at least one electrostatic discharge circuit coupled between a first-voltage rail and a second-voltage rail. The electrostatic discharge circuit includes a silicon-controlled rectifier and a diode. The anode and the cathode of the silicon-controlled rectifier are respectively coupled to an I / O port and the first-voltage rail. The cathode of the diode is coupled to the anode of the silicon-controlled rectifier and the I / O port. The anode of the diode is coupled to the second-voltage rail. The absolute value of the reverse breakdown voltage of the diode is greater than the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier, which is greater than the absolute value of the trigger voltage of the clamping bipolar junction transistor.

A double-sided, double-base, bipolar junction transistor is operated. One example is a method of operating a switch assembly, the method comprising: blocking, by a transistor, a current flow from an upper terminal to a lower terminal of the switch assembly; and then conducting a first load current from the upper terminal to the lower terminal in response to assertion of a conduction signal. The conducting the first load current may be by closing an upper main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current from an upper current source to an upper base of the transistor; and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first turn-on current.

A bipolar junction transistor includes an emitter region, a base region, a collector region and a plurality of fin structures. The emitter region is disposed on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are disposed in the base region and surround the emitter region, and the plurality of fin structures fixedly extend along a direction and parallel to each other.

An electrostatic discharge protection circuit is coupled between a first voltage terminal and a second voltage terminal and includes first and second bipolar junction transistors. First ends of the first and second bipolar junction transistors are coupled to the first and second voltage terminals, respectively. Second ends of the first and second bipolar junction transistors are coupled to each other. Control terminals of the first and second bipolar junction transistors are coupled to each other. A breakdown voltage of a junction between the first end and the control terminal of the first bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the first bipolar junction transistor. A breakdown voltage of a junction between the first end and the control terminal of the second bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the second bipolar junction transistor.

Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including first and second trench isolation regions positioned in the semiconductor substrate. The first trench isolation region extends to a first depth in the semiconductor substrate, and the second trench isolation region extends to a second depth in the semiconductor substrate. The second depth is greater than the first depth. A bipolar junction transistor structure includes a collector, an emitter, and a base each disposed in the semiconductor substrate. The collector includes a portion that extends to the top surface of the semiconductor substrate, the first trench isolation region is positioned in the base, the second trench isolation region is positioned in a lateral direction between the portion of the collector and the base, and the second trench isolation region surrounds the base, the emitter, and the first trench isolation region.

The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.

Disclosed in the present invention are a method for integrating a CMOS device in a double-polysilicon self-aligned bipolar junction transistor process and a structure. The method comprises: successively forming an N-type primary buried layer (103) of a double-polysilicon self-aligned bipolar junction transistor, a P-type primary buried layer (104) of an NMOS, and an N-type secondary buried layer (105) of a PMOS; forming an epitaxial layer (106) on an SOI silicon substrate; forming in the epitaxial layer (106) a P-type well region (107) of the NMOS and an N-type well region (108) of the PMOS; and steps such as forming all-dielectric island isolation of the double-polysilicon self-aligned bipolar junction transistor and the NMOS / PMOS. The semiconductor device of the present invention can achieve various combinations of high-performance NPN / PNP and CMOS devices, and effectively improve the overall device characteristics of the process, so as to meet wider and higher-demanding application technical fields and improve the electrical performance of chips.

The present disclosure generally relates to an insulated gate bipolar junction transistor (IGBJT). In an example, a semiconductor device includes a semiconductor substrate, a first well in the semiconductor substrate, a second well in the semiconductor substrate, a gate electrode over the semiconductor substrate, a source region in the second well, a collector region in the second well, an emitter region in the first well, a drain region in the first well, and a silicide on the source region and the collector region. The first well, source region, and drain region are doped with a first conductivity type. The second well, collector region, and emitter region are doped with a second conductivity type opposite from the first conductivity type. The gate electrode extends laterally over the first well and the second well. The gate electrode is laterally between the source region and the emitter region.

The invention relates to a device model verification method and device, equipment, a storage medium and a program product. A circuit netlist is created, the circuit netlist is used for verifying a bipolar junction transistor (BJT) device model, and the circuit netlist comprises a current source identifier corresponding to a current source, a voltage source identifier corresponding to a voltage source, a transistor identifier corresponding to a transistor and a connection relation; simulation is carried out based on the circuit netlist and model parameters of a to-be-verified BJT device model, simulation results are obtained, and the simulation results comprise target voltages obtained through simulation at different target temperatures; and verifying the BJT device model based on the change condition of the target voltage at the different target temperatures. The simple circuit netlist created by the method has universality, and model verification efficiency can be improved while BJT device model verification is realized, so that modeling efficiency is improved.

The present disclosure provides a current generation circuit and a current detection circuit, which can provide first and second reference currents with different temperature characteristics by using a reference unit in the current generation circuit, and adaptively adjust the steady-state operating point of the circuit itself under the control of first and second bias voltages according to the first and second reference currents, and access an input current and the first bias voltage through an input branch in a mirror output unit thereof, and access the second bias voltage through an output branch and provide an output current, wherein the conversion ratio of the output current to the input current provided by the mirror output unit is mirror-set as the ratio of the first reference current to the second reference current. Thus, the current proportional relationship is constructed by using the current mirror circuit structure including bipolar junction transistors, so as to realize the conversion of the temperature characteristics of the current to the current, so as to be suitable for the circuit application in which the current conversion voltage cannot be realized in practical application.

A biosensor device is provided. The biosensor includes an amplifying bipolar junction transistor (BJT) and a sensing BJT defining a sensing trench. The sensing BJT and the amplifying BJT are coupled to form a Sziklai pair with an emitter of the sensing BJT connected to a collector of the amplifying BJT and a collector of the sensing BJT connected to a base of the amplifying BJT.

Embodiments of a power switching system are disclosed. In some embodiments, the system includes: a power transistor having a control terminal, a first transistor terminal, and a second transistor terminal; a current buffer that includes a bipolar junction transistor connected across the control terminal and the first transistor terminal, the bipolar junction transistor having a base; a gate driver circuit having a first circuit branch connected to the base of the bipolar junction transistor and a second circuit branch connected to the base of the bipolar junction transistor, wherein: the first circuit branch includes a first switch for opening and closing the first circuit branch; the second circuit branch includes a second switch for opening and closing the second circuit branch and a current source. In some embodiments, the power transistor is a Silicon Carbide field effect transistor or a Gallium Nitride field effect transistor.

A dynamic vision sensor (DVS) including a plurality of substrates electrically connected to one another and stacked vertically includes a photoelectric conversion device configured to generate charges in response to incident light from an external environment that is external to the DVS sensor, a bipolar junction transistor (BJT) device including a base connected to the photoelectric conversion device and configured to output a current based on amplifying a current output from the photoelectric conversion device, and a DVS pixel circuit that detects a change in intensity of the incident light and to output an event signal based on the current. The photoelectric conversion device is on a first substrate among the plurality of substrates. At least part of the DVS pixel circuit is on a different substrate from the first substrate among the plurality of substrates.

A switch circuit for coupling two circuit terminals together is disclosed. The switch circuit includes a double-base bipolar junction transistor and a field-effect transistor coupled, in series, between a first terminal and a second terminal. Various driver circuits may be employed to activate, in response to an activation of a switch signal, the field-effect transistor, and couple one or both of the base terminals of the double-base bipolar junction transistor to voltage sources to initiate base currents to reduce the channel resistance of the double-base bipolar junction transistor.