96 results about "Bipolar junction transistor" patented technology

Various techniques to eliminate the error caused by variable β coupled with a series resistance in BJTs are described. Multiple known currents are applied to a terminal of the BJT and a corresponding VBE is generated. A resistor R is coupled in series with a base or emitter of the BJT and an analog-to-digital converter (ADC) is used to measure the voltage across the resistor R for each of the known currents. These voltages are used to determine ratios of β change, which are then used to determine a temperature of the BJT.

The present disclosure relates to a lateral bipolar junction transistor device and a method of manufacturing such a device. A non-uniform base width bipolar junction transistor (BJT) device includes a semiconductor substrate having an upper surface, and a BJT device including a collector region, a base region, and an emitter region located in the semiconductor substrate, the base region located between the collector region and the emitter region; the base region including a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

A bandgap voltage reference circuit comprises a current mirror circuit, a first sub-circuit and an output circuit. The current mirror circuit is coupled between an input source and a ground, is configured to generate a first current, and comprises first and second bipolar junction transistors (BJTs) and a first resistor. The two BJTs' bases are coupled together. The first resistor is coupled between the first BJT's emitter and the ground. The first sub-circuit comprises a transistor coupled to the first BJT's base and collector, comprises a second resistor coupled between the transistor and the ground, and is configured to generate a second current based on the second resistor and a base-emitter potential difference of the second BJT. The output circuit is coupled between the input source and the ground, and is configured to generate an output reference voltage based on the first, second currents and a third resistor.

This invention provides a simulation method for a DC output characteristic model of a van der Waals bipolar junction transistor (VJT), relating to the field of semiconductor device technology. The method includes: acquiring a target VJT and experimentally measuring its output characteristic curve; constructing a DC output characteristic model of the target VJT based on the output characteristic curve and obtaining initial parameters for the DC output characteristic model; iteratively optimizing the initial parameters using existing mathematical software to obtain optimized parameters; constructing a simulation module based on the DC output characteristic model and setting simulation parameters based on the optimized parameters; and performing simulation calculations using the simulation module to obtain simulation data and simulation curves for the target VJT, thus completing the simulation. This invention enables rapid judgment of the characteristics of a target VJT by constructing a simulation module for the target VJT and performing simulation calculations using the simulation module to obtain simulation data and simulation curves.

A temperature sensor system includes two P-type bipolar junction transistors (BJTs) configured as diodes and current sources operating the diodes at different current densities. The system includes a voltage reference, a multiplexer, a voltage ramp generating circuit, a comparator, an XOR circuit, a counter, and a second logic circuit (math unit). The sensor system measures temperatures by comparing the various voltages with the ramp voltage. The counter is enabled by performing an XOR function on a Start signal and the counter output or by performing an XOR function on outputs of multiple counters.

The invention discloses a method and a structure for integrating a double-gate JFET (junction field effect transistor) device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming a buried layer structure, an epitaxial layer and an isolation structure of the bipolar junction transistor and the JFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, etching to form a base region window, and forming a heavily doped collector region, a heavily doped outer base region, a heavily doped bottom gate, a heavily doped top gate, a source region and a drain region through the base region window; s500, forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes of the bipolar junction transistor and the JFET device on the dielectric layer. According to the invention, the high-speed bipolar junction transistor and the JFET device can be integrated in a single manufacturing process under the condition that a large amount of process complexity is not increased.

A multilayer semiconductor device includes: a substrate comprising silicon carbide (SiC); and an epitaxial transition layer on the substrate, the epitaxial transition layer comprising a first epitaxial oxide material or SiC. One or more epitaxial active regions comprising one or more second epitaxial oxide materials are formed on the epitaxial transition layer, and a metal layer is formed over the one or more epitaxial active regions, the metal layer comprising one or more electrical contacts. The multilayer semiconductor device includes one of the following: a metal-oxide-semiconductor field-effect transistor (MOSFET), a vertically conductive MOSFET, a lateral MOSFET, a metal-semiconductor field-effect transistor (MSFET), a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-insulator-semiconductor (MIS) device, a PN device, a PNP device, an NPN device, or an insulated-gate bipolar transistor (IGBT).

A double-sided, double-base, bipolar junction transistor is operated. One example is a method of operating a switch assembly, the method comprising: blocking, by a transistor, a current flow from an upper terminal to a lower terminal of the switch assembly; and then conducting a first load current from the upper terminal to the lower terminal in response to assertion of a conduction signal. The conducting the first load current may be by closing an upper main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current from an upper current source to an upper base of the transistor; and then providing a first steady-state current from the upper current source to the upper base, the first steady-state current being lower than the first turn-on current.

A bipolar junction transistor includes an emitter region, a base region, a collector region and a plurality of fin structures. The emitter region is disposed on a substrate. The base region surrounds the emitter region. The collector region surrounds the base region. The plurality of fin structures are disposed in the base region and surround the emitter region, and the plurality of fin structures fixedly extend along a direction and parallel to each other.

An electrostatic discharge protection circuit is coupled between a first voltage terminal and a second voltage terminal and includes first and second bipolar junction transistors. First ends of the first and second bipolar junction transistors are coupled to the first and second voltage terminals, respectively. Second ends of the first and second bipolar junction transistors are coupled to each other. Control terminals of the first and second bipolar junction transistors are coupled to each other. A breakdown voltage of a junction between the first end and the control terminal of the first bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the first bipolar junction transistor. A breakdown voltage of a junction between the first end and the control terminal of the second bipolar junction transistor is greater than a breakdown voltage of a junction between the second end and the control terminal of the second bipolar junction transistor.

Disclosed in the present invention are a method for integrating a CMOS device in a double-polysilicon self-aligned bipolar junction transistor process and a structure. The method comprises: successively forming an N-type primary buried layer (103) of a double-polysilicon self-aligned bipolar junction transistor, a P-type primary buried layer (104) of an NMOS, and an N-type secondary buried layer (105) of a PMOS; forming an epitaxial layer (106) on an SOI silicon substrate; forming in the epitaxial layer (106) a P-type well region (107) of the NMOS and an N-type well region (108) of the PMOS; and steps such as forming all-dielectric island isolation of the double-polysilicon self-aligned bipolar junction transistor and the NMOS / PMOS. The semiconductor device of the present invention can achieve various combinations of high-performance NPN / PNP and CMOS devices, and effectively improve the overall device characteristics of the process, so as to meet wider and higher-demanding application technical fields and improve the electrical performance of chips.

The present disclosure generally relates to an insulated gate bipolar junction transistor (IGBJT). In an example, a semiconductor device includes a semiconductor substrate, a first well in the semiconductor substrate, a second well in the semiconductor substrate, a gate electrode over the semiconductor substrate, a source region in the second well, a collector region in the second well, an emitter region in the first well, a drain region in the first well, and a silicide on the source region and the collector region. The first well, source region, and drain region are doped with a first conductivity type. The second well, collector region, and emitter region are doped with a second conductivity type opposite from the first conductivity type. The gate electrode extends laterally over the first well and the second well. The gate electrode is laterally between the source region and the emitter region.

The invention relates to a device model verification method and device, equipment, a storage medium and a program product. A circuit netlist is created, the circuit netlist is used for verifying a bipolar junction transistor (BJT) device model, and the circuit netlist comprises a current source identifier corresponding to a current source, a voltage source identifier corresponding to a voltage source, a transistor identifier corresponding to a transistor and a connection relation; simulation is carried out based on the circuit netlist and model parameters of a to-be-verified BJT device model, simulation results are obtained, and the simulation results comprise target voltages obtained through simulation at different target temperatures; and verifying the BJT device model based on the change condition of the target voltage at the different target temperatures. The simple circuit netlist created by the method has universality, and model verification efficiency can be improved while BJT device model verification is realized, so that modeling efficiency is improved.

The present disclosure provides a current generation circuit and a current detection circuit, which can provide first and second reference currents with different temperature characteristics by using a reference unit in the current generation circuit, and adaptively adjust the steady-state operating point of the circuit itself under the control of first and second bias voltages according to the first and second reference currents, and access an input current and the first bias voltage through an input branch in a mirror output unit thereof, and access the second bias voltage through an output branch and provide an output current, wherein the conversion ratio of the output current to the input current provided by the mirror output unit is mirror-set as the ratio of the first reference current to the second reference current. Thus, the current proportional relationship is constructed by using the current mirror circuit structure including bipolar junction transistors, so as to realize the conversion of the temperature characteristics of the current to the current, so as to be suitable for the circuit application in which the current conversion voltage cannot be realized in practical application.

A biosensor device is provided. The biosensor includes an amplifying bipolar junction transistor (BJT) and a sensing BJT defining a sensing trench. The sensing BJT and the amplifying BJT are coupled to form a Sziklai pair with an emitter of the sensing BJT connected to a collector of the amplifying BJT and a collector of the sensing BJT connected to a base of the amplifying BJT.

Embodiments of a power switching system are disclosed. In some embodiments, the system includes: a power transistor having a control terminal, a first transistor terminal, and a second transistor terminal; a current buffer that includes a bipolar junction transistor connected across the control terminal and the first transistor terminal, the bipolar junction transistor having a base; a gate driver circuit having a first circuit branch connected to the base of the bipolar junction transistor and a second circuit branch connected to the base of the bipolar junction transistor, wherein: the first circuit branch includes a first switch for opening and closing the first circuit branch; the second circuit branch includes a second switch for opening and closing the second circuit branch and a current source. In some embodiments, the power transistor is a Silicon Carbide field effect transistor or a Gallium Nitride field effect transistor.

A semiconductor device includes a base including a base contact, an emitter including an emitter contact, a well region below the base and the emitter, an extrinsic base between the base and the well region, and a collector located below the well region and on a backside of the semiconductor device. The base contact and the emitter contact are connected to a frontside of the semiconductor device.

Various techniques to eliminate the error caused by variable β coupled with a series resistance in BJTs are described. Multiple known currents are applied to a terminal of the BJT and a corresponding VBE is generated. A resistor R is coupled in series with a base or emitter of the BJT and an analog-to-digital converter (ADC) is used to measure the voltage across the resistor R for each of the known currents. These voltages are used to determine ratios of β change, which are then used to determine a temperature of the BJT.

The invention discloses a method and a structure for integrating a PJFET device and an NJFET device in a bipolar junction transistor process, and the method comprises the steps: providing a substrate, and forming buried layer structures, isolation structures and epitaxial layers of a bipolar junction transistor, the PJFET device and the NJFET device on the substrate; carrying out penetration doping and well region doping in the epitaxial layer; forming a collector crystalline region, a base crystalline region, a bottom gate crystalline region, a top gate crystalline region, a source crystalline layer and a drain crystalline region of the PJFET device and the NJFET device above the epitaxial layer; depositing a dielectric layer on the epitaxial layer, and etching to form a base region window; forming a heavily-doped collector region, a heavily-doped outer base region, and heavily-doped bottom gates, heavily-doped top gates, source regions and drain regions of the PJFET device and the NJFET device through injection and annealing of a base region window; forming an emitter region window, and forming an emitter crystalline region in the emitter region window; and forming electrodes on the dielectric layer. According to the invention, the bipolar junction transistor, the PJFET device and the NJFET device are simultaneously integrated in a single manufacturing process.

The present disclosure generally relates to semiconductor processing for forming an emitter layer in a bipolar junction transistor (BIT). In an example, a BIT includes a collector (102), a base (104) on the collector (102), and an emitter layer (106) on the base (104). The emitter layer (106) includes a first emitter sub-layer (108) and a second emitter sub-layer (110) over the first emitter sub-layer (108). The first emitter sub-layer (108) includes boron (122) and carbon (124). A concentration of carbon (124) is uniform throughout the first emitter sub-layer (108). The second emitter sub-layer (110) includes boron (122). A concentration of boron (122) in the second emitter sub-layer (110) is greater than a concentration of boron (122) in the first emitter sub-layer (108).

The application provides a capacitor capacity online monitoring method, device, system and auxiliary discharge network. The method comprises the following steps: when a power converter is in an online running state, collecting a direct current power supply voltage multiple times and recording time points in a stage of bipolar junction transistor disconnection and resistor running; determining capacities of first and second aluminum electrolytic capacitors according to a starting time point of the stage of bipolar junction transistor disconnection and resistor running, a total output current of the first and second aluminum electrolytic capacitors, a resistor value of the resistor, the direct current power supply voltage and the time points; the first and second capacitor branches are connected in parallel with the direct current power supply; the first capacitor branch comprises the resistor and the first aluminum electrolytic capacitor connected in series; the second capacitor branch comprises the second aluminum electrolytic capacitor; and the bipolar junction transistor is connected in parallel with the resistor. The application can realize online monitoring of the capacities of the capacitors and improve the reliability of capacitor state monitoring.

The invention provides a silicon carbide BJT (Bipolar Junction Transistor) device structure and a preparation method, and relates to the technical field of semiconductor device preparation, and the preparation method comprises the following steps: forming a terminal structure with a doping type opposite to that of an epitaxial layer in the epitaxial layer on a substrate; generating a base region on the upper surface of the epitaxial layer; generating an emitter region on the upper surface of the base region; respectively generating base region lead metal on the base region and the emitter region; generating emitter region lead metal on the base region lead metal; a protective layer is formed on the upper surface of the device through chemical vapor deposition and photoetching technologies, and collector region metal is formed on the back face of the device through a back face metallization technology. Based on a photoetching stripping technology and a silicon carbide epitaxial growth technology, the base region and the emitter region of the BJT device can be directly formed by using a photoetching stripping and epitaxial growth method when being manufactured, so that the interface state problem caused by plasma etching and ion implantation processes is avoided, the internal interface state of the BJT device can be effectively improved, and the reliability of the BJT device is improved. And the device amplification performance beta is improved.

Provided is field-effect transistor structure including: a substrate including therein at least one 1st doped region, a 2nd doped region on one side of the 1st doped region, and a 3rd doped region on another side of the 1st doped region; a 1st channel structure including therein a 4th doped region on the 2nd doped region in the substrate; and a 2nd channel structure, at a side of the 1st channel structure, including therein a 5th doped region on the 3rd doped region in the substrate, wherein the 4th, 2nd, 1st, 3rd and 5th doped regions form a sequentially connected passive device.

Pixel This description concerns a logarithmic response pixel having a photosensitive element (D1) connected to at least one bipolar junction transistor configured as a diode. Figure for the abbreviation: Fig. 2

A bandgap reference voltage generation circuit includes two bipolar junction transistors biased at different current densities to generate a base-emitter voltage difference, and to determine a negative temperature coefficient current. The circuit further includes a delta-voltage sensing resistor and a feedback circuit to ensure that the voltage drop across the delta-voltage sensing resistor includes the voltage difference, thereby generating a positive temperature coefficient current. The positive and negative temperature coefficient currents are combined to bias an output resistor, generating an output current with low-order temperature compensation. A multi-stage compensation circuit further generates a compensation current, which is injected into a tap of the output resistor to form a bandgap reference voltage with high-order temperature compensation. The compensation current varies with temperature and exhibits at least three stages of temperature coefficient.

Disclosed in the present invention are a method and structure for integrating thick- and thin-gate-oxide CMOS devices in a dual-poly self-aligned bipolar junction transistor process. The method comprises: providing an SOI silicon substrate; sequentially forming an N-type first buried layer (103) of a dual-poly self-aligned bipolar junction transistor, a P-type first buried layer (104) of a thin-gate-oxide NMOS, and a P-type second buried layer (105) of a thick-gate-oxide NMOS; forming an epitaxial layer (106) on the SOI silicon substrate; and forming a P-type first well region (107) of the thin-gate-oxide NMOS and a P-type second well region (108) of the thick-gate-oxide NMOS in the epitaxial layer. The semiconductor device in the present invention enables various combinations of high-performance NPN / PNP and thick- and thin-gate-oxide CMOS devices, thereby effectively improving the overall device characteristics of the process, meeting higher demands for broader application fields, and improving the electrical performance of chips.

A hybrid switch circuit for coupling two circuit terminals together is disclosed. The hybrid switch circuit includes a set of bidirectional switch devices coupled between a first circuit terminal and a second circuit terminal. The hybrid switch circuit also includes a set of unidirectional switch devices that are also coupled between the first circuit terminal and the second circuit terminal. In some cases, the set of bidirectional switch devices may be implemented using bidirectional double-base bipolar junction transistors, while the set of unidirectional switch devices may be implemented using wide bandgap transistors. In response to a de-assertion of a switch signal, a control circuit may open the set of bidirectional switch devices and, after a period of time has elapsed, open the set of unidirectional switch devices.

Bias circuits are provided for biasing an amplifier transistor in load-modulated amplifiers such as a class C amplifier. In a first bias circuit, a current source drives a reference current into a first node coupled to a second node through a first resistor. The first node couples to a collector of a first bipolar junction transistor and to a base of a second bipolar junction transistor. The second node coupled to a base of a third bipolar junction transistor.

Operating a double-sided double-base bipolar junction transistor. One example is a method of operating a switch assembly, the method comprising: blocking current flow from an upper terminal of the switch assembly to a lower terminal by a transistor; and then responsive to assertion of a conduction signal, conducting a first load current from the upper terminal to a lower terminal. The conducting the first load current may be by: closing an upper-main FET coupled between the upper terminal and an upper collector-emitter of the transistor; closing a lower-main FET coupled between a lower collector-emitter of the transistor and the lower terminal; driving a first turn-on current to an upper base of the transistor from an upper current source; and then providing a first steady-state current to the upper base from the upper current source, the first steady-state current lower than the first turn-on current.

A manufacturing method for a super-β bipolar junction transistor includes providing a substrate, and forming a first conductive type isolation buried layer and a first conductive type doped layer based on the substrate. The isolation buried layer is located at a bottom of the doped layer. The method also includes forming a second conductive type base region in the doped layer and forming a second conductive type doped island on a peripheral side of the base region. A doping concentration of the doped island is greater than that of the base region. Additionally, the method includes forming a first conductive type collector region in the doped layer, and the collector region is spaced from the base region. Further, the method includes forming a first conductive type emitter region in the base region.