55805 results about "Audio power amplifier" patented technology

An adapter allows the interconnection of a sensor originating from one manufacturer to be coupled with conventionally incompatible monitors originating from other manufacturers to form a properly functioning pulse oximetry system. The adapter matches a sensor driver in a monitor to the current requirements and light source configuration of a sensor. The adapter also matches a sensor's light detector signal level to the dynamic range requirements of a monitor preamplifier. Further, the adapter provides compatible sensor calibration, sensor type and security information to a monitor. The adapter may have a self-contained power source or it may derive power from the monitor, allowing both passive and active adapter components. The adapter is particular suited as an adapter cable, replacing a conventional patient cable or sensor cable as the interconnection between a sensor to a monitor in a pulse oximetry system.

A method of producing a diode drive current in an oximeter includes sensing at least a part of a current passing through the diode and converting the sensed current to a sensed voltage, inputting the sensed voltage to a feedback amplifier for stabilizing the current passing through the diode, and eliminating an offset voltage across inputs of the feedback amplifier. A pulse oximeter includes a diode for emitting light flashes, a feedback amplifier having inputs, a feedback capacitor, and an output, the feedback amplifier stabilizing a current passing through the diode, a nulling amplifier having inputs, a nulling capacitor, and an output, the nulling amplifier charging and discharging the feedback capacitor until the inputs of the feedback amplifier are at a same voltage. The operation may include synchronizing an elimination of input offset voltages of the feedback and nulling amplifiers with on or off state of diode current.

A patient module comprising an 8 channel EEG pre-amplifier whose signal acquisition and processing characteristics are optimized for use in the operating room and intensive care unit. This patient module comprises at least an optimized multistage input filter, an optimized input stage circuit topography, ultra-isolation, oversampling, a multiplexer inter-sample charge dump, and high performance low-frequency-enhanced shielding.

A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits such as a processor for processing data among stacks each associated with multiple memory cells are factored out. The processor is implemented with an input logic, a latch and an output logic. The input logic can transform the data received from either the sense amplifier or the data latches. The output logic further processes the transformed data to send to either the sense amplifier or the data latches or to a controller. This provides an infrastructure with maximum versatility and a minimum of components for sophisticated processing of the data sensed and the data to be input or output.

Controls for an optical scanner, such as a single fiber scanning endoscope (SFSE) that includes a resonating optical fiber and a single photodetector to produce large field of view, high-resolution images. A nonlinear control scheme with feedback linearization is employed in one type of control to accurately produce a desired scan. Open loop and closed loops controllers are applied to the nonlinear optical scanner of the SFSE. A closed loop control (no model) uses either phase locked loop and PID controllers, or a dual-phase lock-in amplifier and two PIDs for each axis controlled. Other forms of the control that employ a model use a frequency space tracking control, an error space tracking control, feedback linearizing controls, an adaptive control, and a sliding mode control.

In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.

A DRAM-like non-volatile memory array includes a cell array of non-volatile cell units with a DRAM-like cross-coupled latch-type sense amplifier. Each non-volatile cell unit has two non-volatile cell devices with respective bit lines and source lines running in parallel and laid out perpendicular to the word line associated with the non-volatile cell unit. The two non-volatile cell devices are programmed with erased and programmed threshold voltages as a pair for storing a single bit of binary data. The two bit lines of each non-volatile cell unit are coupled through a Y-decoder and a latch device to the two respective inputs of the latch-type sense amplifier which provides a large sensing margin for the cell array to operate properly even with a narrowed threshold voltage gap. Each non-volatile cell device may be a 2 T FLOTOX-based EEPROM cell, a 2 T flash cell, 11 T flash cell or a 1.5 T split-gate flash cell.

A sense amplifier of a memory array may be provided to amplify data presented from storage cells of the memory array. Additionally, a sense amplifier latch may be provided to store data received from the sense amplifier. The sense amplifier may be enabled for operation by a sense amplifier enable signal that is distinct from a clock signal. Moreover, the latch enable signal of the sense amplifier latch may be controlled by the sense amplifier enable signal, such that the sense amplifier latch opens in response to activation of the sense amplifier and closes in response to deactivation of the sense amplifier.

Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

A content addressable memory (CAM) device and process for searching a CAM. The CAM device includes a plurality of CAM cells, match-lines (MLs), search lines, and ML sense amplifiers. The ML sense amplifiers are capable of self-calibration to their respective thresholds to reduce effects of random device variation between adjacent sense amplifiers.

A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal. The delay reduction unit is disposed between the input signal applying unit and the ground switch, and reduces a signal delay from when the clock signal to when the evaluation signal pair is output from the second output terminal pair.

One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by when the reference sense amplifier sensing a reference current detects an expected state. In another aspect, an integration period for an amplified output is determined by when the reference sense amplifier outputs an expected state. When these determined timings are used to control the one or more sense amplifiers, environment and systemic variations are tracked.