2017 results about "Interconnection" patented technology

The invention discloses a construction method and device of a power terminal interconnection communication model, a medium and a program product. The method comprises the following steps: acquiring terminal operation data of a plurality of power terminals in a power system, determining operation characteristic data in the terminal operation data, and classifying the terminal operation data according to the operation characteristic data to obtain a plurality of initial data sets; determining a plurality of target data sets according to the data similarity among the power terminal data in the plurality of initial data sets, and determining a target incidence matrix corresponding to the plurality of target data sets, determining the importance degree of the data category corresponding to the target data set in the communication network of the power system according to the target incidence matrix; and a data communication model is constructed according to the importance degree of the data category in the communication network of the power system, so that the operation efficiency, the stability and the response speed of the power system are improved, and the reliability and the intelligent level of the whole communication network are enhanced.

The invention provides a flexible electronic device multi-physics field coupling performance simulation analysis method, and relates to the technical field of flexible electronics. Firstly, a geometric model of the flexible electronic device is constructed; the geometric model comprises a three-layer assembly structure of an electronic chip, an adhesive layer and a flexible PCB layer, and an interconnection structure; setting electromagnetic-thermal-mechanical field coupling parameters of the geometric model; then, grid division is conducted on the geometric model through a finite element method, and the grid division precision of the area where the interconnection structure is located is higher than that of other areas; building a multi-physics field coupling model according to the geometric model and set coupling parameters; applying load and boundary conditions to the model, wherein the load and boundary conditions comprise a current source, a heat generation load, a convection heat dissipation boundary condition and a mechanical constraint condition; and simulating the working state of the flexible electronic device under the action of multi-physics field coupling in the multi-physics field coupling model to obtain a simulation result. According to the method, the performance and the failure mechanism of the flexible electronic device under the multi-physics field coupling effect can be effectively predicted.

The invention discloses a consistency interconnection processing device, a data transmission method, equipment and a heterogeneous system, and relates to the technical field of data transmission, the consistency interconnection processing device installed on the equipment is utilized, the consistency interconnection processing device comprises a consistency interconnection port and a consistency interconnection controller, the consistency interconnection controller controls the consistency interconnection interface to establish a consistency interconnection communication link between the devices and distribute a cache space from the devices where the consistency interconnection interface is located, so that consistency interconnection between the devices is achieved; the consistency interconnection controller monitors the cache line state of the device where the consistency interconnection controller is located and the cache line states of other devices and records the global cache line state table, when the consistency interconnection transaction request is executed, the global cache line state table is inquired according to the target data information and then the target access position is determined, actual memory access detection does not need to be carried out, and the memory access efficiency is improved. Therefore, the number of times of executing the consistency access is reduced, the consistency maintenance overhead of the consistency interconnection between the devices is reduced, and the memory access performance of the consistency interconnection between the devices is improved.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention discloses an SOC interconnection system, a method for the SOC interconnection system, electronic equipment and a storage medium. The SOC interconnection system includes: a plurality of computing devices configured as a plurality of computing device groups; wherein the plurality of computing device groups are groups of the plurality of computing devices based on mutual access frequencies among the plurality of computing devices, each computing device group in the plurality of computing device groups is provided with a corresponding routing device, and each computing device in each computing device group is coupled with the corresponding routing device. The plurality of routing devices corresponding to the plurality of computing device groups are mutually coupled. According to the SOC interconnection system, the wiring congestion risk can be reduced, and the realization of the physical architecture of the SOC is facilitated.

The invention discloses a chip design method, system and device based on a multi-core heterogeneous architecture and a medium. The method comprises the steps that the type and number of heterogeneous computing cores are determined according to a target application scene, and a task scheduling unit is configured; designing an on-chip interconnection structure of a heterogeneous computing core by adopting a hybrid topological structure, and verifying and adjusting a dynamic task scheduling strategy and the on-chip interconnection structure through hardware simulation; configuring a power management unit according to the energy efficiency optimization target, wherein the power management unit is used for controlling the working state of the heterogeneous computing core; operating data of the heterogeneous computing core are collected in the post-silicon verification stage, a firmware updating scheme is generated according to the operating data, and firmware updating is conducted according to the firmware updating scheme. By optimizing the chip design process under the multi-core heterogeneous architecture, the performance, the energy efficiency ratio and the reliability of the chip are improved, and the method can be widely applied to the technical field of chip design.

The invention relates to a multi-protocol communication conversion module and a communication method of an intelligent safety fence, and belongs to the technical field of communication protocols. The multi-protocol communication conversion module comprises the following steps: step 1, performing protocol type identification on various protocol heterogeneous devices in the intelligent safety fence; step 2, constructing a data analysis rule base of the protocol according to the identified protocol type; 3, analyzing the data according to a data analysis rule base of the protocol, and converting the analyzed data into a uniform data format so as to facilitate data interaction among the heterogeneous devices; 4, performing protocol packaging on the data converted into the uniform format according to a protocol type supported by the target protocol heterogeneous equipment and a pre-constructed protocol mapping table; step 5, sending the packaged data to the target protocol heterogeneous device, and realizing interconnection and intercommunication among the protocol heterogeneous devices in the intelligent safety guardrail; the method has the beneficial effects that the analyzed data is converted into a uniform data format, and interconnection among protocol heterogeneous devices is realized.

The invention relates to the technical field of data compression, in particular to an intelligent data compression method and system based on multi-protocol heterogeneous equipment interconnection. The method comprises the following steps: when it is detected that a new heterogeneous device applies to join a network, carrying out communication protocol real-time analysis and protocol conversion adaptation to obtain a heterogeneous device adaptation protocol; carrying out multi-device data stream receiving according to a heterogeneous device adaptation protocol, and generating data streams of a plurality of time windows; adaptive coding and multi-level compression are carried out on the data streams of the multiple time windows, and a multi-device adaptive compression mechanism is constructed; identifying compression load characteristics of each heterogeneous device, and performing dynamic task allocation to obtain an intelligent task allocation strategy; and driving real-time data intelligent compression operation based on an intelligent task allocation strategy and a multi-device adaptive compression mechanism. According to the invention, efficient and adaptive data compression of different devices is realized, and the data transmission efficiency and quality are improved.

The invention relates to the technical field of semiconductors, and discloses a glass-based three-dimensional interconnection structure and a packaging framework based on the glass-based three-dimensional interconnection structure, the glass-based three-dimensional interconnection structure comprises a glass plate core, two opposite sides of the glass plate core are respectively a first surface and a second surface; the front rewiring layer is arranged on the first surface; the back rewiring layer is arranged on the second surface; the glass through hole penetrates through the glass plate core, and a base metal interconnection layer is filled in the glass through hole; the base metal interconnection layer extends to the first surface and is electrically connected with the front rewiring layer; and the base metal interconnection layer extends to the second surface and is electrically connected with the back rewiring layer. According to the technical scheme provided by the invention, the technical effects of vertical integration capability, thermal management efficiency, electromagnetic performance and the like can be remarkably improved in a high-frequency and high-integration scene.

The invention discloses a structure and a manufacturing method of a circuit board with interconnection of any layers of through holes, two ends of an isolation strip which needs to be insulated between layers at the through holes of the circuit board are respectively provided with a concave etching position, the concave etching positions serve as isolation rings, and the concave etching positions are formed after an isolation disc arranged on an inner-layer core plate is etched in a concave mode; the manufacturing method comprises the following steps that a circuit board is provided, a drilling position is arranged on the circuit board, and the drilling position is a position needing to be drilled in subsequent processing; the two ends of the interlayer isolation strip needing insulation at the drilling position of the circuit board are each provided with an isolation disc with the outer diameter larger than the outer diameter of the drilling position. A through hole is drilled in the position, corresponding to the drilling position, of the circuit board, so that the isolation disc on the inner layer is exposed in the through hole, then the isolation disc in the hole is removed through concave etching, and a concave etching position serving as an isolation ring is formed; and after the circuit board is subjected to copper deposition and electroplating, a structure of interconnection of any layers of the through holes is formed. According to the method, a plurality of signals can be transmitted in the same hole, and the purpose of interconnection of any layer in the through hole can be achieved.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention provides a multimode communication network dynamic scheduling system fused with AI computing power, which belongs to the technical field of communication equipment and artificial intelligence hardware fusion, and is characterized in that based on a four-layer hardware architecture of'core control-computing power support-multimode communication-high-speed interconnection ', an interconnection layer is constructed by adopting high-speed interfaces such as PCIe / SGMII + and the like, and inter-module fault is realized; 10ms low-delay data transmission is realized; the AI computing power module integrated with the 8TOPS NPU is deeply coupled with the multi-mode communication module, and the AI computing power module is quantized and compressed through an LSTM / Transform model and then solidified to an NPU special storage to realize scene self-adaptive scheduling; a'acquisition-identification-decision-feedback 'hardware closed loop is established, the communication interruption rate is reduced in an emergency scene, the overall power consumption is reduced, and AI reasoning is delayed. Through breakthrough hardware architecture design, AI computing power and a multi-mode communication module are deeply integrated, an intelligent communication resource scheduling system is constructed, and dynamic optimal configuration of communication resources in multiple scenes can be realized.

The invention discloses a network-on-chip construction method and device, a medium and a product, and relates to the technical field of network-on-chip design, and the method comprises the steps: building a bottom layer cellular network based on a cellular topological structure, each node in the bottom layer network comprises a router and a processing unit, and carries out the data interaction with an adjacent node; the method comprises the following steps of: symmetrically dividing a network into a plurality of geometric sectors with the same coverage angle by taking a center node of a bottom-layer network as an original point, and selecting at least one node from each sector as a cross-layer node; and connecting the cross-layer nodes to corresponding nodes in the top-layer switched network through additional channels, wherein the top-layer network nodes only comprise routers and realize full interconnection through the additional channels. According to the invention, the long-distance communication is transferred to the top switching network through a hierarchical structure, the data transmission hop count and signal delay are effectively reduced, the hardware resource consumption is reduced, and the network expansibility and the communication efficiency are improved.

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

The invention discloses an industrial equipment interconnection and intercommunication method based on an industrial control platform, and relates to the technical field of industrial equipment interconnection and intercommunication, and the method specifically comprises the following steps: calculating a behavior entanglement degree between a resending data frame with repeated content and a resending data frame, and if the entanglement degree exceeds a preset threshold value, determining that the resending data frame is the resending data frame; if yes, extracting a sequence offset, a time delay amount and a field fluctuation amplitude, and generating an index vector used for describing the aging degree of the data identifier; the generated index vector is input into a pre-trained graph embedding algorithm model, a first parameter and a second parameter are generated, the first parameter is used for describing the consistency of the data frame and a historical evolution path, and the second parameter is used for describing the aging degree of the data frame identifier. According to the method, the problem that the reissued data of the industrial equipment cannot be accurately identified is solved, and timeliness judgment and validity identification of the state data are realized based on the causal atlas and the graph embedding model.

The embodiment of the invention discloses a GPU BOX, a server, an interconnection system and a high-speed interconnection and data interaction method. The GPU BOX high-speed interconnection method is characterized in that the GPU BOX comprises a GPU and a control mainboard, an internal PCIe switch, an internal storage device, a first DMA controller and a system controller are integrated in the control mainboard, and a second DMA controller is integrated in the GPU; the system controller receives the reading instruction and performs data read-write initialization on the first DMA controller and the second DMA controller based on the reading instruction; the first DMA controller after data read-write initialization reads cache data from the internal storage device, and transmits the cache data to the GPU via the internal PCIe switch through the established GDS connection; wherein the GDS connection between the GPU and the internal storage device is established through the system controller, the second DMA controller, the internal PCIe switch and the first DMA controller. According to the method, high-speed direct data transmission of the GPU BOX can be achieved, CPU data transfer is not needed, and the data transmission efficiency is greatly improved.

The invention discloses a photoetching technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask plate line manufacturing method and photoetching equipment, and the photoetching technology implementation method comprises the following steps: selecting a first mask plate, and aligning and exposing the first mask plate and a first original pattern unit through a second alignment mark, transferring the first mask pattern to a first exposure area; longitudinally moving the substrate by M times of the longitudinal size of the original pattern for alignment exposure, and transversely moving by 1 time of the transverse size of the original pattern for alignment exposure to complete exposure of other M * 1 chipset exposure areas; a second mask is selected to be aligned with the first original pattern unit for exposure through a second alignment mark, and a second mask pattern is transferred to a second exposure area; and transversely moving the substrate by N times of the transverse size of the original pattern for alignment exposure, and longitudinally moving by 1 time of the longitudinal size of the original pattern for alignment exposure, thereby completing exposure of other 1 * N chipset exposure areas. According to the scheme, high-density interconnection of multiple chips is realized.

The invention belongs to the technical field of Ethernet high-speed interconnection, and provides a high-speed low-delay 10-gigabit switching method and system based on an FPGA, and the method comprises the steps: receiving Ethernet data frames, storing effective data frames in a data caching module, and generating a caching write-in address and a control signal; reading a destination address, a source address and a type field of the analyzed data frame from the data caching module, and updating a forwarding address table through a dynamic learning mode or a preset mode; based on the updated forwarding address table, a three-level assembly line framework is adopted to complete address searching; reading the data frame from the cache according to the forwarding decision, repackaging the Ethernet header information and the check code, and controlling the sending standard rate; and meanwhile, the sending rate is dynamically adjusted, and VLAN division, port rate and queue scheduling parameters are optimized in combination with an external configuration command. According to the invention, the onboard processor is utilized to cooperate with the FGPA to realize the fast search of the forwarding table, the residence time of the data packet in the switching unit is reduced, and the operation efficiency of the side application is improved.

The invention discloses a communication method and system for interconnection and intercommunication between charging platforms, and the method comprises the steps: obtaining a platform standardized data package according to the original data of a charging pile; according to the platform standardized data packet, obtaining a data stream after peak clipping; according to the data stream after the peak clipping, obtaining a middle and electric connection 102-X protocol interaction message; obtaining a data frame which is converted into a target platform according to the message interacted by the medium and electric connection 102-X protocol; obtaining an encrypted data block and a signature abstract according to the data frame of the target platform; according to the encrypted data block and the signature abstract, obtaining data subjected to secure transmission and verification; and according to the data failed in verification or the abnormal data, obtaining the repaired data or alarm information. According to the invention, the efficiency and accuracy of data communication are improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

The embodiment of the invention discloses a soft bus power terminal heterogeneous interconnection method and system based on an Ethernet protocol stack. The method comprises the following steps: dynamically calculating fragment parameters according to the difference of different protocol stacks in heterogeneous network interconnection; based on a dynamic programming algorithm, generating a self-adaptive fragmentation scheme according to the input parameters, and forming an integrated fragmentation recombination framework; based on an intelligent decision-making mechanism, an optimal fragmentation strategy and a recombination mechanism are generated, a simulation platform is established, different network scenes and service flows are simulated, a simulation result of the simulation platform is combined with a result of the intelligent decision-making mechanism, and the effect of an intelligent decision-making algorithm is optimized. And transmitting and recombining the data packet by adopting an encryption and authentication mechanism. According to the scheme, the efficiency and the reliability of data transmission in the heterogeneous network are remarkably improved, the compatibility problem among different network protocol stacks is effectively solved, the fragmentation frequency during cross-network transmission is reduced, the time sequence and the integrity of data packets are ensured, and the processing overhead and the network delay are reduced.

A method and apparatus for frequency domain diagnosis of a power cable defect on the basis of a cross-interconnection box structure. The method comprises: by means of a wiring terminal intersecting a three-phase shielding layer of a cross-interconnection box, injecting a broadband signal, and obtaining a time domain result (S101); according to the time domain result being mapped into a frequency domain, performing analysis, and obtaining impedance spectrum results of a left end and a right end of an injection cross-interconnection box (S102); and, according to the impedance spectrum results, diagnosing hidden danger defects of an outer sheath and a main insulation in a three-phase cable (S103). The present disclosure solves the problem in the related technology that traveling wave reflection method diagnosis strategies cannot avoid direct connection to a cable core wire when identifying a main insulation fault in a cable, which limits the application scenarios of a traveling wave injection method to only being applicable to inspection before a cable has been put into operation and cable defect assessment after a cable fault has occurred. Additionally, the present disclosure solves the problems of high device requirements and testing costs, leading to the inability to meet daily operation and maintenance inspection requirements of cables and various test scenarios.

A network environment comprises a plurality of host machines that are coupled to each other via a network fabric comprising a plurality of switches, that in turn include a plurality of ports. Each host machine comprises one or more GPUs. A first subset of ports from is associated with a first virtual plane, wherein the first virtual plane identifies a first collection of resources to be used for communicating packets from / to host machines associated with the first virtual plane. A second subset of ports is associated with a second virtual plane that is different from the first virtual plane. A first host machine and a second host machine are associated with the first virtual plane and the second virtual plane, respectively. A packet is communicated from the first host machine to the second host machine using ports from the first subset of ports and the second subset of ports.

The invention discloses a server cabinet, and relates to the technical field of servers, the server cabinet comprises a plurality of computing nodes and a plurality of switching nodes, the plurality of computing nodes are arranged along a first direction, the plurality of switching nodes are arranged along a second direction, and each computing node is provided with a plurality of first connectors in a third direction. Each computing node is provided with a plurality of first connectors in the first direction, each switching node is provided with a plurality of second connectors in the third direction, and the first connectors are correspondingly connected with the second connectors, so that each computing node and each switching node are orthogonally connected when being blind-inserted into the server cabinet, and therefore, the computing nodes and the switching nodes can be orthogonally connected to form full interconnection; and the use of cables for connecting the computing nodes and the switching nodes is reduced, so that the cost required by full interconnection is reduced. Meanwhile, due to the design of orthogonal connection, the complexity of wiring is reduced, and the fault risk caused by wiring errors or poor connection is reduced, so that the reliability of the system is improved.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention discloses a time delay optimization method and device of a network interconnection system, electronic equipment and a medium, and relates to the field of network communication, and the method comprises the steps: adjusting the BAR resource window size of a non-transparent bridge processor in a BIOS based on a firmware file of a target processor, and re-burning the adjusted BIOS to a BMC processor, and initializing each DMA channel in the non-transparent bridge processor to obtain a physical address of each DMA channel, identifying the minimum physical address as a mapping initial address of the BAR, and mapping the mapping initial address and the BAR address space sum to a virtual address space of a user mode so as to access each DMA channel. The problem that the requirements for the overall bandwidth and low delay of the storage controller cannot be met when one DMA channel is started is solved, the data concurrent processing capacity of the non-transparent bridge processor is improved by enabling the four DMA channels and mapping the four DMA channels to the user mode, and therefore the interconnection bandwidth of the controllers is higher, and the interconnection delay of the controllers is lower.

The invention is applicable to the technical field of integrated circuit design, and provides a method for repairing crosstalk noise violation on a data path, which comprises the following steps of: reading a crosstalk noise violation report of a static time sequence analysis STA tool; finding an interconnection line corresponding to each violation in the report from a layout wiring tool, and finding adjacent interconnection line position information and connected logic unit information of the current interconnection line; selecting a corresponding repairing scheme according to the specific conditions of the interconnection lines and the connected logic units, and executing and adjusting the repairing scheme so as to repair crosstalk noise on a data path; and after a round of repair is completed, if crosstalk noise violation is also detected in the STA tool, the steps need to be executed again until all crosstalk noise problems are solved. According to the method provided by the invention, the crosstalk problem is efficiently identified and solved through an automatic process, the signal integrity and the function correctness of circuit design are ensured, and compared with a traditional scheme, the method is more targeted, and the gain brought by single change is favorably improved.

The invention discloses a consistency interconnection control device and method, an electronic device, a product and a computing system, and relates to the technical field of computers, the consistency interconnection control device is provided and comprises a consistency interconnection network, a first controller and a first connector, the consistency interconnection network comprises a plurality of interconnected consistency interconnection nodes, the consistency interconnection node is connected with the first card slot for installing the acceleration card through the first connector, and the first controller manages the state of the cache line of the acceleration card and controls the consistency interconnection network to execute the consistency interconnection read-write task between different acceleration cards, so that the consistency interconnection system for the acceleration computing cluster is realized. By implementing the cache consistency between the acceleration cards, when the acceleration computing cluster executes distributed computing, the cache can be hit firstly, so that access to a local memory and memories of other acceleration cards is reduced, the problem of high time consumption of communication between different accelerators of the acceleration computing cluster is solved, and the efficiency of distributed computing is improved.

The invention discloses a detection method for representing interface roughness of an interconnection structure by using low-frequency noise. According to the method, constant low current is applied to a to-be-tested structure, output current of the to-be-tested structure is measured, and then random current fluctuation generated by interaction of electrons and interconnection structure interfaces, defects and phonons is obtained; fourier transform is carried out on random current fluctuation to obtain frequency domain parameters of the current; calculating the power spectrum density of random current fluctuation according to the frequency domain parameter of the current; wherein the PSD is proportional to the f, and then fitting is carried out to obtain a slope k; and evaluating the interface roughness of the interconnection structure by using the slope k. According to the method, the experiment can be rapidly completed under the condition that the sample is not damaged, and the reusability of the sample is improved. In addition, the low-frequency noise characterization method does not need direct contact or imaging, is suitable for testing packaged chips, and can measure the overall roughness of long interconnection line segments at the same time.