1190 results about "Interconnection" patented technology

The invention relates to the technical field of data compression, in particular to an intelligent data compression method and system based on multi-protocol heterogeneous equipment interconnection. The method comprises the following steps: when it is detected that a new heterogeneous device applies to join a network, carrying out communication protocol real-time analysis and protocol conversion adaptation to obtain a heterogeneous device adaptation protocol; carrying out multi-device data stream receiving according to a heterogeneous device adaptation protocol, and generating data streams of a plurality of time windows; adaptive coding and multi-level compression are carried out on the data streams of the multiple time windows, and a multi-device adaptive compression mechanism is constructed; identifying compression load characteristics of each heterogeneous device, and performing dynamic task allocation to obtain an intelligent task allocation strategy; and driving real-time data intelligent compression operation based on an intelligent task allocation strategy and a multi-device adaptive compression mechanism. According to the invention, efficient and adaptive data compression of different devices is realized, and the data transmission efficiency and quality are improved.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention provides a chip interconnection line delay prediction method and device, equipment and a storage medium, and the method comprises the steps: combining geometric design parameters generated in a chip wiring stage with electrical attribute parameters, and generating a distributed RC network model; carrying out electromagnetic field solving on interconnection lines of the distributed RC network model, extracting coupling capacitance parameters of interconnection line segments, and generating a parasitic parameter file; correcting the resistance value and the capacitance value of the parasitic parameter file according to the PVT environment data of the chip interconnection line, and generating target RC network data; inputting the target RC network data and the interconnection line delay value of the parasitic parameter file into a preset deep neural network for training to obtain a first delay prediction result; and fusing the first delay prediction result with a second delay prediction result calculated by the distributed RC network model to generate a delay prediction value. According to the scheme, the accurate delay prediction value can be generated in a complex interconnection wiring environment, and the accuracy of delay prediction is improved.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

The invention relates to a GPU cluster, a redundancy optimization method of the GPU cluster, electronic equipment, a storage medium and a computer program product, the GPU cluster comprises a plurality of GPU cabinets, and each GPU cabinet comprises a plurality of GPU nodes, a GPU extension frame and an interconnection module; for any GPU cabinet, each GPU node in the GPU cabinet comprises a plurality of physical GPUs, and a GPU expansion frame in the GPU cabinet comprises a plurality of standby virtual GPUs; the interconnection module in the GPU cabinet is used for carrying out GPU interconnection on a plurality of GPU nodes and a plurality of GPU expansion frames in the GPU cabinet; and the plurality of standby virtual GPUs in the GPU extension frame in the GPU cabinet are used for providing redundant computing resources for the plurality of physical GPUs in each GPU node in the GPU cabinet. According to the embodiment of the invention, the GPU card-level redundancy capability can be effectively realized.

The invention discloses a CXL protocol extension method, device and system based on the Ethernet. The method comprises the following steps of: carrying out long-distance expansion interconnection on a CXL (Compute Express Link) protocol by using Ethernet as a physical transmission medium; by bearing the CXL protocol on the Ethernet, the range of memory pooling is expanded from the rack level to the whole data center (kilometer level), and the potential of the CXL technology is thoroughly released; through protocol translation, label management and flow control realized by pure hardware, an operating system kernel and a software protocol stack are bypassed, so that the end-to-end memory access delay is far lower than that of any software-based network storage scheme, and a reliable request-response tracking and timeout retransmission mechanism is realized through a hardware label manager. By distinguishing the control flow and the data flow, differentiated QoS guarantee is provided for different types of memory flows, and the stability of the system under high load is ensured.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention provides a bus interconnection system, a signal processing method and a server, and relates to the technical field of computers. In the bus interconnection system, the port of the bus switch can be expanded by using the channel aggregation module on the premise of ensuring that the interconnection topology is formed between the processor and the peripheral equipment, the interconnection topology is formed between the peripheral equipment, and the communication connection can be established between the processor and the peripheral equipment, and the communication connection can be established between the peripheral equipment; and the number of peripheral equipment which can be accessed to the bus switch can be effectively expanded. Therefore, a plurality of bus switches can be prevented from being mutually connected to form the interconnection topological structure, the interconnection topological structure can be simplified, the system complexity can be reduced, and the port utilization rate of the bus switches can be improved.

The invention discloses a flexible interconnection configuration method and system for a power distribution network frame, a medium and equipment, and belongs to the technical field of power distribution network planning of an electric power system, and the method comprises the steps: obtaining an equipment parameter, a source load parameter and a network topology parameter of a current power distribution network; based on the equipment parameters, the source load parameters and the network topology parameters, taking the joint planning of SOP, interconnection switches and lines as an optimization object, taking the lowest comprehensive equiannual value cost of an investment scheme as a target, constructing a target function, and combining a physical structure constraint, an equipment operation constraint, an electrical performance constraint and a network reconstruction constraint to construct a planning model; and iteratively solving the planning model, and outputting a configuration scheme for power distribution network reconstruction. Therefore, by implementing the method, the problems of high investment cost, low operation efficiency and difficulty in realizing efficient consumption of new energy and economic operation of the system under resource constraints caused by lack of cooperation of equipment and line planning in a power distribution network planning configuration method in the prior art can be solved.

The invention relates to the technical field of alternating-current and direct-current power distribution networks, in particular to an alternating-current and direct-current power distribution network SOP partition interconnection locating and sizing method and a related device, and the method comprises the steps: obtaining GIS multi-source data and power distribution network data of a target region; dividing a power supply area according to the GIS multi-source data and the power distribution network data to obtain a to-be-interconnected partition pair set; generating a high-quality interconnected partition pair set by using the to-be-interconnected partition pair set; constructing a target optimization model by taking the minimum total operation cost as an optimization target and taking a power balance constraint, a node voltage constraint, a branch capacity constraint, an SOP operation constraint, an SOP reactive power constraint and an SOP capacity constraint as constraint conditions; and inputting the high-quality interconnection partition pair set into the target optimization model, cooperatively solving the target optimization model by adopting a double-layer optimization algorithm to obtain the optimal position and the optimal capacity of the SOP, and solving the technical problem that the existing SOP locating and sizing method is difficult to meet the targets of engineering feasibility and optimal operation benefit at the same time.

The invention provides an equipment networking method and system based on a distributed soft bus, and the method comprises the steps: starting a distributed soft bus module and carrying out the discovery of adjacent equipment, and obtaining a trusted equipment set after identity verification; a point-to-point communication link between the devices is established according to the trusted device set, and a distributed mesh interconnection topology is formed; performing routing calculation and data forwarding on data transmission in the mesh topology to realize end-to-end communication; meanwhile, dynamic changes of equipment in the network are monitored, topology updating is carried out, and the network stability is maintained. The scheme does not depend on the dependence of the traditional star network on the central node, realizes direct interconnection between devices through the distributed soft bus technology, improves the fault-tolerant capability and transmission efficiency of the network, and solves the problems of poor network reliability and limited expansibility in the prior art.

The invention discloses an ultra-wideband RCS (radar cross section) reduction metasurface with mixed wave absorption and diffuse scattering and a wave-transparent window, and belongs to the technical field of electromagnetic metamaterials. The metasurface adopts a four-layer cascade structure and comprises a first layer of polarization conversion structure, a second layer of 2.5 D lossy structure, a third layer of Jerusalem cross-shaped lossy structure and a fourth layer of frequency selective surface structure. By loading a lumped resistor at a specific position and adopting a metal through hole interconnection technology, dual functions of radar cross section reduction in a 1-20GHz ultra-wideband and low insertion loss wave transmission in a 8-12GHz frequency band are realized. The structure of each layer adopts a highly symmetrical design and has the characteristic of polarization insensitivity, and meanwhile, by optimizing interlayer air gaps and dielectric material selection, the structure compactness is realized on the premise of ensuring the performance. The method has important application value in the aspect of integration of stealth equipment and a communication system.

The invention provides a flexible interconnected power distribution network power supply recovery method considering wind and light uncertainty and a related device. According to the method, the objective function, the system power flow constraint, the E-SOP operation constraint, the system safe operation constraint and the wind and light output constraint are constructed by fully considering the wind and light uncertainty model and the energy storage type intelligent soft switch E-SOP loss condition. And solving the objective function based on each constraint condition, and controlling the E-SOP by adopting the solved optimal power supply recovery topology so as to recover the power supply of the power-losing node in the flexible interconnection power distribution network. Therefore, the self-healing control support capability of the E-SOP can be fully excavated, and the influence of the wind and light uncertainty on the recovery of the power distribution network can be explored, so that the fault recovery effect of the flexible interconnection power distribution network can be improved, the power supply recovery capability of the power distribution network can be effectively improved, and certain help is provided for the safe and stable operation of the power distribution network.

The invention discloses a flexible interconnection and mode smooth switching method for a distributed power generation system, and relates to the technical field of distributed power generation, and the method comprises the steps: building a droop control relation through continuously collecting DC voltage and current for a source side rectifier of each power generation unit; in a normal mode, the output current of the back-to-back rectifier and the voltage of an intermediate capacitor are collected, the same phase of the current and the load current is kept by using phase locking control, and voltage regulation is realized by combining a dq coordinate model; when a fault of a source side rectifier is detected, an alternating current reference value is generated based on intermediate capacitor voltage deviation and is input into a single current loop controller for voltage stabilization, and meanwhile, a phase advance, adaptive gain and integral saturation resistance mechanism is introduced, so that quick response and stable operation are ensured; in the mode switching process, normal control quantity and fault control quantity are subjected to weighted fusion, and dynamic consistency is achieved through pole matching and reference pre-alignment; the intermediate capacitor voltage fluctuation is significantly reduced, the recovery time is shortened, and the system stability and reliability are improved.

The invention provides a medium and low voltage flexible direct current interconnection scheduling method, and relates to the technical field of power distribution network scheduling, and the method comprises the steps: carrying out the feature weight correction of a first fault judgment result and a second fault judgment result according to a transient feature quantity, and obtaining the corrected fault positioning information; specific fault equipment is determined according to the corrected fault positioning information, and a fault token containing the available capacity of the specific fault equipment is generated; and obtaining a dynamic capacity boundary of the thermoelectric coupling constraint of the specific fault equipment, constructing a dynamic scheduling optimization model, and performing optimization scheduling on the specific fault equipment according to the dynamic scheduling optimization model. According to the method, the fault information is obtained through coupling backstepping and spectral decomposition, weight correction is carried out in combination with the transient characteristics in the current limiting mode, the fault token containing the available capacity is generated and participates in scheduling, unavailable equipment can be eliminated in time or participated in derating, and the power supply continuity of key loads is guaranteed.

The invention provides a chip routing method and device, electronic equipment and a storage medium, and relates to the technical field of chip design and manufacture, and the method comprises the steps: carrying out the first-stage interleaving among a plurality of input and output modules based on a memory address of a current data request, and determining a target input and output module; in the target input and output module, performing second-level interleaving among the plurality of links based on the memory address, and determining a target link; and performing third-level interleaving among the plurality of point-to-point channels of the target link, and determining the point-to-point channel of the current data request. According to the method and the device provided by the invention, a three-level progressive interleaving architecture which performs dynamic calculation completely based on the memory address is constructed, the problem that hardware resource consumption is sharply increased due to chip interconnection scale enlargement is solved, the chip cost and power consumption are remarkably saved, and through a step-by-step refined load balancing mechanism, the load balancing efficiency is greatly improved. The routing efficiency in the chip is improved, and the overall communication bandwidth and system performance of chip interconnection are improved.

The invention belongs to the technical field of power grid dispatching, and particularly discloses a dual-port equivalent cluster aggregation method. According to the method, an independent aggregation operation interval is established for two ports by solving a specific robust optimization problem, an initial aggressive boundary is formed, and an initial high-dimensional polyhedral model is established. The key improvement is that the condition extreme value of the power of the other port is solved under the constraint of the operation interval of one port, so that the physical coupling relation is converted into a series of accurate boundary points, and meanwhile, the calculation complexity is also reduced. And finally, cutting the initial and aggressive high-dimensional model by using the boundaries, eliminating an infeasible space generated by neglecting coupling, and quickly generating a feasible dual-port aggregation interval. The problems of large model error and low aggregation efficiency caused by dual-port interconnection are systematically solved.

The invention provides a half-bridge system, a chip and a preparation method of the half-bridge system, and relates to the technical field of power. The half-bridge system comprises an upper tube and a lower tube which are connected in sequence; the source electrode of the upper tube is connected with the drain electrode of the lower tube; hybrid bonding is arranged between the source electrode of the upper tube and the drain electrode of the lower tube, the source electrode of the upper tube and the drain electrode of the lower tube form interconnection through the hybrid bonding, and the source electrode of the upper tube and the lower tube form an inverted structure through the hybrid bonding. Direct and short-distance interconnection of the source electrode of the upper tube and the drain electrode of the lower tube can be achieved through mixed bonding, and compared with traditional bonding wires and long PCB routing, the current transmission path is greatly shortened, and parasitic inductance can be remarkably reduced. In addition, the inverted structure further optimizes the spatial layout and the connection mode between the devices, reduces additional leads and other parasitic sources, and weakens the source of parasitic inductance generation from the structural level.

The invention relates to the technical field of semiconductor packaging, and discloses a bonding wire welding method based on bare chip interconnection, and the method comprises the steps: collecting and fusing acoustic response and optical reflection signals of a bonding interface in real time through a multi-mode in-situ sensing mechanism integrating acoustic resonance and surface plasmon resonance; dynamically calculating the thickness, the mechanical coupling deformation and the energy dissipation state of the intermetallic compound layer; and the ultrasonic power and the bonding force are subjected to closed-loop adjustment in combination with a model prediction control algorithm, so that the welding process is evolved along a preset optimal physical path all the time. The system comprises a multi-mode sensing welding head, a synchronous data acquisition module, a state resolving module and a self-adaptive control module. The transparent and intelligent welding process is realized, and the bonding consistency, reliability and yield of high-density interconnection are remarkably improved.

The invention discloses a semiconductor package and a semiconductor package assembly. The semiconductor package comprises a first interconnection structure; the first chip is arranged on the first interconnection structure and is coupled with the first interconnection structure; a first redistribution layer disposed on the first chip and coupled to the first chip; a molding compound disposed on the first interconnect structure and encapsulating the first chip and the first redistribution layer; and a through-mold via passing through the molding compound and connecting between the first redistribution layer and the first interconnect structure; the first chip comprises a first back connection structure and a second back connection structure, a first transistor layer; a first front connection structure; and a first carrier on the first interconnect structure and coupled to the first interconnect structure. Therefore, the thick power supply / ground wire and the thin signal wire are separately arranged, and mutual interference possibly existing between power supply / ground transmission and signal transmission can be avoided.

The invention provides a read-write data processing method and system based on chip particle interconnection interface address allocation. The method comprises the following steps: mapping a core particle interconnection structure formed by interconnection of a plurality of core particles into a directed graph; determining data streams among a plurality of core particles according to chip product design requirements, and simplifying the directed graph into sub-graphs based on the data streams; allocating an address to each interconnection interface controller from a root node of the sub-graph; and each interconnection interface controller identifies whether the received read-write request is forwarded to the equipment of the current bus or routed to other interconnection interface controllers according to the allocated address. By utilizing the method and the system, chip framework designers can determine the number and the direction of accessing other devices by the main device of each subsystem according to actual product development requirements, so that the degree of freedom of product design is greatly improved, and the data processing efficiency of products is greatly improved.

To provide a wiring circuit board capable of increasing rigidity of a wiring part in a thickness direction while allowing movement of the wiring part in a second direction.SOLUTION: The wired circuit substrate 1 includes a wired portion 3A and a supporting portion 3A supporting one end portion of the wired portion 2A. The interconnection part 3A includes a first insulating layer 12, an interconnection 133A, a metallic support layer 11, and a covering layer 15. The covering layer 15 has a first portion 151 covering the side S1 of the metallic support layer 11 and a second portion 152 covering the other side S2 of the metallic support layer 11 in the thickness direction. The thickness T12 of the second portion 152 is larger than the thickness T11 of the first portion 151.SELECTED DRAWING: Figure 2

The invention discloses a packaging structure, a packaging method and an electronic component, and relates to the technical field of semiconductors, and the packaging structure comprises a first chip, a second chip, a first electric connection part, a second electric connection part and a rewiring layer. Through the superposition cross layout of the first chip and the second chip, while the integration level is ensured, the wiring space is expanded by using the radial distribution of the non-overlapping area, and the coverage connection of the re-wiring layer is matched, so that the high-density interconnection is realized, and the parasitic inductance and parasitic capacitance are reduced; meanwhile, the signal transmission path is shortened through the combination of the cross layout and the rewiring layer, and the parasitic inductance and the parasitic capacitance are further reduced; besides, paths of different signals can be physically isolated through independent distribution of the non-overlapping areas, parasitic inductance and parasitic capacitance are further reduced, signal delay, reflection and coupling interference are reduced, and the problem of poor signal transmission performance caused by wiring limitation in traditional packaging is effectively solved.

A multi-port flexible interconnection device for distribution networks, and a control method and system thereof are provided. The multi-port flexible interconnection device includes a bipolar output inverter and a multi-port flexible interconnection module connected in series therewith. The multi-port flexible interconnection module includes multiple unipolar output inverters which share the same common connection bus and are connected in parallel, and AC output ports of each unipolar output inverter are interconnected with different feeders. By adjusting an AC output voltage in series between the feeders, active and reactive power decoupling control for each feeder is achieved. Energy balance for the entire device and its components is maintained by controlling an internal circulating current of the bipolar output inverter. The provided introduces the multi-port flexible interconnection module to interconnect multiple feeders in a distribution network, enabling flexible power interchange between feeders and facilitating a flexible AC distribution network featuring multi-terminal interconnection.

The invention discloses a fault diagnosis and self-healing control method, system, equipment and medium for a flexible interconnection device of a power distribution network, and belongs to the technical field of fault diagnosis and control of the power distribution network, and the method comprises the steps: building a system state vector, collecting operation parameters of the power distribution network, and carrying out the weighted fusion; performing quality inspection on the original data based on the acquired operation parameters, and dynamically adjusting model parameters through digital twin synchronization and model parameter updating; deep learning is carried out to carry out multi-level fault feature extraction, and multi-scale feature fusion is carried out; a fault mode identification module is started, and fault probability is calculated for fault classification; evaluating the severity of the fault according to a fault diagnosis result, selecting an optimal control strategy, and carrying out self-healing control; and fault early warning is started to estimate a future fault occurrence probability, and early warning information of different levels is issued to perform preventive maintenance. According to the invention, full-process automation and intelligentization from data perception and intelligent diagnosis to active control and prospective maintenance are realized.

The invention provides a PCIe (Peripheral Component Interconnect Express) endpoint device communication method, device and equipment based on software defined interconnection. The implementation scheme comprises the following steps: acquiring a communication request between endpoint devices; based on the bound queue pair relationship, applying for a point-to-point memory in a base address register space exposed by the receiving end, and determining a destination address corresponding to the communication request; according to the communication request and the destination address, the work queue element is issued to the bound queue pair, so that the endpoint device corresponding to the queue pair executes data handling; and generating a completion event associated with the communication request based on interruption information sent by the endpoint equipment, and pushing the completion event into a completion queue, so that a user reads and judges a transmission result through an event acquisition interface. According to the scheme, an end-to-end communication path can be communicated through a unified queue and event interface, the overall efficiency is improved while the bottom layer difference is shielded, high performance and low delay are ensured, reliability and restorability are enhanced, and good parallel expansion capacity is achieved.

The present invention provides an optoelectronic interconnection packaging structure and a preparation method therefor. The method comprises: using a laser method, forming a first blind hole and a second blind hole, the bases of the first blind hole and the second blind hole being in a glass substrate, then performing thinning processing on a first surface of the glass substrate and a second surface of the glass substrate, to form a first through hole and a second through hole, respectively, that are arranged in an offset manner. On the basis of the laser method and the thinning processing, the present application can prepare a high-performance TGV adapter plate on a glass substrate that has a relatively small pitch and a relatively small CD size, is thin and suitable for high-density arrangement, and can effectively prevent metal posts from overlapping. In addition, an optical waveguide layer is disposed between the glass substrate and a rewiring layer, and the TGV adapter plate is used to connect an electrical chip and an optical chip, which can make metal wiring more flexible, achieve photoelectric interconnection integration, reduce package size, lower power consumption, and improve reliability. The application is thus applicable to high-density integrated packaging, and can achieve good optoelectronic signal transmission.