1464 results about "Interconnection" patented technology

The invention discloses a consistency interconnection processing device, a data transmission method, equipment and a heterogeneous system, and relates to the technical field of data transmission, the consistency interconnection processing device installed on the equipment is utilized, the consistency interconnection processing device comprises a consistency interconnection port and a consistency interconnection controller, the consistency interconnection controller controls the consistency interconnection interface to establish a consistency interconnection communication link between the devices and distribute a cache space from the devices where the consistency interconnection interface is located, so that consistency interconnection between the devices is achieved; the consistency interconnection controller monitors the cache line state of the device where the consistency interconnection controller is located and the cache line states of other devices and records the global cache line state table, when the consistency interconnection transaction request is executed, the global cache line state table is inquired according to the target data information and then the target access position is determined, actual memory access detection does not need to be carried out, and the memory access efficiency is improved. Therefore, the number of times of executing the consistency access is reduced, the consistency maintenance overhead of the consistency interconnection between the devices is reduced, and the memory access performance of the consistency interconnection between the devices is improved.

The invention discloses an implementation method of a multi-chip high-density connection photoetching technology, an implementation method of a photoetching technology for multi-chip interconnection, a chip-level chip interconnection method, a manufacturing method of a mask plate line and photoetching equipment. The implementation method of the multi-chip high-density connection photoetching technology comprises the following steps: selecting a first mask plate to align and expose with a first original pattern unit in a first M * N chipset through a second alignment mark, and transferring a pattern of the first mask plate to an exposure area covering the first original pattern unit; longitudinally moving the substrate by M times of the longitudinal size of the original pattern or transversely moving the substrate by N times of the transverse size of the original pattern to execute alignment exposure, and completing exposure of corresponding areas of other M * N chip groups; and other masks are selected to repeatedly perform exposure on other corresponding pattern units of the first M * N chip set, and longitudinal movement or transverse movement is repeatedly performed to complete exposure of corresponding areas of the corresponding pattern units in other M * N chip sets. According to the scheme, high-density interconnection of multiple chips is realized.

The invention relates to a multi-protocol communication conversion module and a communication method of an intelligent safety fence, and belongs to the technical field of communication protocols. The multi-protocol communication conversion module comprises the following steps: step 1, performing protocol type identification on various protocol heterogeneous devices in the intelligent safety fence; step 2, constructing a data analysis rule base of the protocol according to the identified protocol type; 3, analyzing the data according to a data analysis rule base of the protocol, and converting the analyzed data into a uniform data format so as to facilitate data interaction among the heterogeneous devices; 4, performing protocol packaging on the data converted into the uniform format according to a protocol type supported by the target protocol heterogeneous equipment and a pre-constructed protocol mapping table; step 5, sending the packaged data to the target protocol heterogeneous device, and realizing interconnection and intercommunication among the protocol heterogeneous devices in the intelligent safety guardrail; the method has the beneficial effects that the analyzed data is converted into a uniform data format, and interconnection among protocol heterogeneous devices is realized.

The invention relates to the technical field of data compression, in particular to an intelligent data compression method and system based on multi-protocol heterogeneous equipment interconnection. The method comprises the following steps: when it is detected that a new heterogeneous device applies to join a network, carrying out communication protocol real-time analysis and protocol conversion adaptation to obtain a heterogeneous device adaptation protocol; carrying out multi-device data stream receiving according to a heterogeneous device adaptation protocol, and generating data streams of a plurality of time windows; adaptive coding and multi-level compression are carried out on the data streams of the multiple time windows, and a multi-device adaptive compression mechanism is constructed; identifying compression load characteristics of each heterogeneous device, and performing dynamic task allocation to obtain an intelligent task allocation strategy; and driving real-time data intelligent compression operation based on an intelligent task allocation strategy and a multi-device adaptive compression mechanism. According to the invention, efficient and adaptive data compression of different devices is realized, and the data transmission efficiency and quality are improved.

The embodiment of the invention discloses a chip verification environment generation method and system, electronic equipment and a storage medium, relates to the technical field of integrated circuit verification, can adapt to verification environments with different configurations, and improves verification efficiency. The method comprises the following steps: constructing or calling a verification environment template; analyzing the initial configuration information and the routing topology information, and generating a target configuration file according to an interface protocol and an interconnection rule of a register transfer level and a model; the routing topology information indicates an interconnection link topology structure between the devices, and the target configuration file indicates a component type corresponding to each device required by simulation forming of each interconnection link and a matched verification component type; loading and instantiating the register transfer level component and the model component based on the verification environment template according to the component type; and according to the verification component type, interconnection is carried out between the register transfer level component and the model component through the verification component, and a chip executable verification environment is generated. The method and the device are suitable for a scene for constructing a chip verification environment.

The invention provides a multimode communication network dynamic scheduling system fused with AI computing power, which belongs to the technical field of communication equipment and artificial intelligence hardware fusion, and is characterized in that based on a four-layer hardware architecture of'core control-computing power support-multimode communication-high-speed interconnection ', an interconnection layer is constructed by adopting high-speed interfaces such as PCIe / SGMII + and the like, and inter-module fault is realized; 10ms low-delay data transmission is realized; the AI computing power module integrated with the 8TOPS NPU is deeply coupled with the multi-mode communication module, and the AI computing power module is quantized and compressed through an LSTM / Transform model and then solidified to an NPU special storage to realize scene self-adaptive scheduling; a'acquisition-identification-decision-feedback 'hardware closed loop is established, the communication interruption rate is reduced in an emergency scene, the overall power consumption is reduced, and AI reasoning is delayed. Through breakthrough hardware architecture design, AI computing power and a multi-mode communication module are deeply integrated, an intelligent communication resource scheduling system is constructed, and dynamic optimal configuration of communication resources in multiple scenes can be realized.

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

The embodiment of the invention discloses a GPU BOX, a server, an interconnection system and a high-speed interconnection and data interaction method. The GPU BOX high-speed interconnection method is characterized in that the GPU BOX comprises a GPU and a control mainboard, an internal PCIe switch, an internal storage device, a first DMA controller and a system controller are integrated in the control mainboard, and a second DMA controller is integrated in the GPU; the system controller receives the reading instruction and performs data read-write initialization on the first DMA controller and the second DMA controller based on the reading instruction; the first DMA controller after data read-write initialization reads cache data from the internal storage device, and transmits the cache data to the GPU via the internal PCIe switch through the established GDS connection; wherein the GDS connection between the GPU and the internal storage device is established through the system controller, the second DMA controller, the internal PCIe switch and the first DMA controller. According to the method, high-speed direct data transmission of the GPU BOX can be achieved, CPU data transfer is not needed, and the data transmission efficiency is greatly improved.

The invention discloses a photoetching technology implementation method for multi-chip high-density connection, a chip-level chip interconnection method, a mask plate line manufacturing method and photoetching equipment, and the photoetching technology implementation method comprises the following steps: selecting a first mask plate, and aligning and exposing the first mask plate and a first original pattern unit through a second alignment mark, transferring the first mask pattern to a first exposure area; longitudinally moving the substrate by M times of the longitudinal size of the original pattern for alignment exposure, and transversely moving by 1 time of the transverse size of the original pattern for alignment exposure to complete exposure of other M * 1 chipset exposure areas; a second mask is selected to be aligned with the first original pattern unit for exposure through a second alignment mark, and a second mask pattern is transferred to a second exposure area; and transversely moving the substrate by N times of the transverse size of the original pattern for alignment exposure, and longitudinally moving by 1 time of the longitudinal size of the original pattern for alignment exposure, thereby completing exposure of other 1 * N chipset exposure areas. According to the scheme, high-density interconnection of multiple chips is realized.

The invention discloses a cross-device memory dynamic complementary utilization method based on CXL protocol interconnection and a computer system. The method comprises the following steps that an ECC module of a memory detects data in the data transmission process; when a data error is detected, the error is positioned by the ECC module, the error counting module corresponding to the position is updated, and an error report is generated; when the counting value of the error counting module reaches a set threshold value, the area corresponding to the position is marked as a failure area; evaluating the states of all memories based on the spatial dimension, the health dimension, the time delay dimension and the load dimension, and selecting a target memory according to an evaluation result of the states of the memories; distributing a new logic address for the failure area based on the error report and a selected target memory; the logic address is transmitted to a target memory through a CXL protocol, and an address mapping table is updated at the same time; and after the mapping is successful, migrating the data of the failure area to the healthy area of the target memory by the system through a CXL protocol.

A method and apparatus for frequency domain diagnosis of a power cable defect on the basis of a cross-interconnection box structure. The method comprises: by means of a wiring terminal intersecting a three-phase shielding layer of a cross-interconnection box, injecting a broadband signal, and obtaining a time domain result (S101); according to the time domain result being mapped into a frequency domain, performing analysis, and obtaining impedance spectrum results of a left end and a right end of an injection cross-interconnection box (S102); and, according to the impedance spectrum results, diagnosing hidden danger defects of an outer sheath and a main insulation in a three-phase cable (S103). The present disclosure solves the problem in the related technology that traveling wave reflection method diagnosis strategies cannot avoid direct connection to a cable core wire when identifying a main insulation fault in a cable, which limits the application scenarios of a traveling wave injection method to only being applicable to inspection before a cable has been put into operation and cable defect assessment after a cable fault has occurred. Additionally, the present disclosure solves the problems of high device requirements and testing costs, leading to the inability to meet daily operation and maintenance inspection requirements of cables and various test scenarios.

The invention belongs to the field of PCIe (Peripheral Component Interconnect Express) chips, and relates to a CXL switching chip of a multi-core-grain architecture and a cross-core-grain routing switching method thereof, and a plurality of CXL switching core grains with uniform specifications are packaged and interconnected to form the CXL switching chip; each CXL switching core particle comprises a plurality of ports, each port can be configured to be in a CXL mode and a D2D mode, and the port of each CXL switching core particle at least comprises a physical layer, a CXL link layer, a CXL transaction layer, a D2D routing layer, a bypass and a multipath selection module; the CXL switching chip further comprises a multi-VC on-chip CXL switching network, and the multi-VC on-chip CXL switching network comprises at least one order-preserving switching VC and one out-of-order switching VC. According to the method, CXL switching chips of various specifications can be flexibly constructed, the design complexity and verification difficulty of the large-scale or multi-port CXL switching chips are effectively reduced, and the production yield of the chips is improved.

The invention provides a chip interconnection line delay prediction method and device, equipment and a storage medium, and the method comprises the steps: combining geometric design parameters generated in a chip wiring stage with electrical attribute parameters, and generating a distributed RC network model; carrying out electromagnetic field solving on interconnection lines of the distributed RC network model, extracting coupling capacitance parameters of interconnection line segments, and generating a parasitic parameter file; correcting the resistance value and the capacitance value of the parasitic parameter file according to the PVT environment data of the chip interconnection line, and generating target RC network data; inputting the target RC network data and the interconnection line delay value of the parasitic parameter file into a preset deep neural network for training to obtain a first delay prediction result; and fusing the first delay prediction result with a second delay prediction result calculated by the distributed RC network model to generate a delay prediction value. According to the scheme, the accurate delay prediction value can be generated in a complex interconnection wiring environment, and the accuracy of delay prediction is improved.

The invention relates to the technical field of integrated circuits, in particular to a multi-FPGA (field programmable gate array) interconnection method based on a data hub, electronic equipment and a medium. Then, obtaining a time division multiplexing proportional gain for adding a direct connection virtual cable to the group hypothesis of the FPGA with the communication requirement and each virtual path set is not empty, updating the virtual path combination set and the virtual path sets of the groups of all the FPGAs until all the virtual path sets are empty, determining a target path combination, and sending the target path combination to the FPGA; and establishing interconnection between the corresponding FPGAs on the basis of the initial topological structure through the data hub based on the target path combination. According to the method, the system frequency of communication between the multiple FPGAs is improved, and the system performance of communication between the multiple FPGAs is optimized.

The invention discloses a circuit, a data processing method, equipment, a medium and a program product in the technical field of computers. In the application, the three-dimensional heterogeneous computing body layer can adapt to diversified computing power requirements, and is beneficial to realizing higher routing and higher data transmission efficiency between nodes. The shared cache layer is beneficial to realizing cache consistency of different heterogeneous computing nodes, and the cache utilization rate is improved. The internal interconnection module and the external interconnection module provided by the interface layer are easy to realize internal and external efficient communication. A first channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the three-dimensional heterogeneous computing body layer and direct connection of physical channels between the control layer and the shared cache layer; a second channel controller provided by the control layer can realize direct connection of physical channels between the control layer and the interface layer; therefore, the communication delay between different levels can be reduced, the data transmission efficiency between different levels can be improved, and a high-bandwidth application scene can be met.

The invention provides a 3D structure core particle test layout design method supporting cross-layer cascade test and single core particle self-test, and the method comprises the following steps: a, designing the test point layout of 3D stacked core particles, each layer of core particles adopting a hexagonal arrangement mode, and enabling a test PIN in one layer to be connected with six signal PINs in the same layer; and meanwhile, a vertical test channel is arranged, so that the in-layer test PIN of each layer is connected with the corresponding test PIN of the adjacent layer through a vertical interconnection structure. According to the invention, full test coverage of 3D stacking is adapted, the problem that interlayer signals are difficult to test in a 3D structure is solved through the in-layer hexagonal layout and the vertical test channel, and full-scene coverage of in-layer, interlayer and cross-core particle signals is realized.

The invention relates to a GPU cluster, a redundancy optimization method of the GPU cluster, electronic equipment, a storage medium and a computer program product, the GPU cluster comprises a plurality of GPU cabinets, and each GPU cabinet comprises a plurality of GPU nodes, a GPU extension frame and an interconnection module; for any GPU cabinet, each GPU node in the GPU cabinet comprises a plurality of physical GPUs, and a GPU expansion frame in the GPU cabinet comprises a plurality of standby virtual GPUs; the interconnection module in the GPU cabinet is used for carrying out GPU interconnection on a plurality of GPU nodes and a plurality of GPU expansion frames in the GPU cabinet; and the plurality of standby virtual GPUs in the GPU extension frame in the GPU cabinet are used for providing redundant computing resources for the plurality of physical GPUs in each GPU node in the GPU cabinet. According to the embodiment of the invention, the GPU card-level redundancy capability can be effectively realized.

The invention discloses a CXL protocol extension method, device and system based on the Ethernet. The method comprises the following steps of: carrying out long-distance expansion interconnection on a CXL (Compute Express Link) protocol by using Ethernet as a physical transmission medium; by bearing the CXL protocol on the Ethernet, the range of memory pooling is expanded from the rack level to the whole data center (kilometer level), and the potential of the CXL technology is thoroughly released; through protocol translation, label management and flow control realized by pure hardware, an operating system kernel and a software protocol stack are bypassed, so that the end-to-end memory access delay is far lower than that of any software-based network storage scheme, and a reliable request-response tracking and timeout retransmission mechanism is realized through a hardware label manager. By distinguishing the control flow and the data flow, differentiated QoS guarantee is provided for different types of memory flows, and the stability of the system under high load is ensured.

Provided in the embodiments of the present application are an interconnection link control method and apparatus, a nonvolatile readable storage medium and an electronic device. The method comprises: reading first device information of a target storage device from a specified configuration space of the target storage device, the target storage device being a storage device connected to a target processor on a server mainboard by means of a specified interconnection link, and the first device information being used for indicating the device type of the target storage device; when the target storage device being of a specified type is determined on the basis of the first device information, acquiring second device information of the target storage device, the second device information being used for indicating the specified interconnection link used for connecting the target storage device to the target processor; and enabling a volume management device (VMD) function of the target interconnection link indicated by the second device information, the VMD function being matched with the storage device of the specified type.

The invention provides a load transfer control method and device based on three-port flexible interconnection, and relates to the technical field of power grids. According to the method, the flexible interconnection device is arranged, the power grid state data, the load prediction data and the power generation prediction data of the distributed energy in the power distribution area are monitored, and the load transfer strategy is determined by using the multi-objective optimization function, so that the cooperative control scheme of a plurality of DCAC converters and DCDC converters in the flexible interconnection device is determined; and load transfer control is carried out on the load of the power distribution areas, so that load transfer among the plurality of power distribution areas is realized. According to the invention, rapid and flexible load transfer control is realized through the flexible interconnection device, manual participation is not needed, a power supply strategy can be rapidly adjusted when a power grid fails or a load is suddenly changed, continuous power supply of an important load is ensured, the power failure time and range are reduced, and the problem of long processing time of a traditional transformer area load transfer scheme is solved; and the power supply reliability of the distribution area is improved.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

The invention discloses a multi-port flexible interconnection control method, system, equipment and medium, and the method comprises the steps: obtaining first historical load information and real-time load information of a first flexible interconnection device, obtaining a plurality of clustering results based on the first historical load information, based on each clustering result and the real-time load information, judging whether the first flexible interconnection device breaks down or not; if a fault occurs, respectively acquiring second historical load information of each second flexible interconnection device, determining a plurality of standby devices based on each second historical load information, calculating a target distance between the first flexible interconnection device and each standby device, and determining the standby device with the minimum target distance as a target port flexible interconnection device; and connecting the load of the first flexible interconnection device and the distributed power supply to the target port flexible interconnection device, so that the target port flexible interconnection device performs load scheduling. Therefore, resource waste can be reduced while stable operation of the power grid is guaranteed.

The invention provides a chip time sequence analysis method and device, and the method comprises the steps: determining the second data path time delay between the corresponding ports of interconnected modules according to the first data path time delay of the corresponding port of each module and the interconnection relation information between the modules under the condition that a plurality of modules are in a target stable state, the interconnection module comprises two modules which are directly connected in the modules; and determining convergence information of the top time sequence of the interconnection modules according to the clock period, the trigger establishment time, the clock uncertainty, the clock skew between the interconnection modules and the second data path time delay. According to the method and the device, the time sequence between the interconnected modules can be quickly analyzed before the top-layer time sequence analysis is executed, and the time sequence analysis efficiency of the top layer of the chip is improved without waiting for all the modules to complete a physical implementation process.

The invention discloses a micro-copper pillar bump interconnection resistor electromigration degradation prediction method. The method comprises the following steps: obtaining the net flux of Cu atoms in a Cu6Sn5 layer and a Cu3Sn layer and the net flux of Ni atoms in a Ni-Cu-Sn compound layer under forward current and reverse current; establishing a relationship between the net flux of Ni atoms and the thickness change of the Ni-Cu-Sn compound layer and a relationship between the net flux of Cu atoms and the thickness change of the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity growth model of the Ni-Cu-Sn compound, the Cu6Sn5 layer and the Cu3Sn layer; establishing a thickness polarity consumption model of the Cu bonding pad, the Sn solder and the Ni layer; and establishing a resistance electromigration degradation model of micro-copper pillar bump interconnection. According to the method, the electromigration degradation prediction of the interconnection resistor of the copper pillar bump plated with the Ni layer can be realized, and a large amount of service life and time and economic cost generated by a failure analysis test are greatly reduced or avoided.

The invention provides a bus interconnection system, a signal processing method and a server, and relates to the technical field of computers. In the bus interconnection system, the port of the bus switch can be expanded by using the channel aggregation module on the premise of ensuring that the interconnection topology is formed between the processor and the peripheral equipment, the interconnection topology is formed between the peripheral equipment, and the communication connection can be established between the processor and the peripheral equipment, and the communication connection can be established between the peripheral equipment; and the number of peripheral equipment which can be accessed to the bus switch can be effectively expanded. Therefore, a plurality of bus switches can be prevented from being mutually connected to form the interconnection topological structure, the interconnection topological structure can be simplified, the system complexity can be reduced, and the port utilization rate of the bus switches can be improved.

The invention discloses a flexible interconnection configuration method and system for a power distribution network frame, a medium and equipment, and belongs to the technical field of power distribution network planning of an electric power system, and the method comprises the steps: obtaining an equipment parameter, a source load parameter and a network topology parameter of a current power distribution network; based on the equipment parameters, the source load parameters and the network topology parameters, taking the joint planning of SOP, interconnection switches and lines as an optimization object, taking the lowest comprehensive equiannual value cost of an investment scheme as a target, constructing a target function, and combining a physical structure constraint, an equipment operation constraint, an electrical performance constraint and a network reconstruction constraint to construct a planning model; and iteratively solving the planning model, and outputting a configuration scheme for power distribution network reconstruction. Therefore, by implementing the method, the problems of high investment cost, low operation efficiency and difficulty in realizing efficient consumption of new energy and economic operation of the system under resource constraints caused by lack of cooperation of equipment and line planning in a power distribution network planning configuration method in the prior art can be solved.

The invention relates to the technical field of alternating-current and direct-current power distribution networks, in particular to an alternating-current and direct-current power distribution network SOP partition interconnection locating and sizing method and a related device, and the method comprises the steps: obtaining GIS multi-source data and power distribution network data of a target region; dividing a power supply area according to the GIS multi-source data and the power distribution network data to obtain a to-be-interconnected partition pair set; generating a high-quality interconnected partition pair set by using the to-be-interconnected partition pair set; constructing a target optimization model by taking the minimum total operation cost as an optimization target and taking a power balance constraint, a node voltage constraint, a branch capacity constraint, an SOP operation constraint, an SOP reactive power constraint and an SOP capacity constraint as constraint conditions; and inputting the high-quality interconnection partition pair set into the target optimization model, cooperatively solving the target optimization model by adopting a double-layer optimization algorithm to obtain the optimal position and the optimal capacity of the SOP, and solving the technical problem that the existing SOP locating and sizing method is difficult to meet the targets of engineering feasibility and optimal operation benefit at the same time.

The invention provides an equipment networking method and system based on a distributed soft bus, and the method comprises the steps: starting a distributed soft bus module and carrying out the discovery of adjacent equipment, and obtaining a trusted equipment set after identity verification; a point-to-point communication link between the devices is established according to the trusted device set, and a distributed mesh interconnection topology is formed; performing routing calculation and data forwarding on data transmission in the mesh topology to realize end-to-end communication; meanwhile, dynamic changes of equipment in the network are monitored, topology updating is carried out, and the network stability is maintained. The scheme does not depend on the dependence of the traditional star network on the central node, realizes direct interconnection between devices through the distributed soft bus technology, improves the fault-tolerant capability and transmission efficiency of the network, and solves the problems of poor network reliability and limited expansibility in the prior art.

The invention discloses an electronic receipt matching method and device based on interconnection and interworking, and the method comprises the steps: carrying out the field information extraction of an electronic receipt query request reply message, and obtaining an interconnection and interworking account transaction detail table of an electronic receipt query request; initiating an electronic receipt issuing application, and after the electronic receipt is obtained, filling the stored electronic receipt index into an OFD receipt file index field of the interconnection and interworking account transaction detail table; according to a preset matching rule corresponding to the channel type of the bank transaction detail structured table, matching the bank transaction detail structured table with an interconnection and interworking account transaction detail table; and when the matching is successful, associating the electronic receipt index with the bank transaction detail structured table. And the electronic receipt file and the transaction structured data are rapidly and accurately matched correspondingly.

The invention discloses an ultra-wideband RCS (radar cross section) reduction metasurface with mixed wave absorption and diffuse scattering and a wave-transparent window, and belongs to the technical field of electromagnetic metamaterials. The metasurface adopts a four-layer cascade structure and comprises a first layer of polarization conversion structure, a second layer of 2.5 D lossy structure, a third layer of Jerusalem cross-shaped lossy structure and a fourth layer of frequency selective surface structure. By loading a lumped resistor at a specific position and adopting a metal through hole interconnection technology, dual functions of radar cross section reduction in a 1-20GHz ultra-wideband and low insertion loss wave transmission in a 8-12GHz frequency band are realized. The structure of each layer adopts a highly symmetrical design and has the characteristic of polarization insensitivity, and meanwhile, by optimizing interlayer air gaps and dielectric material selection, the structure compactness is realized on the premise of ensuring the performance. The method has important application value in the aspect of integration of stealth equipment and a communication system.