1039 results about "Contact pad" patented technology

This disclosure generally relates to medical devices that include a sensor transmitter assembly that includes a sensor assembly including a sensor module where a first sensor including a first sensor head having at least one first sensor contact pad is combined with a second sensor including a second sensor head having at least one second sensor contact pad. The sensor transmitter assembly also includes a transmitter assembly positioned on a top of the sensor assembly to form a single unit, the transmitter assembly having at least one transmitter contact disposed on a base of the transmitter assembly, where the first sensor contact pad(s) and the second sensor form a connection path with the transmitter contact(s).

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

Methods for fabricating branched substrates having conductive contact pads and hybrid dielectric bonding surfaces for directly bonding dies and electrically connecting them to the contact pads. A branched substrate can include a main portion and one or more branch portions hybrid bonded to the main portion. Some sections of the branched substrate can be flexible to allow deformable electrical connection between components that are hybrid bonded to different regions of the branched substrate. A flexible branch portion may provide electrical connection between vertically separated layers of two components. The method includes directly bonding a branch portion of the branched substrate to the main portion of the branched substrate via a hybrid bonding interface comprising a conductive interface between contact pads of the main and branch portions and a hybrid bonded dielectric interface between dielectric surfaces of the of the main and branch portions.

A miniaturized paddle card assembly that provides high-speed, high-performance transmission. The paddle card has two or more rows of contact pads for mating with complementary conductors, two or more rows of terminals for cable termination, and alternating dielectric layers and metal layers. The two or more rows of terminals are disposed on respective metal layers. Such a configuration enables conductive traces electrically connecting corresponding contact pads and terminals to be substantially straight, and therefore reduces the lengths of the conductive traces. It is also reduced that the size of the paddle card in both a lateral direction parallel to the rows and a longitudinal direction perpendicular to the lateral direction, without changing the thickness of the paddle card. With the paddle card assembly provided herein, the integrity of the signals transmitted therethrough can be maintained and / or improved at higher speed.

Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

The utility model relates to a semiconductor structure. The semiconductor structure comprises a substrate; the source electrode, the grid electrode and the drain electrode are stacked on the substrate; the first isolation layer is arranged between the grid electrode and the drain electrode; the second isolation layer is arranged between the first isolation layer and the drain electrode; the channel layer penetrates through the grid electrode, the first isolation layer and the second isolation layer, and the channel layer is arranged on the source electrode; the gate dielectric layer is arranged between the gate and the channel layer; the insulating layer is arranged on the inner side of the channel layer; the contact pad is arranged on the insulating layer; the nitrogen component content of the second isolation layer is greater than the nitrogen component content of the first isolation layer. The second isolation layer protects the first isolation layer in the etching or grinding process, the first isolation layer is prevented from being damaged, the integrity of the semiconductor structure is protected, and the product yield of the semiconductor structure is improved.

An information handling system main printed circuit board having a CPU couples to a graphics printed circuit board having a GPU with an interposer that includes contacts and wirelines that communicate signals between the separate boards. For example, an interposer couples to an upper and lower side of the main and graphics printed circuit boards to align spring contacts with contact pads of the main and graphics printed circuit so that signals are transferred through the interposer, which also provides a physical structure to define a motherboard with the assembly of the main and graphics printed circuit boards into a single piece.

The invention belongs to the technical field of electric power, and discloses an isolating switch which comprises a base, a second insulating column fixedly mounted at the top of the base, a static contact pad fixedly mounted at the top of the second insulating column, and a disconnecting link assembly hinged to the static contact pad, and the butt joint assembly is fixedly arranged at the top of the base. According to the invention, the disconnecting link main body is driven by an electric motor or a hand wheel to rotate by taking the hinged part of the disconnecting link main body and the static contact pad as a center shaft, so that the butt joint piece falls into the top of the moving contact pad, the butt joint piece pushes the two sliding frames, the conductive piece and the butt joint toothed plate to move relatively, and the butt joint toothed plate is engaged with racks on two sides of the butt joint piece; the contact area of the butt-joint piece and the butt-joint toothed plate is increased through meshing of the multiple racks, the phenomenon of deformation caused by thermal expansion and cold contraction is avoided, meanwhile, the butt-joint piece and the butt-joint toothed plate are in surface contact all the time, the effective conductive section is guaranteed, local overheating and arc discharge are avoided, and the reliability of circuit on-off is guaranteed.

An electrical connector assembly includes a wire end connector and a board end connector. The board end connector includes a first housing, a slot, and a plurality of conductive terminals. The conductive terminals are disposed in the slot. The wire end connector is detachably connected to the board end connector. The board end connector includes a second housing and a tongue plate. The wire end connector has four sidewalls that define an accommodating space. The tongue plate is disposed in the accommodating space. The tongue plate is connected to a cable assembly, and a surface of the tongue plate is provided with a plurality of contact pads. When the board end connector is docked with the wire end connector, the tongue plate is inserted into the slot, so that the contact pads electrical contact the conductive terminals, and the first housing is inserted into the accommodating space.

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

The invention discloses a device bearing carrier suitable for semiconductor processing and a use method of the device bearing carrier, and relates to the technical field of semiconductor processing equipment.The structure of a wafer adsorption device in the prior art is optimized and improved, and a contact pad assembly with a silica gel hose as a main body is additionally arranged on the wafer adsorption device in the prior art; the contact pad assembly is used for wrapping the adsorption pipe which is directly contacted with the wafer, and the air leakage phenomenon is avoided in a manner of separating an air flow channel; the technical effects that the device bearing carrier suitable for semiconductor processing is high in applicability for wafers of different specifications, relatively low in manufacturing and maintenance cost and relatively high in reliability are achieved.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die, including a plurality of transistors, on the interposer. A carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact is positioned directly over one or more of the top metal structures with the bonding layer between them.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

The invention relates to a packaged integrated circuit having a package substrate with an integrated isolation circuit. A package substrate (202) includes a first metal layer (328, 1906), a second metal layer (324, 1904), an isolation material (314) including the first metal layer (328, 1906) and the second metal layer (324, 1904), an isolation circuit (e.g. 204 in fig. 2), a first plurality of contact pads (350), and a second plurality of contact pads. The isolation circuit (204) includes a first circuit element (306) in the first metal layer (328, 1906) and a second circuit element (308) in the second metal layer, the second circuit element (308) being electrically isolated from the first circuit element (306) by the isolation material (314). The first plurality of contact pads (316, 318) is adapted to be coupled to a first integrated circuit (310) on the package substrate, and includes a first contact pad (318-2) coupled to the first circuit element (306). The second plurality of contact pads (330, 332) is adapted for coupling to a second integrated circuit (320) on the package substrate (202) and includes a second contact pad (332-2) coupled to the second circuit element (308).

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

The invention relates to a clamping device and method for deburring of solar new energy vehicle plate stamping parts, and belongs to the technical field of deburring machining and clamping of solar new energy vehicle plate stamping parts. The global contour scanning mechanism is fixedly mounted on the base and is used for acquiring global contour data of the stamping part; the reference positioning mechanism is fixedly mounted on the mounting plane and is used for initially positioning the stamping part; the multiple cooperative supporting and clamping units are distributed on the mounting plane in an array mode, each cooperative supporting and clamping unit comprises an electric linear actuator and a sensing head fixed to the top end of the electric linear actuator, and a pressure sensor and a micro accelerometer are integrated in each sensing head; the flexible contact pad at the top of the sensing head is made of elastic materials such as nylon or polyurethane, so that the surface of a workpiece can be prevented from being scratched or indented, and supporting force is uniformly transmitted.

An information handling system peripheral display presents visual images with a display panel. A timing controller board has an edge connector that interfaces with a scalar board edge connector when the scalar board couples with slots at posts of the back side. The scalar board couples display cable ports to accept display information from an information handling system and extends the display cable ports out of openings of the midplane. The scalar board communicates visual information to the adjacent timing controller board through the edge connector without the use of a cable. A power board couples with posts and slots adjacent the scalar board to engage a power connector with power pins into a socket of the power board. Power communicates from the power board through the scalar board to the timing controller board and then to a backlight through a pogo pin and contact pad interface.

A method for manufacturing a probe head for the functionality testing of devices under test (DUT) is disclosed. The method includes providing a containment element, arranging a lower guide at a lower face of the containment element which faces toward the devices under test during the test, and arranging an upper guide at an upper face of the containment element. The containment element is interposed between the lower and upper guides which are initially in the shape of a single plate connected to the containment element. The method further includes cutting the lower and / or upper guide thereby defining a plurality of guide portions that are independent and separated from each other, and inserting a plurality of contact elements into respective guide holes formed in the guides. The contact elements are adapted to contact pads of the devices under test. A probe head obtained by the method is also disclosed.

A set of audio headphones operatively coupled to an information handling system includes a digital signal processor (DSP), a headphone power management unit (PMU) to provide power to the DSP, a first ear cup with a first speaker and a second ear cup with a second speaker operatively coupled to each other via a headband, and a mouth privacy cover operatively coupled to the first ear cup at a first end of the mouth privacy cover and operatively coupled to the second ear cup at a second end of the mouth privacy cover, the mouth privacy cover having a microphone built into the mouth privacy cover and operatively coupled to the DSP via a cover receiver with electrical contacts formed on the mouth privacy cover and interfacing with ear cup contact pads formed on at least one of the first ear cup and second ear cup.

A method for fabricating an optoelectronic arrangement is described, comprising the following steps: - Providing a carrier (1) with a top surface (1a) and a bottom surface (1b), - Forming a plurality of contact pads (2) on the carrier (1) on the upper surface (1a), wherein each contact pad (2) is free of ferromagnetic materials, - Forming a shield (3) on the carrier (1), wherein the shield (3) at least partially surrounds each contact pad (2) in the lateral direction (L) and comprises a first ferromagnetic material, - Providing a plurality of optoelectronic components (4), each component comprising a second ferromagnetic material on a side facing the upper surface (1a) of the support (1), - Providing a magnet (5) on the lower surface (1b) of the support (1), wherein the magnet exerts a magnetic force (F), - Bringing the majority of optoelectronic components (4) closer to the upper surface (1a) and - Attaching the majority of optoelectronic components (4) to the carrier (1) on the upper surface (1a). The optoelectronic components (4) may, for example, be micro-LEDs.

A bonded structure is disclosed. The bonded structure can comprise a first semiconductor element having a first contact pad. An interposer can include a second contact pad on a first side of the interposer and a third contact pad and a fourth contact pad on a second side of the interposer opposite the first side, the second contact pad bonded to the first contact pad; a second semiconductor element having a fifth contact pad bonded to the third contact pad and a sixth contact pad bonded to the fourth contact pad. A switching circuitry can be configured to switch between a first electrical connection between the second and third contact pads and a second electrical connection between the second and fourth contact pads.

An implantable probe apparatus includes: a flexible substrate, which includes a first part and a plurality of second parts separated from each other; a probe pad array, which includes a plurality of contact pads that are formed in the first part; a plurality of electrodes, which are formed in respective tail end sections of the plurality of second parts away from the first part; and a plurality of leads, which are formed in the plurality of second parts to electrically connect the plurality of electrodes to the corresponding contact pads respectively; where each second part in the plurality of second parts includes N stages of segments, the Nth stage of segments include the respective tail end sections of the plurality of second parts, a plurality of branches are branched from each segment in the nth stage of segments to serve as the (n+1)th stage of segments.

The utility model provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a substrate which comprises a display area and a peripheral area surrounding the display area, and the peripheral area comprises a binding area located on one side of the display area; the plurality of sub-pixels are located on one side of the substrate and located in the display area; the data lines are located in the display area and extend to the binding area, and the data lines are electrically connected with the sub-pixels and configured to provide data signals for the sub-pixels; the plurality of first contact pads are positioned in the binding area and are connected with the plurality of data lines; the multiple second contact pads are located in the binding area and located on the sides, away from the display area, of the multiple first contact pads, and the multiple first contact pads and the multiple second contact pads are configured to be bound with the driving chip; the plurality of virtual wires are located on the sides, close to the display area, of the plurality of first contact pads and located on at least one side of the plurality of data lines in the first direction. The display effect can be improved.

A power semiconductor device is provided that includes paralleled transistor cells, and a common source, a common drain and a common gate operatively coupled to the paralleled transistor cells. The power semiconductor device also includes a plurality of common gate contact pads operatively coupled to the common gate, and one or more resistors coupled to respective one or more common gate contact pads of the plurality of common gate contact pads. The one or more resistors are also coupled between the respective one or more common gate contact pads and the common gate. The plurality of common gate contact pads provide a selectable resistive decoupling of the common gate by connection of one of the plurality of common gate contact pads.

A card edge connector includes a connector housing having a cavity and holding a contact assembly in the cavity. The contact assembly has a contact positioner holding contacts in a contact array. Each contact includes a mating end, a terminating end, and an intermediate portion between the mating end and the terminating end. The card edge connector includes a connector sleeve coupled to the connector housing movable between a retracted position and an advanced position. The connector sleeve includes an insert received in the cavity having a card slot configured to receive a module circuit board of a pluggable module. The insert includes press anvils configured to engage the intermediate portions of the contacts to move the mating ends of the contacts toward the module circuit board to mate with corresponding contact pads on the module circuit board when moved to the advanced position.

The invention relates to a component package, in particular a laser package, comprising a first semiconductor chip with a first main side and a second main side opposite the first. The first semiconductor chip has a first layer adjacent to the first main side, which comprises a photonically integrated element, wherein the first layer has at least one light input surface, at least one light output surface, and at least one light guide connecting the at least one light input surface and the at least one light output surface. The first semiconductor chip also has a second layer adjacent to the second main side, which comprises an integrated circuit that is decoupled from the photonically integrated element, and a plurality of contact pads on the second main side, which are provided for connection to a carrier, in particular a PCB, or a second semiconductor chip.The component package also comprises a first optoelectronic component, in particular a laser chip, which is designed to emit light of a first wavelength from at least one first emission surface, wherein the at least one first emission surface is arranged opposite the at least one light coupling surface.

An LED includes first / second doped layers with active region(s) therebetween emitting a first wavelength. A wavelength converter on a first LED surface absorbs the first wavelength and emits a second, longer wavelength. A second LED surface is against a substrate surface. A first electrical contact on the first LED surface extends along LED sidewalls, separated from the active region(s) and second doped layer by an insulating layer, connecting the first doped layer to a first contact pad. In some instances, contact pads are on the substrate surface; a second electrical contact extends onto LED sidewalls, connecting the second doped layer to a second contact pad. In some other instances contact pads are on laterally-extending portions of the second doped layer. The insulating layer separates the first contact pad from the second doped layer; a second contact pad is in direct electrical contact with the second doped layer.

The present invention relates to a TSV electrical interconnect structure having a high aspect ratio and method of manufacturing it. In the method, a backside via and a backside contact pad connected to the backside via are formed on a backside of the semiconductor base. A front-side via connected to the backside via is then formed in the front side of the semiconductor base, obtaining a TSV which electrically connects the front side and backside of the semiconductor base that has a thickness greater than or equal to 150 μm. The TSV has an aspect ratio higher than 20, which can meet the requirements of package-level matching. The TSV electrical interconnect structure having a high aspect ratio can be connected to a package substrate or a PCB board through the backside contact pad. A rewiring layer on the front side of the semiconductor base is connected to the front-side via, and the TSV electrical interconnect structure having a high aspect ratio can provide an interconnection through the rewiring layer. Moreover, one or more other semiconductor bases may be stacked on the front side.

A method of making a semiconductor structure includes forming a first contact pad over an interconnect structure. The method further includes forming a second contact pad over the interconnect structure, wherein the second contact pad is electrically separated from the first contact pad. The method further includes depositing a first buffer layer over the interconnect structure, wherein the first buffer layer partially covers the second contact pad, and an edge of the second contact pad extends beyond the first buffer layer.

The invention relates to the technical field of hub spinning, in particular to a hub spinning forming die which comprises an upper die and a lower die. A groove is formed in the inner top wall of the upper die, a spiral sliding groove is formed in the groove, a rotating column is arranged on the inner wall of the groove in a matched mode, a contact pad is installed at the bottom of the rotating column, a torsional spring is installed at the top of the rotating column, and the top end of the torsional spring is fixedly connected with the inner top wall of the groove. The outer wall of the rotating column is provided with a sliding ball, the sliding ball is embedded into the spiral sliding groove, a linkage structure of the spiral sliding groove and the rotating column is arranged in the upper die, automatic rotation and positioning of a hub on a center positioning rod of the lower die are achieved, a hub bolt hole and the positioning column can be accurately aligned without manual intervention, and the positioning accuracy of the hub is improved. The problem that the direction of the hub needs to be manually adjusted through a traditional spinning die is effectively solved, the assembly efficiency is remarkably improved, and the operation intensity is reduced.