4067 results about "Contact pad" patented technology

An analyte monitor includes a sensor, a sensor control unit, and a display unit. The sensor has, for example, a substrate, a recessed channel formed in the substrate, and conductive material disposed in the recessed channel to form a working electrode. The sensor control unit typically has a housing adapted for placement on skin and is adapted to receive a portion of an electrochemical sensor. The sensor control unit also includes two or more conductive contacts disposed on the housing and configured for coupling to two or more contact pads on the sensor. A transmitter is disposed in the housing and coupled to the plurality of conductive contacts for transmitting data obtained using the sensor. The display unit has a receiver for receiving data transmitted by the transmitter of the sensor control unit and a display coupled to the receiver for displaying an indication of a level of an analyte. The analyte monitor may also be part of a drug delivery system to alter the level of the analyte based on the data obtained using the sensor.

An analyte monitor includes a sensor, a sensor control unit, and a display unit. The sensor has, for example, a substrate, a recessed channel formed in the substrate, and conductive material disposed in the recessed channel to form a working electrode. The sensor control unit typically has a housing adapted for placement on skin and is adapted to receive a portion of an electrochemical sensor. The sensor control unit also includes two or more conductive contacts disposed on the housing and configured for coupling to two or more contact pads on the sensor. A transmitter is disposed in the housing and coupled to the plurality of conductive contacts for transmitting data obtained using the sensor. The display unit has a receiver for receiving data transmitted by the transmitter of the sensor control unit and a display coupled to the receiver for displaying an indication of a level of an analyte. The analyte monitor may also be part of a drug delivery system to alter the level of the analyte based on the data obtained using the sensor.

A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.

The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.

An electrical connector is provided for operation in a point-to-point application. The connector includes an insulated housing having first and second card interfaces configured to mate with associated first and second circuit cards. An electrical wafer is held in the housing and configured to operate in a point-to-point architecture. The signal traces end at signal contact pads located proximate to first and second edges, respectively. The signal contact pads receive a unidirectional signal. Each of the signal traces include a break section at an intermediate point along a length thereof to form a disconnect in the signal traces. The connector further includes an active compensation component bridging the break section in the signal traces. The active compensation component compensates the differential signal incoming from the input contact pads for signal degradation and transmits a compensated signal outward to the output contact pads. The active compensation component transmits the signal only in a single direction within the point-to-point architecture.

A process for fabricating a leadless plastic chip carrier includes selectively etching at least a first surface of a leadframe strip to partially define at least a plurality of contact pads and a die attach pad; selectively plating at least one layer of metal on a second surface of the leadframe strip, on an undersurface of at least the plurality of contact pads and the die attach pad; mounting a semiconductor die on the first surface, on the partially defined die attach pad; wire bonding the semiconductor die to ones of the contact pads; encapsulating the wire bonds and the semiconductor die in a molding material such that the molding material covers a first portion of the die attach pad and first portions of the contact pads; selectively etching a second surface of the leadframe strip to define a second portion of the contact pads and a second portion of the die attach pad by etching the second surface with the at least one layer of metal resisting etching; and singulating the leadless plastic chip carrier from the leadframe strip.

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts. By forming a shared contact opening spanning two dice, the backside contact is formed around the die edge and the backside surface area necessary for the contact opening is minimized. The backside contact allows direct placement of the integrated circuit die on contacts within the packaging, such as a ball grid array, eliminating the need for wire bonds. The need for a pad etch through passivation material overlying active devices on the front side of the die is also eliminated, and no mask levels are added for the devices formed on the front side.

A method of interconnecting electronic components by using a plurality of conductive studs on a surface of a first electronic component and a plurality of corresponding conductive vias on the surface of a second electronic component. Camber on the surface of electronic components may be overcome by coating the surface with a dielectric, planarizing the dielectric, and forming conductive vias corresponding to the contact pads thereon. The conductive studs are substantially lead-free and preferably comprise of copper.

The present disclosure provides a substrate support assembly includes a substrate pedestal having an upper surface for receiving and supporting a substrate, a cover plate disposed on the substrate support pedestal, and two or more lift pins movably disposed through the substrate support pedestal and the cover plate. The cover plate includes a disk body having a central opening. The two or more lift pins are self supportive. Each of the two or more lift pins comprises one or more contact pads, and the contact pads of the lift pins extend into to the central opening of the cover plate to receive and support a substrate at an edge region of the substrate.

An electronic semiconductor module component with a semiconductor stack includes semiconductor components arranged in a vertically stacked relationship. A basic semiconductor component includes a lower interposing unit, on which lower external contact pads are arranged. The basic semiconductor component further includes an upper interposing unit, on which upper external contact pads are arranged. The two interposing units are electrically connected to one another via bonding connections disposed at their edge areas. The basic semiconductor component is a compact component on which different, customer-specific semiconductor components can be stacked.

Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.

Methods and apparatuses for improved integrated circuit (IC) packages are described herein. In an aspect, an IC device package includes an IC die having a contact pad, where the contact pad is located on a hotspot of the IC die. The hotspot is thermally coupled to a thermal interconnect member. In an aspect, the package is encapsulated in a mold compound. In a further aspect, a heat spreader is attached to the mold compound, and is thermally coupled to the thermal interconnect member. In another aspect, a thermal interconnect member thermally is coupled between the heat spreader and the substrate.