1365 results about "Contact pad" patented technology

An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

This disclosure generally relates to medical devices that include a sensor transmitter assembly that includes a sensor assembly including a sensor module where a first sensor including a first sensor head having at least one first sensor contact pad is combined with a second sensor including a second sensor head having at least one second sensor contact pad. The sensor transmitter assembly also includes a transmitter assembly positioned on a top of the sensor assembly to form a single unit, the transmitter assembly having at least one transmitter contact disposed on a base of the transmitter assembly, where the first sensor contact pad(s) and the second sensor form a connection path with the transmitter contact(s).

A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a pixel region with a pixel structure, an isolation region with an isolation structure disposed adjacent to the pixel region, and a contact pad region with a pad structure disposed adjacent to the isolation region. The pixel structure includes an epitaxial structure, which includes an embedded portion with a stepped structure disposed in the substrate and a protruding portion extending above a top surface of the substrate. The pixel structure further includes a capping layer disposed on the protruding portion.

The present disclosure describes an intermittency-based analyte sensor and a method for using the intermittency-based analyte sensor. The intermittency-based analyte sensor includes a microcantilever, a substrate, a plurality of electrodes, a contact pad and a microcontroller. The microcantilever has a micromechanical beam having has a fixed end and a free end. The substrate is connected to the fixed end of the micromechanical beam. The plurality of electrodes are configured to connect to a biased source of alternating voltage. The frequency of the alternating voltage is in a frequency range which generates intermittencies in a motion of the free end. The microcontroller monitors a frequency response of the micromechanical beam; compares the frequency response to a calibration curve, and provides an alert that an analyte has deposited on the surface of the micromechanical beam when the frequency response is less than a calibrated frequency response.

A probe card mounted in an of electronic device testing apparatus is described, having a probe head housing a plurality of contact probes, each having a first end portion which abuts onto contact pads of a device under test, a main board and a connected intermediate board which provides a distance spatial transformation between contact pads made on opposite faces thereof. The intermediate board is a space transformer which includes a plurality of modules that are plate-shaped and coplanar, and structurally and functionally independent from each other. Each module has a first face facing towards the probe head and a first plurality of contact pads whereonto respective second end portions of the contact probes abut and an opposite second face facing towards the main board. The second face has a second plurality of contact pads connected to the first plurality of contact pads.

The invention relates to an electrical element having at least one functional region and a contact surface, wherein a connecting element is arranged on the contact surface, wherein the connecting element comprises a stranded wire coated with sintered material, wherein the stranded wire is connected, in particular sintered, to the contact surface by a sintered material. Furthermore, the invention relates to a method for producing the electrical element according to the invention.

Methods for fabricating branched substrates having conductive contact pads and hybrid dielectric bonding surfaces for directly bonding dies and electrically connecting them to the contact pads. A branched substrate can include a main portion and one or more branch portions hybrid bonded to the main portion. Some sections of the branched substrate can be flexible to allow deformable electrical connection between components that are hybrid bonded to different regions of the branched substrate. A flexible branch portion may provide electrical connection between vertically separated layers of two components. The method includes directly bonding a branch portion of the branched substrate to the main portion of the branched substrate via a hybrid bonding interface comprising a conductive interface between contact pads of the main and branch portions and a hybrid bonded dielectric interface between dielectric surfaces of the of the main and branch portions.

A miniaturized paddle card assembly that provides high-speed, high-performance transmission. The paddle card has two or more rows of contact pads for mating with complementary conductors, two or more rows of terminals for cable termination, and alternating dielectric layers and metal layers. The two or more rows of terminals are disposed on respective metal layers. Such a configuration enables conductive traces electrically connecting corresponding contact pads and terminals to be substantially straight, and therefore reduces the lengths of the conductive traces. It is also reduced that the size of the paddle card in both a lateral direction parallel to the rows and a longitudinal direction perpendicular to the lateral direction, without changing the thickness of the paddle card. With the paddle card assembly provided herein, the integrity of the signals transmitted therethrough can be maintained and / or improved at higher speed.

Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.

A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.

The present invention discloses a stretchable wristband high-density electromyography system for thumb micro-gesture recognition, including a high-density electromyography array and a micro wireless acquisition module; the high-density electromyography array includes three layers of flexible materials, the middle layer of flexible material is printed with flexible electrodes and interconnects, the uppermost and lowermost layers of flexible materials can be removed when in use, and the high-density electromyography array is formed with three parts: a soft skin sensing component, a flexible interconnection, and a rigid pluggable contact pad, wherein the soft skin sensing component is used to closely conformally adhere to the wrist skin, and a flexible electrode is arranged on it, which is electrically connected to the rigid pluggable contact pad through a flexible interconnection, and the rigid pluggable contact pad is a plug-and-play FPC interface for connecting to the micro wireless acquisition module. The system can be directly fitted with the wrist, capture high-fidelity surface electromyography of dynamic and fine gestures centered on the thumb, and apply it to human-computer interaction control.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

The utility model relates to a semiconductor structure. The semiconductor structure comprises a substrate; the source electrode, the grid electrode and the drain electrode are stacked on the substrate; the first isolation layer is arranged between the grid electrode and the drain electrode; the second isolation layer is arranged between the first isolation layer and the drain electrode; the channel layer penetrates through the grid electrode, the first isolation layer and the second isolation layer, and the channel layer is arranged on the source electrode; the gate dielectric layer is arranged between the gate and the channel layer; the insulating layer is arranged on the inner side of the channel layer; the contact pad is arranged on the insulating layer; the nitrogen component content of the second isolation layer is greater than the nitrogen component content of the first isolation layer. The second isolation layer protects the first isolation layer in the etching or grinding process, the first isolation layer is prevented from being damaged, the integrity of the semiconductor structure is protected, and the product yield of the semiconductor structure is improved.

A semiconductor structure and a sewed die are provided. The semiconductor structure includes a first semiconductor die including a first contact pad; a second semiconductor die including a second contact pad; and a stitching die over the first semiconductor die and the second semiconductor die and including a third contact pad connected to the first contact pad and a fourth contact pad connected to the second contact pad. The apparatus also includes a cooling structure over the seamed die. The stitched die includes a first surface including a first dielectric layer in direct contact with the cooling structure.

An information handling system main printed circuit board having a CPU couples to a graphics printed circuit board having a GPU with an interposer that includes contacts and wirelines that communicate signals between the separate boards. For example, an interposer couples to an upper and lower side of the main and graphics printed circuit boards to align spring contacts with contact pads of the main and graphics printed circuit so that signals are transferred through the interposer, which also provides a physical structure to define a motherboard with the assembly of the main and graphics printed circuit boards into a single piece.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

The present specification describes a contact probe (20), the contact probe (20) having, in addition to a first end portion (20A) terminating in a contact tip (21A) configured to abut a contact pad (51A) of a device under test (51) and a second end portion (20B) terminating in a contact head (21B) configured to abut a contact pad (61A) of a board (60) of a testing apparatus, a probe body (20C) extending between the first end portion (20A) and the second end portion (20B) along a longitudinal extension axis (HH), the first end portion (20A) comprising a first support portion (22A) interposed between the probe body (20C) and the contact tip (21A). Suitably, the first support (22A) comprises at least one contact pin (24) and one probe length (23) extending parallel to each other along a longitudinal extension axis (HH) and separated by a gap (ZA).

The invention belongs to the technical field of electric power, and discloses an isolating switch which comprises a base, a second insulating column fixedly mounted at the top of the base, a static contact pad fixedly mounted at the top of the second insulating column, and a disconnecting link assembly hinged to the static contact pad, and the butt joint assembly is fixedly arranged at the top of the base. According to the invention, the disconnecting link main body is driven by an electric motor or a hand wheel to rotate by taking the hinged part of the disconnecting link main body and the static contact pad as a center shaft, so that the butt joint piece falls into the top of the moving contact pad, the butt joint piece pushes the two sliding frames, the conductive piece and the butt joint toothed plate to move relatively, and the butt joint toothed plate is engaged with racks on two sides of the butt joint piece; the contact area of the butt-joint piece and the butt-joint toothed plate is increased through meshing of the multiple racks, the phenomenon of deformation caused by thermal expansion and cold contraction is avoided, meanwhile, the butt-joint piece and the butt-joint toothed plate are in surface contact all the time, the effective conductive section is guaranteed, local overheating and arc discharge are avoided, and the reliability of circuit on-off is guaranteed.

An electrical connector assembly includes a wire end connector and a board end connector. The board end connector includes a first housing, a slot, and a plurality of conductive terminals. The conductive terminals are disposed in the slot. The wire end connector is detachably connected to the board end connector. The board end connector includes a second housing and a tongue plate. The wire end connector has four sidewalls that define an accommodating space. The tongue plate is disposed in the accommodating space. The tongue plate is connected to a cable assembly, and a surface of the tongue plate is provided with a plurality of contact pads. When the board end connector is docked with the wire end connector, the tongue plate is inserted into the slot, so that the contact pads electrical contact the conductive terminals, and the first housing is inserted into the accommodating space.

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

The embodiment of the invention provides a preparation method of a semiconductor structure, and the method is characterized in that the method comprises the steps: providing a first wafer, the first wafer comprises a plurality of first chips, and first cutting channels are disposed among the plurality of first chips; a first dielectric layer, a first groove and a second groove are formed on the first surface of the first wafer, the first groove and the second groove are located in the first dielectric layer, a first alignment mark is formed in the first groove, a first contact pad is formed in the second groove, and the first contact pad is connected with the first chip; providing a plurality of second chip structures, and correspondingly bonding and connecting the second chip structures with the first chips on the side, provided with the first alignment marks, of the first wafer to form the first semiconductor structure; a second alignment mark corresponding to the first alignment mark is formed on the to-be-bonded structure; and bonding the first semiconductor structure with the to-be-bonded structure based on alignment operation between the first alignment mark and the second alignment mark.

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

The invention discloses a device bearing carrier suitable for semiconductor processing and a use method of the device bearing carrier, and relates to the technical field of semiconductor processing equipment.The structure of a wafer adsorption device in the prior art is optimized and improved, and a contact pad assembly with a silica gel hose as a main body is additionally arranged on the wafer adsorption device in the prior art; the contact pad assembly is used for wrapping the adsorption pipe which is directly contacted with the wafer, and the air leakage phenomenon is avoided in a manner of separating an air flow channel; the technical effects that the device bearing carrier suitable for semiconductor processing is high in applicability for wafers of different specifications, relatively low in manufacturing and maintenance cost and relatively high in reliability are achieved.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die, including a plurality of transistors, on the interposer. A carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact is positioned directly over one or more of the top metal structures with the bonding layer between them.

Disclosed herein is a tag suitable for use with pets and other animals. The tag may be a glass tag that includes an antenna, a first circuit block and a second circuit block. The antenna has a common core having a coil wound around the core. The coil interconnects a first antenna pad, a second antenna pad and a third antenna pad; a first circuit block having a first and a second contact pad, the first and second antenna pads interconnected to the first and second contact pads respectively. The second circuit block has a third and a fourth contact pads. The second and third antenna pads interconnected to the third and fourth contact pads respectively. The first circuit block may be an RFID integrated circuit and the second circuit block may be an NFC IC.

An integrated circuit package includes a substrate, a semiconductor interposer on the substrate, and an integrated circuit die on the interposer, the integrated circuit die including a plurality of transistors. The carrier die is coupled to a top surface of the integrated circuit die. The integrated circuit die includes a plurality of top metal structures at a top surface of the integrated circuit die. The carrier die includes a plurality of dummy contact pads. The carrier die is bonded to the integrated circuit die by a bonding layer such that each dummy contact pad is directly over one or more of the top metal structures with the bonding layer between the dummy contact pads and the top metal structures. Embodiments of the present disclosure also relate to a method of forming an integrated circuit package.

The invention relates to a packaged integrated circuit having a package substrate with an integrated isolation circuit. A package substrate (202) includes a first metal layer (328, 1906), a second metal layer (324, 1904), an isolation material (314) including the first metal layer (328, 1906) and the second metal layer (324, 1904), an isolation circuit (e.g. 204 in fig. 2), a first plurality of contact pads (350), and a second plurality of contact pads. The isolation circuit (204) includes a first circuit element (306) in the first metal layer (328, 1906) and a second circuit element (308) in the second metal layer, the second circuit element (308) being electrically isolated from the first circuit element (306) by the isolation material (314). The first plurality of contact pads (316, 318) is adapted to be coupled to a first integrated circuit (310) on the package substrate, and includes a first contact pad (318-2) coupled to the first circuit element (306). The second plurality of contact pads (330, 332) is adapted for coupling to a second integrated circuit (320) on the package substrate (202) and includes a second contact pad (332-2) coupled to the second circuit element (308).

The invention provides semiconductor device thermal resistance measuring equipment, which is applied to the technical field of electrical variable measurement and comprises a case, a workbench fixed at the top of the case, a constant-temperature base arranged in the middle of the workbench, a rack arranged on one side of the workbench and erected above the constant-temperature base, a thermal resistance detector matched with the rack, and a temperature sensor arranged on the thermal resistance detector. The top of the rack is provided with a pressing mechanism which can press and abut against the semiconductor device to be tested towards the upper end face of the constant-temperature base. The middle part of the upper end surface of the constant-temperature base is provided with a flexible heat-conducting contact pad used for self-adapting to the shape of a semiconductor device to be tested, and the flexible heat-conducting contact pad is internally provided with a temperature control assembly; and an environment simulation mechanism is matched on the pressing mechanism. The thermal resistance testing device has a high-adaptability and high-precision thermal resistance testing structure, can adapt to semiconductor devices in various shapes for testing, can simulate the actual application environment of the semiconductor devices, can provide reliable data support for thermal management design of the semiconductor devices, and is good in overall use effect.

A metal grid within a trench isolation structure on the back side of an image sensor is coupled to a contact pad so that a voltage on the metal grid is continuously variable with a voltage on the contact pad. One or more conductive structures directly couple the metal grid to a contact pad. The conductive structures may bypass a front side of the image sensor. A bias voltage on the metal grid may be varied through the contact pad whereby a trade-off between reducing cross-talk and increasing quantum efficiency may be adjusted dynamically in accordance with the application of the image sensor, its environment of use, or its mode of operation.

The invention relates to a clamping device and method for deburring of solar new energy vehicle plate stamping parts, and belongs to the technical field of deburring machining and clamping of solar new energy vehicle plate stamping parts. The global contour scanning mechanism is fixedly mounted on the base and is used for acquiring global contour data of the stamping part; the reference positioning mechanism is fixedly mounted on the mounting plane and is used for initially positioning the stamping part; the multiple cooperative supporting and clamping units are distributed on the mounting plane in an array mode, each cooperative supporting and clamping unit comprises an electric linear actuator and a sensing head fixed to the top end of the electric linear actuator, and a pressure sensor and a micro accelerometer are integrated in each sensing head; the flexible contact pad at the top of the sensing head is made of elastic materials such as nylon or polyurethane, so that the surface of a workpiece can be prevented from being scratched or indented, and supporting force is uniformly transmitted.