1060 results about "Solder ball" patented technology

The invention relates to the field of chip packaging testing, in particular to a BGA chip packaging testing method. The method comprises the following steps: carrying out full-flow thermal imaging scanning on a BGA chip packaging process, carrying out space temperature gradient diffusion distribution analysis, and constructing a temperature diffusion distribution map of each region; according to the probe array, acoustic scanning is carried out on the BGA chip solder ball contact surface, abnormal frequency detection is carried out, and abnormal acoustic nodes are marked; performing transient temperature mutation detection and potential packaging defect positioning analysis on the temperature diffusion distribution map based on abnormal acoustic nodes, and extracting a potential packaging defect area; and carrying out multi-threshold micro-vibration excitation on the potential packaging defect area, carrying out comprehensive evaluation on the reliability of the defect area structure, and generating a reliability evaluation report of the solder ball contact surface structure. According to the invention, accurate packaging test failure prediction is realized, packaging process parameters are optimized, and chip packaging quality and stability are improved.

The invention provides a 2.5 D substrate packaging method and packaging structure, and relates to the technical field of semiconductor packaging. The 2.5 D substrate packaging method comprises the following steps: providing a carrier; wherein the carrier is provided with a flat part and a boss part; the boss part protrudes out of the flat part. Forming a first wiring layer on the boss part; forming a second wiring layer on the flat part; the first wiring layer and the second wiring layer are independent from each other. Mounting a first chip; the first chip comprises a plurality of first electric connection parts, at least one first electric connection part is electrically connected with the first wiring layer, and at least one first electric connection part is electrically connected with the second wiring layer; the length of the first electric connection part connected with the first wiring layer is smaller than that of the first electric connection part connected with the second wiring layer. Removing the carrier; and forming a solder ball on one side, far away from the first chip, of the second wiring layer. The inductance effect and the parasitic effect are reduced, the transmission path is shortened, the transmission efficiency is improved, and the chip integration level and the product performance are improved.

The invention relates to the technical field of high-end chips, and discloses a packaging defect detection method and system for an industrial solid state disk, and the method comprises the steps: collecting multi-source heterogeneous detection data, and extracting the multi-dimensional defect features of a packaging body; packaging process parameters and material attributes of the industrial solid state disk are input into the virtual mirror image body, and a defect sensitivity distribution diagram of the packaging body is generated; identifying a defect expansion path and a defect type of the packaging body; based on the process weak link, the defect expansion path and the defect type, generating a grading defect detection instruction of the packaging body; setting a personalized defect detection mode of the packaging body in combination with the number of NAND stacked layers, the solder ball spacing and the defect type; and outputting a defect detection result of the packaging body through the virtual mirror image body by utilizing a grading defect detection instruction and a personalized defect detection mode. According to the method, the accuracy and credibility of an industrial solid state disk packaging defect detection result can be effectively improved.

The invention relates to the technical field of semiconductor chip packaging, in particular to a photoelectric co-packaging optical coupling passive alignment packaging structure and method. According to the invention, high-precision automatic alignment of the grating coupler in the optical chip and the through hole of the adapter plate is realized by using the solder ball tension effect in the flip reflow soldering process of the optical chip, and a stable optical limiting structure is formed. The passive coupling of the optical elements (such as bare optical fibers, optical fiber arrays, reflectors and the like) and the grating coupler is realized by placing the optical elements with matched sizes in the via holes of the adapter plate and completing refractive index matching and structure fixing by using curing glue. The whole process does not need additional active alignment equipment, is the same as a traditional chip packaging process, has the advantages of being simple in process, low in cost and high in packaging efficiency, and is a key packaging technology of a photoelectric co-packaging system in the future.

The invention relates to the technical field of chip testing, in particular to chip internal signal transmission impedance matching testing equipment which comprises a vector network analysis module and a testing socket module, the testing socket module is internally provided with an inert gas cavity and a cylindrical cavity groove, the inert gas cavity and the cylindrical cavity groove are communicated with each other, and the inert gas cavity and the cylindrical cavity groove are communicated with each other. Gas in the inert gas cavity is inert gas; according to the impedance matching test equipment for signal transmission in the chip, the probe part is actively controlled to retract during test, and the probe part is controlled to eject out to establish test connection after the chip is placed in place, so that hard friction or collision between a solder ball contact of the chip and the probe part can be effectively avoided.

The invention relates to the field of packaging substrates, in particular to a modular stacked substrate and a manufacturing method thereof. Comprising a first sub-packaging substrate and a second sub-packaging substrate; the first sub-packaging substrate and the second sub-packaging substrate are connected through a solder ball, and filling glue is arranged between the first sub-packaging substrate and the second sub-packaging substrate; the first sub-packaging substrate comprises a glass core plate, a circuit layer is arranged between the glass core plate and the surface of the first sub-packaging substrate, and the circuit layer is connected through a first metal column; the first sub-packaging substrate comprises a second metal column, the second metal column penetrates through the glass core plate to be connected with the circuit layer, and printing ink is injected into the second metal column. The yield of large-size substrates can be remarkably improved, and meanwhile the manufacturing cost is reduced. The shrinkage phenomenon caused by the state change after the material is pressed, heated and cooled in the pressing process is avoided, and the overall warping is avoided. The method can be applied to packaging of 2.5 D chips, and the technological level of large-size chips is greatly improved.

The invention provides an LPDDR packaging method, which can effectively reduce the packaging thickness and can effectively improve the heat dissipation capability of a product. The method is characterized in that redistributed solder balls are led out from each stacked LPDDR chip through vertical routing, then the whole stacked assembly is turned over, and an EMI plating layer is plated on the periphery of a plastic package body of the stacked assembly.

The invention provides a solder ball simulation analysis method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: after creating a coaxial body, a signal solder ball model and a signal backflow plane, connecting the coaxial body with the signal solder ball model according to a preset contact area, and adjusting the effective dielectric constant of the coaxial body, the method comprises the following steps of: connecting a simulation signal port with a coaxial body to enable impedance of the coaxial body to be matched with target impedance of a test signal, further, respectively connecting the simulation signal port with the coaxial body and a signal backflow plane, outputting the test signal through the simulation signal port, and respectively acquiring test impedance of a signal solder ball model in an air environment and a target cold liquid environment; finally, the signal solder ball model is corrected according to the test impedance, simulation analysis of the solder ball in different operation environments can be achieved through the method, a reference basis is provided for correction of the signal solder ball model, and the solder ball can meet the performance requirements in the different operation environments.

The invention discloses a microwave and millimeter wave low-cost compact radio frequency digital integrated front-end module, and relates to the technical field of microwave and millimeter wave devices. The front-end module comprises a substrate layer, a preceding-stage compound bare chip and a silicon-based chip group are arranged on the upper surface of the substrate layer, a first group of BGA solder balls located on the lower surface of the substrate layer are connected with a first metal cushion block on one side of the preceding-stage compound bare chip through a first quasi-coaxial structure penetrating through the substrate layer up and down, and a second group of BGA solder balls located on the lower surface of the substrate layer are connected with a second metal cushion block on one side of the preceding-stage compound bare chip through a second quasi-coaxial structure penetrating through the substrate layer up and down. The second metal cushion block is connected with a BGA solder ball on one side of the BGA packaging chip through a second similar coaxial structure vertically penetrating through the substrate layer, and the BGA packaging chip is connected with a third metal cushion block on one side of the silicon-based chip set through a third similar coaxial structure vertically penetrating through the substrate layer. And the fourth metal cushion block is connected with a second group of BGA solder balls positioned on the lower surface of the substrate layer through a fourth quasi-coaxial structure which vertically penetrates through the substrate layer. The front-end module can realize extremely low-loss transmission, and the interconnection flexibility is higher.

The invention relates to the technical field of welding, in particular to a solder ball preparation device for soft soldering, which comprises a ball storage tank with a mounting seat higher than a solder ball separation device, a solder ball conveying shaft is hermetically and slidably connected into the ball storage tank, and a solder ball conveying channel is formed in the center of the solder ball conveying shaft. The lower end of the solder ball conveying shaft is fixedly and hermetically connected with a ball falling hose, one end, far away from the solder ball conveying shaft, of the ball falling hose is fixedly and hermetically connected with an air pipe connecting sleeve, and the air pipe connecting sleeve is fixedly connected to the solder ball separating device and communicated with a ball storage groove of the solder ball separating device. Through the synergistic effect of multiple structures, automatic and continuous supply of the solder balls is finally achieved, the problem that the storage capacity of a ball storage bin in an existing solder ball separation device is limited is solved, high efficiency and stability of feeding of the solder balls large in size in the long-time welding process are guaranteed, and the requirement of soft soldering for solder ball supply is met.

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

Provided are a solder alloy, a solder ball, a preformed solder, a solder joint, and a circuit, which are excellent in wettability and shear strength, suitable in failure mode, capable of suppressing the growth of an intermetallic compound at a bonding interface even after multiple reflow soldering, excellent in drop impact resistance, and suitable in the shape of a bump. The solder alloy has an alloy composition comprising, in mass%, 0.10 to 3.00% of Ag, 0.80 to 6.00% of Cu, 0.08 to 0.60% of Ni, 0.0010 to 0.0150% of Ge, and the balance of Sn. It is preferable that the alloy composition further contains 0.1% or less of at least one of Bi, Sb, In, Zn, Ga, Mn, Cr, Co, Si, Ti, and rare earths in total.

The invention discloses an on-chip antenna and pulse source integrated device and method based on heterogeneous material 3D packaging integration, and relates to the technical field of antennas. The upper surface of the base substrate is used for installing a radiation structure; the upper surface of the photoconductive substrate is used for mounting an excitation structure; the interconnection structure is used for realizing electric connection between the radiation structure and the excitation structure, and the through hole is formed in the base substrate through a TSV or TGV process and penetrates through the whole base substrate; the conductive filling material is filled in the through hole; the solder balls are arranged on the lower surface of the through hole of the base substrate and are made of conductive weld-aid metal; the GSG electrode is arranged on the upper surface of the photoconductive substrate; the device adopts a 3D packaging technology, integrates a radiation structure and an excitation structure on the same chip, breaks through the frequency limitation of 110GHz of a traditional electrical pulse source, has the advantages of high-frequency performance, low dielectric loss, high integration level and the like, and is suitable for the fields of wireless communication, radar ranging systems and the like.

A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

The invention provides an improved YOLOv10-based solder ball defect detection method for a BGA packaged chip, and the method comprises the steps: collecting a solder ball image of the BGA packaged chip, carrying out the morphological preprocessing, and carrying out the analysis and classification of defects; carrying out defect generation on solder ball burr defects with less data; performing similarity measurement on the generated defects and the real defects, and selecting defect data with relatively high similarity to construct a pre-training data set; a YOLOv10 deep learning network is improved, a C2f module in the network is improved, an up-sampling module is replaced with a lightweight dynamic up-sampling operator DySample, an original loss function is replaced with a Focal-EIoU loss function, the improved network is used for pre-training, and a defect detection model is obtained; performing real-time defect detection on the solder ball of the BGA packaging chip by using the defect detection model to obtain defect information; according to the invention, the detection precision and speed of the solder ball defect of the BGA packaging chip are effectively improved.

The invention provides a method and a device for efficiently preparing gold-tin solder balls with uniform and controllable particle size, the device comprises a vacuum system, a liquid drop injection system, a particle collector, an image acquisition system and a liquid level control system, and the liquid drop injection system adopts a crucible fixed in a vacuum chamber as a container for containing gold-tin melt; a micropore piece provided with a round micropore is fixed to the bottom of a crucible and communicated with an inner cavity of the crucible, piezoelectric ceramics arranged at the top of the crucible drive a transmission rod in the crucible to vibrate and apply pressure to gold-tin melt, the gold-tin melt is jetted into liquid drops through the micropore, the liquid drops are rapidly solidified to form gold-tin soldering balls with the uniform particle size after dropping, and the gold-tin soldering balls are collected by a particle collector. And a gap between the outer edge of the bottom of the transmission rod and the micropore at the bottom of the crucible is 0.10-0.35 mm. The invention further discloses a method for preparing the gold-tin solder ball through the device, the gold-tin solder ball is successfully prepared through a pulse micropore jetting method, and the preparation efficiency and the preparation precision have leap-type progress.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

A method for normalizing the solder interconnects (e.g., normalizing the height of the solder ball interconnects) in a circuit package module (e.g., dual-sided mold grid array package module) after removal from a test board includes receiving in a fixture the circuit package module upside down and removably coupling a stencil to the fixture and over the circuit package module. The stencil has a pattern of apertures that coincides with the pattern of solder interconnects of the circuit package module. The method also includes applying solder paste over the stencil to pass through the apertures to add solder paste to the solder interconnects. The method also includes removing the stencil from over the fixture, and removing the circuit package module from the fixture. The circuit package module can be heated to reflow the solder interconnects with the added solder paste.

The invention provides a circuit board assembly and electronic equipment. The circuit board assembly comprises a circuit board, a chip module and a heat dissipation piece, the chip module and the heat dissipation piece are stacked and arranged on the circuit board, the chip module and the circuit board are conducted through a solder ball, and the heat dissipation piece is in heat conduction connection with the chip module; the circuit board assembly further comprises heat-conducting glue and a heat-conducting piece, in the plane direction of the circuit board, a part of the heat-conducting glue is filled in the gap between the chip module and the circuit board and makes contact with the solder balls, the other part of the heat-conducting glue is located outside the chip module, and the heat-conducting piece extends in the thickness direction of the circuit board and makes contact with the solder balls. The heat-conducting piece is used for being in heat-conducting connection with the heat-dissipating piece and the other part of the heat-conducting glue. According to the circuit board assembly, through contact between the solder balls and the heat-conducting glue and contact between the heat-conducting glue and the heat-conducting piece, heat-conducting connection between the chip module and the heat-dissipating piece is achieved, thermal resistance between the chip module and the heat-dissipating piece is reduced through the heat-conducting piece and the heat-conducting glue, and therefore the heat-dissipating efficiency of the circuit board assembly is improved.

The invention discloses a correction method and system of a double-station solder ball welding machine, and belongs to the technical field of welding equipment correction, and the correction method comprises the following steps: arranging various sensors on the double-station solder ball welding machine, and collecting welding data; preprocessing the collected welding data to obtain welding processing data; performing feature extraction on the welding processing data through a feature layer fusion method to obtain a welding feature vector; building a correction prediction model based on a support vector machine, and predicting the welding feature vector obtained in real time to obtain a prediction result; deviation detection judgment is conducted on abnormal data in the prediction result, and welding data needing to be corrected are obtained; and based on the welding data needing to be corrected, corresponding correction measures are taken for the welding data with deviation in each station.

The invention discloses a droplet uniformity on-line detection and alarm method and application. The method comprises the following steps: acquiring an original image through an industrial camera, carrying out image type conversion on the original image to obtain a droplet grayscale image, setting different corrosion values according to different background pollution conditions to carry out morphological operation on a solder ball image, and carrying out online detection on the droplet uniformity according to a preset connectivity value. Eliminating a part smaller than a connected value to obtain a binary image with only the microdroplet, extracting contour coordinate information of the microdroplet by using a Canny algorithm, performing first correction on the contour coordinate information by using open operation, and then performing second coordinate information correction by using a least square ellipse fitting algorithm to obtain a binary image with the microdroplet; and finally, the particle size and the roundness of the microdroplet are calculated according to the contour coordinate information of the microdroplet, and when the software detects that the threshold values of the particle size and the roundness of the microdroplet are lower than a preset alarm threshold value, the alarm gives an alarm to remind an operator to adjust parameters of equipment for preparing the microdroplet in time, so that the final product quality and the production efficiency are improved.

The invention relates to the technical field of integrated circuits, in particular to a soldering flux dipping method and a soldering flux dipping machine table. A soldering flux dipping method comprises the steps that a soldering flux dipping machine table is provided, a groove is formed in the soldering flux dipping machine table, and the groove is used for containing soldering flux; a soldering flux is put into the groove; a target chip is provided, the first surface of the target chip is provided with a solder ball, and the solder ball has a first height; and the solder ball of the target chip is immersed in the groove to dip the soldering flux, so that the soldering flux on the surface of the solder ball has a second height, and the ratio of the second height to the first height is 20%-35%. In the application, the ratio of the second height to the first height is set to be 20%-35%, so that the capillary action between the soldering flux and the solder ball is reduced, the probability that the soldering flux remains between the two welding parts to be welded is further improved, the binding force between the two welding parts to be welded is increased, and the probability that the soldering flux remains between the two welding parts to be welded in the transportation process is reduced. And the probability of deviation of the chip product is reduced.

The invention provides a manufacturing method of a 3D packaging structure of an optical engine module and a CPO module, and relates to the technical field of semiconductor packaging. Firstly, an optical chip wafer is provided, then an electric chip and an optical port protection piece are mounted on the basis of the surface of the optical chip wafer, plastic packaging is carried out on the basis of the upper portion of the optical chip wafer, the electric chip and the optical port protection piece are wrapped by plastic packaging materials, and then the plastic packaging materials are thinned until the optical chip and the optical port protection piece are exposed; the method comprises the following steps: manufacturing a TSV through hole on the basis of an optical chip wafer, thinning the bottom surface of the optical chip wafer until the TSV through hole is exposed, manufacturing an RDL layer and a solder ball on the basis of the bottom surface of the optical chip wafer, connecting the RDL layer with the TSV through hole, removing an optical port protection piece, and finally cutting the optical chip wafer to form a single optical engine module. According to the scheme provided by the invention, the optical chip is prevented from being damaged in the packaging process, and the design flexibility of the optical port is improved.

The utility model relates to a solder ball flattening device used for semiconductor packaging, comprising a lifting platen, the upper surface of the lifting platen is a smooth horizontal plane, and two sides of the lifting platen are respectively and symmetrically provided with ear parts; the heating device is fixedly arranged below the lifting table plate, and the heating device is used for heating the lifting table plate; and the two lead screw pairs are arranged on the two sides of the lifting table plate correspondingly, the lead screw pairs are located below the lug parts, the lead screw pairs can lift the height of the lifting table plate in the vertical direction through a driving motor, and the driving motor is fixedly arranged on the working table top.

The invention discloses a solder composition alloy and a solder ball, and belongs to the technical field of alloys. The composition alloy of the solder provided by the embodiment of the invention comprises silver, copper, nickel, germanium, bismuth and tin, and by adjusting the content of silver, the alloy can have good heat cycle resistance and drop impact resistance; by adjusting the content of nickel, the thickness of a boundary metal part of a welding spot formed by the alloy can be effectively reduced, the situation that the welding spot is broken from the boundary metal part during a ball pushing test is avoided, and then the heat cycle resistance and the falling impact resistance of the alloy are improved; by adjusting the content of bismuth, the tensile strength and yield strength of the alloy can be improved, then the heat-resistant cycle performance of the alloy is improved, meanwhile, the melting point of the alloy is reduced, and energy needed in the welding process is reduced. Therefore, through the synergistic effect of all the components, the alloy can have good heat cycle resistance and falling impact resistance at the same time, and the performance of the alloy in other aspects can be improved.

A solder alloy consisting of Ag: 3.1 to 4.0% by mass, Cu: 0.6 to 0.8% by mass, Bi: 1.5 to 5.5% by mass, Sb: 1.0 to 6.0% by mass, Co: 0.001 to 0.030% by mass, Fe: 0.02 to 0.05% by mass, As: 0.002 to 0.250% by mass, and a balance Sn.

Provided is a board-level semiconductor package including: board pads that are separate from one another; a package substrate including substrate pads that are separate from one another and face the board pads; and connection balls between the board pads and the package substrate, wherein the connection balls connect the board pads to the substrate pads, wherein the connection balls include: metal core solder balls; and core-free solder balls, wherein the substrate pads include first and second substrate pads, and wherein the metal core solder balls are on the first substrate pads, the core-free solder balls are on the second substrate pads, and a diameter of a first second substrate pad among the second substrate pads is different a diameter of a second substrate pad from among the second substrate pads.

The present invention provides a stacked heat dissipation packaging structure and a preparation method thereof, relating to the field of chip packaging technology. The stacked heat dissipation packaging structure includes a substrate, a first chip, a heat dissipation adhesive layer, a first heat dissipation fin, a second heat dissipation fin, a plastic package, and solder balls. The first chip is mounted on the substrate, and a chip groove is provided on a non-functional surface of the first chip; the heat dissipation adhesive layer is provided in the chip groove; the first heat dissipation fin and the second heat dissipation fin are both provided in the chip groove, and the second heat dissipation fin is bent and extended onto the first heat dissipation fin, with a heat dissipation gap formed between the second heat dissipation fin and the first heat dissipation fin. Compared with the prior art, the present invention arranges both the first heat dissipation fin and the second heat dissipation fin on the heat dissipation adhesive layer, which can greatly increase the heat dissipation area, thereby improving the heat dissipation effect and heat dissipation performance. It can also effectively reduce the stacking height, which helps to achieve miniaturization of the packaging structure.

The invention provides a low-coupling rewiring packaging structure and a preparation method thereof, and relates to the chip packaging technology, the packaging structure comprises a chip, a plastic package body, a dielectric layer, a reconfiguration circuit layer and solder balls, and the front surface of the chip is provided with a metal layer; the plastic package body wraps the periphery of the chip; the dielectric layer is arranged on the surface of the metal layer and covers the plastic package body; the reconstruction line layer is arranged in the dielectric layer and is connected with the metal layer; the solder ball is arranged on one side, far away from the chip, of the dielectric layer and is connected with the reconfiguration circuit layer; wherein the metal layer is etched to form an avoiding gap, the avoiding gap penetrates through the metal layer, and the projection of the reconstruction circuit layer on the front surface of the chip is at least partially overlapped with the avoiding gap. Compared with the prior art, by forming the avoiding gap overlapped with the reconstruction circuit layer on the metal layer, the overlapping area of the reconstruction circuit layer and the metal layer can be greatly reduced, the coupling effect with the RDL is reduced, and the return loss result of a high-frequency signal is greatly improved.

The invention discloses a novel ball mounting method without a steel mesh and a substrate structure, and the method employs a pyrolysis film and laser drilling technology to replace a traditional steel mesh. The method comprises the core steps of pasting a pyrolysis film and a PET protective film, drilling a blind hole to a bonding pad through laser, cleaning glue residues through high-pressure water, blade-coating solder paste containing soldering flux, stripping the PET film, forming solder balls through reflow soldering, cleaning the soldering flux and flattening the solder balls. A steel mesh is replaced by the pyrolysis film and laser drilling, use of the steel mesh is eliminated, use of the steel mesh and customization of the steel mesh are not needed, the cost is saved, and the manufacturing period is shortened. The pyrolysis film is pasted on the substrate, the pattern is manufactured in a laser drilling mode, the expansion and contraction are completely consistent with those of the substrate, and the risk of solder ball deviation is reduced; in addition, the method does not need to change the design of the substrate, the ball mounting pattern is directly manufactured according to customer information, drilling is carried out, the process is simple, meanwhile, different types of substrates can be compatible, and compatibility is high.