1324 results about "Solder ball" patented technology

The invention relates to the field of chip packaging testing, in particular to a BGA chip packaging testing method. The method comprises the following steps: carrying out full-flow thermal imaging scanning on a BGA chip packaging process, carrying out space temperature gradient diffusion distribution analysis, and constructing a temperature diffusion distribution map of each region; according to the probe array, acoustic scanning is carried out on the BGA chip solder ball contact surface, abnormal frequency detection is carried out, and abnormal acoustic nodes are marked; performing transient temperature mutation detection and potential packaging defect positioning analysis on the temperature diffusion distribution map based on abnormal acoustic nodes, and extracting a potential packaging defect area; and carrying out multi-threshold micro-vibration excitation on the potential packaging defect area, carrying out comprehensive evaluation on the reliability of the defect area structure, and generating a reliability evaluation report of the solder ball contact surface structure. According to the invention, accurate packaging test failure prediction is realized, packaging process parameters are optimized, and chip packaging quality and stability are improved.

The invention provides a 2.5 D substrate packaging method and packaging structure, and relates to the technical field of semiconductor packaging. The 2.5 D substrate packaging method comprises the following steps: providing a carrier; wherein the carrier is provided with a flat part and a boss part; the boss part protrudes out of the flat part. Forming a first wiring layer on the boss part; forming a second wiring layer on the flat part; the first wiring layer and the second wiring layer are independent from each other. Mounting a first chip; the first chip comprises a plurality of first electric connection parts, at least one first electric connection part is electrically connected with the first wiring layer, and at least one first electric connection part is electrically connected with the second wiring layer; the length of the first electric connection part connected with the first wiring layer is smaller than that of the first electric connection part connected with the second wiring layer. Removing the carrier; and forming a solder ball on one side, far away from the first chip, of the second wiring layer. The inductance effect and the parasitic effect are reduced, the transmission path is shortened, the transmission efficiency is improved, and the chip integration level and the product performance are improved.

The invention relates to the technical field of high-end chips, and discloses a packaging defect detection method and system for an industrial solid state disk, and the method comprises the steps: collecting multi-source heterogeneous detection data, and extracting the multi-dimensional defect features of a packaging body; packaging process parameters and material attributes of the industrial solid state disk are input into the virtual mirror image body, and a defect sensitivity distribution diagram of the packaging body is generated; identifying a defect expansion path and a defect type of the packaging body; based on the process weak link, the defect expansion path and the defect type, generating a grading defect detection instruction of the packaging body; setting a personalized defect detection mode of the packaging body in combination with the number of NAND stacked layers, the solder ball spacing and the defect type; and outputting a defect detection result of the packaging body through the virtual mirror image body by utilizing a grading defect detection instruction and a personalized defect detection mode. According to the method, the accuracy and credibility of an industrial solid state disk packaging defect detection result can be effectively improved.

The invention belongs to the technical field of radio frequency microsystem integration, and particularly relates to a heat dissipation structure based on a three-dimensional heterogeneous integrated radio frequency microsystem, the heat dissipation structure comprises a packaging box and a heat dissipation assembly installed on the side wall of the packaging box, the heat dissipation assembly comprises a U-shaped air pipe and a fan, a plurality of packaging modules are installed in the packaging box, and the U-shaped air pipe is connected with the fan. Each packaging module is installed between two ports of the U-shaped air pipe, the multiple packaging modules are connected through the BGA solder balls, the fans are installed in the two ports of the U-shaped air pipe, and the sealing cover is packaged on the top of the packaging box. Each packaging module is installed between the two ports of the U-shaped air pipe, when each module in the packaging box works, the fan in the U-shaped air pipe drives gas at the top of the packaging module to circulate towards the bottom of the packaging module, then gas flowing among the packaging modules is accelerated, and the packaging efficiency is improved under the condition that it is guaranteed that the packaging box is sealed. And the effect of uniform heat dissipation of each packaging module is realized.

Disclosed examples provide methods that include forming a conductive structure at least partially above a conductive feature of a wafer, attaching a solder ball structure to a side of the conductive structure, and thereafter forming a repassivation layer on a side of the wafer proximate the side of the conductive structure. Further examples provide microelectronic devices and integrated circuits that include a conductive structure coupled with a conductive feature of a metallization structure, a solder ball structure connected to the conductive structure, and a printed repassivation layer disposed on the side of the metallization structure proximate a side of the conductive structure.

The invention relates to the technical field of semiconductor devices, in particular to a highly-integrated 2.5 D packaging structure and method, and the structure comprises a supporting frame structure, a carrier plate, and an auxiliary structure. A chip is arranged on the front surface of the carrier plate, and a bonding wire is arranged between the chip and the carrier plate; a component is arranged on the back surface of the carrier plate, the carrier plate is arranged in an inner cavity of the supporting frame structure, a solder ball is arranged at the bottom end of the supporting frame structure, and an auxiliary structure is arranged in the supporting frame structure; surface mounting is mainly carried out on the back surface of the carrier plate, so that functional devices can be concentrated on one carrier plate to work, the space utilization rate is improved, and more components are added; and moreover, the auxiliary structure has an auxiliary heat dissipation effect on the packaging structure, and convenience is provided for the installation work of the packaging structure through the connecting assembly arranged in the auxiliary structure.

The invention relates to a three-dimensional stacked high-power multi-channel dual-polarization airtight packaging T / R assembly, which comprises a power supply modulation layer, a multifunctional processing layer and a power amplifier low-noise amplifier layer which are sequentially stacked from bottom to top, and electrical interconnection among the three circuit layers and with the outside is realized by adopting the BGA solder balls. The three circuit layers adopt LTCC (Low Temperature Co-Fired Ceramic) or HTCC (High Temperature Coefficient Chip) to realize an integrated packaging structure with a cavity; the interior of the integrated structure is divided into a plurality of same independent cavities so as to accommodate circuits and structures of the channels; a signal transmission structure and a grounding through hole array are arranged in the cavity wall of the integrated structure, so that electrical interconnection, impedance matching and electromagnetic shielding inside and outside the package are realized; each cavity is sealed in an independent airtight mode through a metal cover plate. When necessary, a wave-absorbing material is added in the cavity to prevent self-excitation of the assembly. According to the invention, the product structure and the production process are simplified, the production efficiency, the packaging efficiency and the yield are improved, and the cost is reduced; the power capacity and the reliability of the product are improved, and the maintainability is good.

A manufacturing method of a package substrate includes forming a heterogeneous layer on a substrate body, forming a first circuit layer on the heterogeneous layer, forming a dielectric layer on the heterogeneous layer, embedding the first circuit layer in the dielectric layer, performing a layer-adding circuit, removing the substrate body and the heterogeneous layer to make the depth of the first circuit layer consistent, and forming a second circuit layer on the substrate body. Therefore, a plurality of solder balls can be combined on the first circuit layer.

The invention relates to the technical field of semiconductor chip packaging, in particular to a photoelectric co-packaging optical coupling passive alignment packaging structure and method. According to the invention, high-precision automatic alignment of the grating coupler in the optical chip and the through hole of the adapter plate is realized by using the solder ball tension effect in the flip reflow soldering process of the optical chip, and a stable optical limiting structure is formed. The passive coupling of the optical elements (such as bare optical fibers, optical fiber arrays, reflectors and the like) and the grating coupler is realized by placing the optical elements with matched sizes in the via holes of the adapter plate and completing refractive index matching and structure fixing by using curing glue. The whole process does not need additional active alignment equipment, is the same as a traditional chip packaging process, has the advantages of being simple in process, low in cost and high in packaging efficiency, and is a key packaging technology of a photoelectric co-packaging system in the future.

The invention relates to the technical field of chip testing, in particular to chip internal signal transmission impedance matching testing equipment which comprises a vector network analysis module and a testing socket module, the testing socket module is internally provided with an inert gas cavity and a cylindrical cavity groove, the inert gas cavity and the cylindrical cavity groove are communicated with each other, and the inert gas cavity and the cylindrical cavity groove are communicated with each other. Gas in the inert gas cavity is inert gas; according to the impedance matching test equipment for signal transmission in the chip, the probe part is actively controlled to retract during test, and the probe part is controlled to eject out to establish test connection after the chip is placed in place, so that hard friction or collision between a solder ball contact of the chip and the probe part can be effectively avoided.

The invention relates to the field of packaging substrates, in particular to a modular stacked substrate and a manufacturing method thereof. Comprising a first sub-packaging substrate and a second sub-packaging substrate; the first sub-packaging substrate and the second sub-packaging substrate are connected through a solder ball, and filling glue is arranged between the first sub-packaging substrate and the second sub-packaging substrate; the first sub-packaging substrate comprises a glass core plate, a circuit layer is arranged between the glass core plate and the surface of the first sub-packaging substrate, and the circuit layer is connected through a first metal column; the first sub-packaging substrate comprises a second metal column, the second metal column penetrates through the glass core plate to be connected with the circuit layer, and printing ink is injected into the second metal column. The yield of large-size substrates can be remarkably improved, and meanwhile the manufacturing cost is reduced. The shrinkage phenomenon caused by the state change after the material is pressed, heated and cooled in the pressing process is avoided, and the overall warping is avoided. The method can be applied to packaging of 2.5 D chips, and the technological level of large-size chips is greatly improved.

The invention provides an LPDDR packaging method, which can effectively reduce the packaging thickness and can effectively improve the heat dissipation capability of a product. The method is characterized in that redistributed solder balls are led out from each stacked LPDDR chip through vertical routing, then the whole stacked assembly is turned over, and an EMI plating layer is plated on the periphery of a plastic package body of the stacked assembly.

The utility model discloses an IC (integrated circuit) support plate BGA (ball grid array) solder ball flatting machine, which comprises a rack, a flatting feeding and discharging conveying mechanism, a CCD (charge coupled device) detection alignment mechanism and a solder ball heating and flatting mechanism, and the flatting feeding and discharging conveying mechanism can comprise a first flatting feeding and discharging conveying mechanism and / or a second flatting feeding and discharging conveying mechanism. A feeding and discharging material box positioning mechanism, a carrier plate feeding and discharging box carrying mechanism and a transferring mechanical arm mechanism can be additionally arranged on the feeding side of the first flattening feeding and discharging conveying mechanism. A series of automatic operations such as automatic loading of the support plate, automatic detection of the position of the solder ball, automatic hot pressing and leveling of the solder ball and automatic unloading and boxing of the support plate can be completed, the operation is stable and reliable, the automation degree is high, the yield and the production efficiency of the production process can be improved, the production cost is reduced, and the high-precision production requirement is ensured.

The invention provides a solder ball simulation analysis method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: after creating a coaxial body, a signal solder ball model and a signal backflow plane, connecting the coaxial body with the signal solder ball model according to a preset contact area, and adjusting the effective dielectric constant of the coaxial body, the method comprises the following steps of: connecting a simulation signal port with a coaxial body to enable impedance of the coaxial body to be matched with target impedance of a test signal, further, respectively connecting the simulation signal port with the coaxial body and a signal backflow plane, outputting the test signal through the simulation signal port, and respectively acquiring test impedance of a signal solder ball model in an air environment and a target cold liquid environment; finally, the signal solder ball model is corrected according to the test impedance, simulation analysis of the solder ball in different operation environments can be achieved through the method, a reference basis is provided for correction of the signal solder ball model, and the solder ball can meet the performance requirements in the different operation environments.

The invention discloses a microwave and millimeter wave low-cost compact radio frequency digital integrated front-end module, and relates to the technical field of microwave and millimeter wave devices. The front-end module comprises a substrate layer, a preceding-stage compound bare chip and a silicon-based chip group are arranged on the upper surface of the substrate layer, a first group of BGA solder balls located on the lower surface of the substrate layer are connected with a first metal cushion block on one side of the preceding-stage compound bare chip through a first quasi-coaxial structure penetrating through the substrate layer up and down, and a second group of BGA solder balls located on the lower surface of the substrate layer are connected with a second metal cushion block on one side of the preceding-stage compound bare chip through a second quasi-coaxial structure penetrating through the substrate layer up and down. The second metal cushion block is connected with a BGA solder ball on one side of the BGA packaging chip through a second similar coaxial structure vertically penetrating through the substrate layer, and the BGA packaging chip is connected with a third metal cushion block on one side of the silicon-based chip set through a third similar coaxial structure vertically penetrating through the substrate layer. And the fourth metal cushion block is connected with a second group of BGA solder balls positioned on the lower surface of the substrate layer through a fourth quasi-coaxial structure which vertically penetrates through the substrate layer. The front-end module can realize extremely low-loss transmission, and the interconnection flexibility is higher.

The invention relates to the technical field of welding, in particular to a solder ball preparation device for soft soldering, which comprises a ball storage tank with a mounting seat higher than a solder ball separation device, a solder ball conveying shaft is hermetically and slidably connected into the ball storage tank, and a solder ball conveying channel is formed in the center of the solder ball conveying shaft. The lower end of the solder ball conveying shaft is fixedly and hermetically connected with a ball falling hose, one end, far away from the solder ball conveying shaft, of the ball falling hose is fixedly and hermetically connected with an air pipe connecting sleeve, and the air pipe connecting sleeve is fixedly connected to the solder ball separating device and communicated with a ball storage groove of the solder ball separating device. Through the synergistic effect of multiple structures, automatic and continuous supply of the solder balls is finally achieved, the problem that the storage capacity of a ball storage bin in an existing solder ball separation device is limited is solved, high efficiency and stability of feeding of the solder balls large in size in the long-time welding process are guaranteed, and the requirement of soft soldering for solder ball supply is met.

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

Provided are a solder alloy, a solder ball, a preformed solder, a solder joint, and a circuit, which are excellent in wettability and shear strength, suitable in failure mode, capable of suppressing the growth of an intermetallic compound at a bonding interface even after multiple reflow soldering, excellent in drop impact resistance, and suitable in the shape of a bump. The solder alloy has an alloy composition comprising, in mass%, 0.10 to 3.00% of Ag, 0.80 to 6.00% of Cu, 0.08 to 0.60% of Ni, 0.0010 to 0.0150% of Ge, and the balance of Sn. It is preferable that the alloy composition further contains 0.1% or less of at least one of Bi, Sb, In, Zn, Ga, Mn, Cr, Co, Si, Ti, and rare earths in total.

The invention discloses an on-chip antenna and pulse source integrated device and method based on heterogeneous material 3D packaging integration, and relates to the technical field of antennas. The upper surface of the base substrate is used for installing a radiation structure; the upper surface of the photoconductive substrate is used for mounting an excitation structure; the interconnection structure is used for realizing electric connection between the radiation structure and the excitation structure, and the through hole is formed in the base substrate through a TSV or TGV process and penetrates through the whole base substrate; the conductive filling material is filled in the through hole; the solder balls are arranged on the lower surface of the through hole of the base substrate and are made of conductive weld-aid metal; the GSG electrode is arranged on the upper surface of the photoconductive substrate; the device adopts a 3D packaging technology, integrates a radiation structure and an excitation structure on the same chip, breaks through the frequency limitation of 110GHz of a traditional electrical pulse source, has the advantages of high-frequency performance, low dielectric loss, high integration level and the like, and is suitable for the fields of wireless communication, radar ranging systems and the like.

A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

The invention provides an improved YOLOv10-based solder ball defect detection method for a BGA packaged chip, and the method comprises the steps: collecting a solder ball image of the BGA packaged chip, carrying out the morphological preprocessing, and carrying out the analysis and classification of defects; carrying out defect generation on solder ball burr defects with less data; performing similarity measurement on the generated defects and the real defects, and selecting defect data with relatively high similarity to construct a pre-training data set; a YOLOv10 deep learning network is improved, a C2f module in the network is improved, an up-sampling module is replaced with a lightweight dynamic up-sampling operator DySample, an original loss function is replaced with a Focal-EIoU loss function, the improved network is used for pre-training, and a defect detection model is obtained; performing real-time defect detection on the solder ball of the BGA packaging chip by using the defect detection model to obtain defect information; according to the invention, the detection precision and speed of the solder ball defect of the BGA packaging chip are effectively improved.

The invention discloses a stacked chip lead bonding packaging structure and a preparation method. The preparation method comprises the following steps: preparing a temporary bonding adhesive film layer on the surface of a glass slide; preparing a metal anti-reflection layer on the surface of the temporary bonding adhesive film layer; preparing a rewiring layer on the metal anti-reflection layer; mounting and stacking a chip group on the surface of the rewiring layer; performing plastic packaging; removing the glass slide, and exposing the temporary bonding adhesive film layer; removing the temporary bonding glue layer to expose the metal anti-reflection layer; removing the metal anti-reflection layer to expose the metal bonding pad; solder balls are arranged on the metal bonding pads; and grinding and cutting to obtain the packaging body. According to the invention, the rewiring layer is used for replacing an organic substrate, a plurality of chips are mounted on the rewiring layer, interconnection among the chips is carried out through lead bonding, and signals are connected to the rewiring layer through lead bonding, so that the organic substrate is omitted, the risk of material breakage caused by imbalance of supply and demand is avoided, and the packaging cost is reduced; the method is suitable for industrial popularization.

The invention provides a method and a device for efficiently preparing gold-tin solder balls with uniform and controllable particle size, the device comprises a vacuum system, a liquid drop injection system, a particle collector, an image acquisition system and a liquid level control system, and the liquid drop injection system adopts a crucible fixed in a vacuum chamber as a container for containing gold-tin melt; a micropore piece provided with a round micropore is fixed to the bottom of a crucible and communicated with an inner cavity of the crucible, piezoelectric ceramics arranged at the top of the crucible drive a transmission rod in the crucible to vibrate and apply pressure to gold-tin melt, the gold-tin melt is jetted into liquid drops through the micropore, the liquid drops are rapidly solidified to form gold-tin soldering balls with the uniform particle size after dropping, and the gold-tin soldering balls are collected by a particle collector. And a gap between the outer edge of the bottom of the transmission rod and the micropore at the bottom of the crucible is 0.10-0.35 mm. The invention further discloses a method for preparing the gold-tin solder ball through the device, the gold-tin solder ball is successfully prepared through a pulse micropore jetting method, and the preparation efficiency and the preparation precision have leap-type progress.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

The embodiment of the present invention provides a wafer-level fan-out packaging method and a wafer-level fan-out packaging structure, which relate to the field of chip packaging technology. The method prepares a carrier with a relief protrusion and directly forms a plastic package body on the carrier. After removing the carrier, a plastic package body with a relief groove is obtained. The relief groove is directly obtained by plastic packaging with a plastic packaging material, and then the chip is embedded in the relief groove, and a passivation layer covering the relief groove is formed on the surface of the plastic package body, and finally the wafer-level processes such as wiring layer and solder ball are completed. The advantages of easy plasticity and low cost of the plastic package material are fully utilized, and the mature plastic packaging shaping process is used. In combination with the relief protrusion of the carrier, the relief groove and other structures can be accurately shaped, and the process is simple and the process difficulty is low. In addition, by embedding the chip in the relief groove, the front side is rewired to fan out each signal contact outside the plastic package, thereby improving the reliability of the plastic package.

A method for normalizing the solder interconnects (e.g., normalizing the height of the solder ball interconnects) in a circuit package module (e.g., dual-sided mold grid array package module) after removal from a test board includes receiving in a fixture the circuit package module upside down and removably coupling a stencil to the fixture and over the circuit package module. The stencil has a pattern of apertures that coincides with the pattern of solder interconnects of the circuit package module. The method also includes applying solder paste over the stencil to pass through the apertures to add solder paste to the solder interconnects. The method also includes removing the stencil from over the fixture, and removing the circuit package module from the fixture. The circuit package module can be heated to reflow the solder interconnects with the added solder paste.

The invention provides a circuit board assembly and electronic equipment. The circuit board assembly comprises a circuit board, a chip module and a heat dissipation piece, the chip module and the heat dissipation piece are stacked and arranged on the circuit board, the chip module and the circuit board are conducted through a solder ball, and the heat dissipation piece is in heat conduction connection with the chip module; the circuit board assembly further comprises heat-conducting glue and a heat-conducting piece, in the plane direction of the circuit board, a part of the heat-conducting glue is filled in the gap between the chip module and the circuit board and makes contact with the solder balls, the other part of the heat-conducting glue is located outside the chip module, and the heat-conducting piece extends in the thickness direction of the circuit board and makes contact with the solder balls. The heat-conducting piece is used for being in heat-conducting connection with the heat-dissipating piece and the other part of the heat-conducting glue. According to the circuit board assembly, through contact between the solder balls and the heat-conducting glue and contact between the heat-conducting glue and the heat-conducting piece, heat-conducting connection between the chip module and the heat-dissipating piece is achieved, thermal resistance between the chip module and the heat-dissipating piece is reduced through the heat-conducting piece and the heat-conducting glue, and therefore the heat-dissipating efficiency of the circuit board assembly is improved.

The invention discloses a correction method and system of a double-station solder ball welding machine, and belongs to the technical field of welding equipment correction, and the correction method comprises the following steps: arranging various sensors on the double-station solder ball welding machine, and collecting welding data; preprocessing the collected welding data to obtain welding processing data; performing feature extraction on the welding processing data through a feature layer fusion method to obtain a welding feature vector; building a correction prediction model based on a support vector machine, and predicting the welding feature vector obtained in real time to obtain a prediction result; deviation detection judgment is conducted on abnormal data in the prediction result, and welding data needing to be corrected are obtained; and based on the welding data needing to be corrected, corresponding correction measures are taken for the welding data with deviation in each station.

The invention provides a surface acoustic wave filter packaging structure, a preparation method thereof and radio frequency equipment, and relates to the technical field of semiconductors. By arranging the annular enclosing wall structure, the interdigital electrode is located inside the annular enclosing wall structure, the solder ball is located outside the annular enclosing wall structure, after the plastic packaging layer is prepared, the plastic packaging layer at least wraps the solder ball, at the moment, the solder ball is not in an isolated state, and the risk that the solder ball cracks or even falls off is greatly reduced in the cold and hot impact process; and the stability of the packaging structure of the surface acoustic wave filter is improved. According to the surface acoustic wave filter, the interdigital electrode is located in the annular enclosing wall structure, and the annular enclosing wall structure is in contact with the substrate and the bearing substrate in the first direction, so that the interdigital electrode and the bearing substrate are separated from each other, and the separated area is a cavity area of the surface acoustic wave filter; therefore, in the preparation process of the plastic packaging layer, the arrangement of the annular enclosing wall structure can prevent the plastic packaging material from entering the cavity area, and the effective protection of the working area of the packaging structure of the surface acoustic wave filter is realized.

The invention discloses a droplet uniformity on-line detection and alarm method and application. The method comprises the following steps: acquiring an original image through an industrial camera, carrying out image type conversion on the original image to obtain a droplet grayscale image, setting different corrosion values according to different background pollution conditions to carry out morphological operation on a solder ball image, and carrying out online detection on the droplet uniformity according to a preset connectivity value. Eliminating a part smaller than a connected value to obtain a binary image with only the microdroplet, extracting contour coordinate information of the microdroplet by using a Canny algorithm, performing first correction on the contour coordinate information by using open operation, and then performing second coordinate information correction by using a least square ellipse fitting algorithm to obtain a binary image with the microdroplet; and finally, the particle size and the roundness of the microdroplet are calculated according to the contour coordinate information of the microdroplet, and when the software detects that the threshold values of the particle size and the roundness of the microdroplet are lower than a preset alarm threshold value, the alarm gives an alarm to remind an operator to adjust parameters of equipment for preparing the microdroplet in time, so that the final product quality and the production efficiency are improved.