749 results about "Solder ball" patented technology

The invention relates to the technical field of high-end chips, and discloses a packaging defect detection method and system for an industrial solid state disk, and the method comprises the steps: collecting multi-source heterogeneous detection data, and extracting the multi-dimensional defect features of a packaging body; packaging process parameters and material attributes of the industrial solid state disk are input into the virtual mirror image body, and a defect sensitivity distribution diagram of the packaging body is generated; identifying a defect expansion path and a defect type of the packaging body; based on the process weak link, the defect expansion path and the defect type, generating a grading defect detection instruction of the packaging body; setting a personalized defect detection mode of the packaging body in combination with the number of NAND stacked layers, the solder ball spacing and the defect type; and outputting a defect detection result of the packaging body through the virtual mirror image body by utilizing a grading defect detection instruction and a personalized defect detection mode. According to the method, the accuracy and credibility of an industrial solid state disk packaging defect detection result can be effectively improved.

The invention relates to the field of packaging substrates, in particular to a modular stacked substrate and a manufacturing method thereof. Comprising a first sub-packaging substrate and a second sub-packaging substrate; the first sub-packaging substrate and the second sub-packaging substrate are connected through a solder ball, and filling glue is arranged between the first sub-packaging substrate and the second sub-packaging substrate; the first sub-packaging substrate comprises a glass core plate, a circuit layer is arranged between the glass core plate and the surface of the first sub-packaging substrate, and the circuit layer is connected through a first metal column; the first sub-packaging substrate comprises a second metal column, the second metal column penetrates through the glass core plate to be connected with the circuit layer, and printing ink is injected into the second metal column. The yield of large-size substrates can be remarkably improved, and meanwhile the manufacturing cost is reduced. The shrinkage phenomenon caused by the state change after the material is pressed, heated and cooled in the pressing process is avoided, and the overall warping is avoided. The method can be applied to packaging of 2.5 D chips, and the technological level of large-size chips is greatly improved.

The invention provides an LPDDR packaging method, which can effectively reduce the packaging thickness and can effectively improve the heat dissipation capability of a product. The method is characterized in that redistributed solder balls are led out from each stacked LPDDR chip through vertical routing, then the whole stacked assembly is turned over, and an EMI plating layer is plated on the periphery of a plastic package body of the stacked assembly.

The invention relates to the technical field of welding, in particular to a solder ball preparation device for soft soldering, which comprises a ball storage tank with a mounting seat higher than a solder ball separation device, a solder ball conveying shaft is hermetically and slidably connected into the ball storage tank, and a solder ball conveying channel is formed in the center of the solder ball conveying shaft. The lower end of the solder ball conveying shaft is fixedly and hermetically connected with a ball falling hose, one end, far away from the solder ball conveying shaft, of the ball falling hose is fixedly and hermetically connected with an air pipe connecting sleeve, and the air pipe connecting sleeve is fixedly connected to the solder ball separating device and communicated with a ball storage groove of the solder ball separating device. Through the synergistic effect of multiple structures, automatic and continuous supply of the solder balls is finally achieved, the problem that the storage capacity of a ball storage bin in an existing solder ball separation device is limited is solved, high efficiency and stability of feeding of the solder balls large in size in the long-time welding process are guaranteed, and the requirement of soft soldering for solder ball supply is met.

The invention relates to the technical field of solder ball array optimization, in particular to a low-warpage solder ball array optimization method and system in FC-BGA packaging of a glass substrate, and the method comprises the steps: determining the glass substrate and a plurality of solder balls, designing a preliminary array layout, creating a three-dimensional geometric model, carrying out the thermal loading simulation of the three-dimensional geometric model, and obtaining a plurality of thermal stress distribution nephograms; and executing the following operations on each thermal stress distribution cloud picture in the plurality of thermal stress distribution cloud pictures: obtaining a maximum thermal stress region from the thermal stress distribution cloud picture, obtaining a region position and a maximum thermal stress value according to the maximum thermal stress region, obtaining an optimal array layout, summarizing the optimal array layout, and obtaining the thermal stress distribution cloud picture. A plurality of thermal stress distribution cloud pictures are obtained, a plurality of optimal array layouts corresponding to the thermal stress distribution cloud pictures are obtained, the optimal array layout is obtained, the voidage of the welding spots is calculated based on the optimal array layout, and optimization of the low-warpage welding ball array in FC-BGA packaging of the glass substrate is completed based on the voidage of the welding spots. According to the invention, the optimization precision and efficiency of the solder ball layout can be improved.

Provided are a solder alloy, a solder ball, a preformed solder, a solder joint, and a circuit, which are excellent in wettability and shear strength, suitable in failure mode, capable of suppressing the growth of an intermetallic compound at a bonding interface even after multiple reflow soldering, excellent in drop impact resistance, and suitable in the shape of a bump. The solder alloy has an alloy composition comprising, in mass%, 0.10 to 3.00% of Ag, 0.80 to 6.00% of Cu, 0.08 to 0.60% of Ni, 0.0010 to 0.0150% of Ge, and the balance of Sn. It is preferable that the alloy composition further contains 0.1% or less of at least one of Bi, Sb, In, Zn, Ga, Mn, Cr, Co, Si, Ti, and rare earths in total.

The invention discloses a semiconductor packaging alignment mark manufacturing method and a semiconductor packaging alignment mark product. The semiconductor packaging alignment mark manufacturing method comprises the following steps that a cofferdam is manufactured at the position, corresponding to a TSV area, on light glass; the cofferdam is coated with bonding glue; bonding the wafer on the optical glass and grinding and thinning the wafer; performing etching to form a first-order groove and an alignment Mark; completing the etching of the silicon through hole; preparing a dielectric layer on the wafer; preparing a passivation layer on the dielectric layer; preparing an RDL (redistribution layer); pre-cutting a groove, and half-cutting to a cofferdam; preparing a solder mask layer; and planting or printing a solder ball, and then cutting into a final finished product. According to the invention, the alignment function of the photoetching process after pre-cutting can be realized, the overall process capability can be improved, the process steps are reduced, the product manufacturing period is shortened, the packaging cost is reduced, and the product competitiveness is improved; a special laser marking station is not needed, wafer surface pollution caused by laser marking is reduced, operators of the original laser marking station are saved, manpower and material resources are saved, one manufacturing process is saved, and the packaging cost is reduced.

The invention provides a manufacturing method of a 3D packaging structure of an optical engine module and a CPO module, and relates to the technical field of semiconductor packaging. Firstly, an optical chip wafer is provided, then an electric chip and an optical port protection piece are mounted on the basis of the surface of the optical chip wafer, plastic packaging is carried out on the basis of the upper portion of the optical chip wafer, the electric chip and the optical port protection piece are wrapped by plastic packaging materials, and then the plastic packaging materials are thinned until the optical chip and the optical port protection piece are exposed; the method comprises the following steps: manufacturing a TSV through hole on the basis of an optical chip wafer, thinning the bottom surface of the optical chip wafer until the TSV through hole is exposed, manufacturing an RDL layer and a solder ball on the basis of the bottom surface of the optical chip wafer, connecting the RDL layer with the TSV through hole, removing an optical port protection piece, and finally cutting the optical chip wafer to form a single optical engine module. According to the scheme provided by the invention, the optical chip is prevented from being damaged in the packaging process, and the design flexibility of the optical port is improved.

The utility model relates to a solder ball flattening device used for semiconductor packaging, comprising a lifting platen, the upper surface of the lifting platen is a smooth horizontal plane, and two sides of the lifting platen are respectively and symmetrically provided with ear parts; the heating device is fixedly arranged below the lifting table plate, and the heating device is used for heating the lifting table plate; and the two lead screw pairs are arranged on the two sides of the lifting table plate correspondingly, the lead screw pairs are located below the lug parts, the lead screw pairs can lift the height of the lifting table plate in the vertical direction through a driving motor, and the driving motor is fixedly arranged on the working table top.

A solder alloy consisting of Ag: 3.1 to 4.0% by mass, Cu: 0.6 to 0.8% by mass, Bi: 1.5 to 5.5% by mass, Sb: 1.0 to 6.0% by mass, Co: 0.001 to 0.030% by mass, Fe: 0.02 to 0.05% by mass, As: 0.002 to 0.250% by mass, and a balance Sn.

Provided is a board-level semiconductor package including: board pads that are separate from one another; a package substrate including substrate pads that are separate from one another and face the board pads; and connection balls between the board pads and the package substrate, wherein the connection balls connect the board pads to the substrate pads, wherein the connection balls include: metal core solder balls; and core-free solder balls, wherein the substrate pads include first and second substrate pads, and wherein the metal core solder balls are on the first substrate pads, the core-free solder balls are on the second substrate pads, and a diameter of a first second substrate pad among the second substrate pads is different a diameter of a second substrate pad from among the second substrate pads.

The present invention provides a stacked heat dissipation packaging structure and a preparation method thereof, relating to the field of chip packaging technology. The stacked heat dissipation packaging structure includes a substrate, a first chip, a heat dissipation adhesive layer, a first heat dissipation fin, a second heat dissipation fin, a plastic package, and solder balls. The first chip is mounted on the substrate, and a chip groove is provided on a non-functional surface of the first chip; the heat dissipation adhesive layer is provided in the chip groove; the first heat dissipation fin and the second heat dissipation fin are both provided in the chip groove, and the second heat dissipation fin is bent and extended onto the first heat dissipation fin, with a heat dissipation gap formed between the second heat dissipation fin and the first heat dissipation fin. Compared with the prior art, the present invention arranges both the first heat dissipation fin and the second heat dissipation fin on the heat dissipation adhesive layer, which can greatly increase the heat dissipation area, thereby improving the heat dissipation effect and heat dissipation performance. It can also effectively reduce the stacking height, which helps to achieve miniaturization of the packaging structure.

The invention provides a photoelectric chip packaging method and a photoelectric chip packaging structure, and relates to the technical field of semiconductor packaging, and the method comprises the steps: firstly mounting an electric chip on an optical chip, and then mounting the optical chip and a signal processing chip on the surface of one side of an adapter plate. And forming a solder ball on the surface of the other side of the adapter plate, and cutting the adapter plate along the cutting channel. And then the adapter plate is mounted on the substrate, and then the heat dissipation device is mounted. Compared with the prior art, electric connection is realized by adopting the design of the optical chip with the first conductive hole and the adapter plate with the second conductive hole, the delay of signal transmission can be reduced, the signal loss is reduced, and the transmission rate is improved. Meanwhile, due to the laminated design of the electric chip and the optical chip, the occupied area of the whole chip packaging can be greatly reduced, and the packaging size is reduced. And the signal processing chip and the electric chip can be directly subjected to fit heat dissipation by using the heat dissipation device, so that the overall heat dissipation performance is greatly improved.

The invention provides a photoelectric chip packaging method and a photoelectric chip packaging structure, and relates to the technical field of semiconductor packaging, and according to the method, the front faces of an optical chip and a signal processing chip are attached to an alignment plate in an alignment mode. And then the carrier plate is bonded to the back surfaces of the optical chip and the signal processing chip. And the alignment plate is removed, and the electric chip is bridged and bonded to the front surfaces of the optical chip and the signal processing chip. And then the adapter plate is attached to the front surfaces of the optical chip and the signal processing chip. And solder balls are formed on the adapter plate and the electric chip, then the carrier plate is removed, and finally the adapter plate is cut along the cutting channel. Compared with the prior art, signal transmission delay can be reduced, signal loss can be reduced, the transmission rate can be improved, meanwhile, the packaging size is reduced, and miniaturization of products is facilitated. And an alignment plate process is adopted, so that accurate alignment of the optical chip and the digital processing chip can be ensured, and the electrical connection performance is ensured.

The differential via hole structure comprises at least one differential group, the differential group comprises a first differential pair and a second differential pair, a first connecting line of two differential via holes in the first differential pair is perpendicular to a second connecting line of two differential via holes in the second differential pair, and one differential via hole in the first differential pair is located on the second connecting line; according to the embodiment of the invention, the two differential pairs in one differential group are vertically arranged, and one differential pair is located on the vertical line, passing through one differential via hole, of the other differential pair, so that the differential crosstalk can be reduced, the system margin can be improved, and the signal integrity of a link can be improved on the premise of not influencing the straight-through bandwidth. The invention further provides a solder ball array packaging assembly, a printed circuit board and communication equipment.

Disclosed is an upper press head for mechanical testing and electrical testing of a semiconductor chip package. The upper press head includes: a force receiving component configured to receive a downward force; a force delivering component, having an upper portion connected with the force receiving component and having a first lateral sectional area, and a lower portion having a second lateral sectional area less than the first lateral sectional area; a force applying component connected with the lower portion of the force delivering component and configured to apply the downward force to the semiconductor chip package, the force applying component including: a plurality of protrusions that are laterally separated from each other and are configured to simultaneously press the semiconductor chip package; and a space between two adjacent protrusions matches portions of solder balls of the semiconductor chip package.

An electronic device including an IC having a package interconnect including a pillar and a solder cap coupled to a bottom surface of the pillar to reduce the height of the IC package. The IC package includes a substrate comprising an outer metallization layer having a metal pad and a package mold layer adjacent to the outer metallization layer. The pillar has a top surface and a bottom surface. The pillar extends through the package mold layer with the top surface coupled to the metal pad and the bottom surface coupled to the solder cap. In contrast to conventional package interconnects, such as ball grid arrays (BGA), for example, deploying the solder cap on the bottom surface of the pillar advantageously results in using less solder and tighter pitch between adjacent package interconnects because the width of the pillar is less than a solder ball in a BGA.

The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system uses a cooling fluid supply module for the cooling of the pogo pin, and the cooling fluid may be either a coolant or a cooling gas. When an electronic device is accommodated in the chip socket, the cooling fluid supply module supplies a cooling fluid into the chip socket through the cooling fluid supply channel and the inlet, and the cooling fluid passes through the pogo pins and then flows into the cooling fluid discharge channel through the outlet. In the present invention, the cooling fluid is mainly used to cool not only the pogo pins in the chip socket but also the bottom surface of the electronic device and the solder ball contacts on the bottom surface.

The invention relates to the technical field of surface optical defect detection, in particular to a tin ball unqualified product identification and rejection system based on online monitoring, which constructs a structure expression map based on linkage analysis of a contour change area, an edge response intensity matrix and a direction gradient mapping matrix and in combination with position difference and brightness fall between connection points. High-sensitivity capture of local details on the surface of the solder ball is realized, and the recognition precision and boundary judgment capability of irregular pit and spot areas are remarkably improved by calculating coordinate offset and boundary length change between connection points and combining a graph neural network. Through a multi-factor association adjustment mode of determining confidence, label disturbance frequency and historical deviation records, adaptive convergence of identification classification parameters and progressive optimization of an output matrix structure are realized, the identification precision of a flaw area is improved, and the real-time performance and stability of subsequent action response are optimized.

The invention discloses a three-dimensional stacked multi-channel radio frequency module based on a mixed ceramic material, and relates to the technical field of microelectronic packaging. The invention relates to a radio frequency module which comprises an HTCC tube shell and a DPC tube shell which are arranged in an overlapped mode, the interior of the HTCC tube shell is divided into at least two independent cavities used for installing radio frequency chips through a metal enclosure frame, a control and power supply chip is installed in the DPC tube shell, and a solder ball array is further arranged on the lower surface of the DPC tube shell; the three-dimensional stacked packaging structure further comprises a radio frequency vertical interconnection piece, the radio frequency vertical interconnection piece is vertically arranged in the DPC tube shell and extends upwards, and the HTCC tube shell and the DPC tube shell are fixedly connected through the radio frequency vertical interconnection piece to form the three-dimensional stacked packaging structure. The invention provides a three-dimensional stacked multi-channel radio frequency module based on a mixed ceramic material, which can significantly reduce the overall packaging cost and complexity through heterogeneous material integration and three-dimensional stacking on the premise of ensuring high-efficiency heat dissipation and high channel isolation of a high-power radio frequency chip. And the multi-channel radio frequency SiP packaging with high performance, miniaturization and low cost is realized.

Provided are a solder alloy, a solder paste, a solder ball, and a solder joint which have a low melting point, are excellent in ductility, shear strength, and heat cycle resistance, further suppress the occurrence of open defects, and in addition, have reduced residual voids even at the time of joining in a large area. A solder alloy has an alloy composition of, by mass %, Bi: 35.0 to 68.0%, Sb: 0.1 to 2.0%, Ni: 0.010 to 0.050%, Ge: 0.007 to 0.090%, with the balance being Sn. Preferably, the alloy composition further contains, by mass %, at least one of Co, Ti, Al, Mn, As, Fe, Pd, Zn, Zr, Pb, In, Ce, P, and Ga: 0.1% or less in total. Further, this solder alloy can be suitably used for solder pastes, solder balls, and solder joints.

A double-sided partially molded SIP module. A semiconductor device has a substrate and a first component disposed above a first surface of the substrate. A connector is disposed above the first surface of the substrate. A first sealant is deposited above the first component, while the connector remains outside the first sealant. A shielding layer is formed above the first sealant, while the connector remains outside the shielding layer. A second component is disposed above a second surface of the substrate. Solder bumps are disposed above the second surface of the substrate. A second sealant is deposited above the second surface of the substrate. An opening is formed through the second sealant to expose the solder bumps. Solder balls are disposed in the openings. The solder balls and solder bumps are reflowed to form a combined solder bump.

The present invention employs a lead-free and antimony-free solder alloy which has an alloy composition that contains from 1.0% by mass to 4.0% by mass of Ag, from 0.1% by mass to 1.0% by mass of Cu, from 0.1% by mass to 9.0% by mass of Bi, from 0.005% by mass to 0.3% by mass of Ni and from 0.001% by mass to 0.015% by mass of Ge, with the balance being made up of Sn.

The application relates to a method for improving the thermal fatigue resistance of a lead-free solder interconnection BGA package joint, and relates to the field of electronic packaging welding. The surface of a PCB substrate is processed by superfast laser to have a well-shaped micro-nano structure, the well-shaped micro-nano structure is a grid-shaped straight-line groove microstructure formed by a plurality of transverse parallel lines and a plurality of longitudinal parallel lines, the adjacent interval between the plurality of transverse parallel lines and the plurality of longitudinal parallel lines is 80-120 mu m, the groove width is 10-20 mu m, the groove depth is about 30-50 um, the groove parameters are adjusted by adjusting the superfast laser processing parameters, and a large number of micro-particles are covered on the inside and around the groove; the solder ball is planted on a bare chip through a heating plate, and the chip and the processed PCB substrate are welded and packaged through a hot air welding machine. The specific surface area and structural richness of the surface are improved, and the problems of poor thermal fatigue resistance and poor durability of the existing BGA package joint can be solved.

The invention belongs to the technical field of semiconductor memory packaging, and particularly relates to a memory chip based on two-dimensional material and CMOS circuit 2.5 D integration and a preparation method thereof. According to the chip, a 2.5 D packaging structure is adopted, two-dimensional material ultra-flash memory device core particles and peripheral control circuit core particles prepared by adopting a standard CMOS technology are integrated on an intermediate layer, reliable electric connection is achieved through a metal bump-solder ball interconnection structure, a low-temperature flip-chip technology is adopted in the packaging process, and therefore the reliability of the chip is improved. The design of a multi-layer metal bump laminated structure is matched, and the heat sensitivity and interconnection reliability of the two-dimensional material are considered; and the intermediate layer is further connected with a PCB test board below the intermediate layer to construct signal channels among the core particles and outside the chip. According to the structure, the ultrafast programming / erasing characteristic of the two-dimensional material flash memory and the logic function advantage of the CMOS circuit are fully combined, and a feasible path and technical support are provided for engineering and system-level application of a two-dimensional material ultrafast memory device.

The invention relates to the technical field of element identification and positioning, and discloses a BGA type element feature adaptive search method, system, device and equipment and a medium, and the method comprises the following steps: obtaining the average circle radius of solder balls and the central position of each solder ball from a feature region of a BGA type element image; counting projection information of an overall distribution diagram formed based on the average circle radius and the center position of each solder ball in the horizontal and vertical directions; according to the projection information, correcting the inclination angle of the feature area or eliminating the mark point to obtain a corrected image; constructing a row matrix and a column matrix according to the position information of the solder balls on the corrected image; and detecting whether interference points exist in the corrected image according to the row matrix and the column matrix. According to the scheme, the size features of the BGA element can be searched in a self-adaptive mode, high reliability and self-inspection capacity are achieved, interference points / false feature points can be effectively recognized and removed through self-inspection, and the accuracy of feature search results is guaranteed.

Provided is a component with solder bumps comprising: a substrate; and a plurality of electrodes positioned on the substrate and having solder bumps. In some of the electrodes, the solder bumps are high bumps having a solder base part formed on the electrode surface and a solder protruding part formed on the solder base part surface, and in the remaining electrodes, the solder bumps are small bumps having a solder base part formed on the electrode surface.

The invention discloses a semiconductor packaging method, which comprises the following steps of: preparing a wafer or a chip with a first rewiring layer; mounting a wafer or a chip, or the wafer or the chip and a support material on a carrier plate, carrying out plastic packaging, removing the carrier plate, and exposing the first rewiring layer; manufacturing a second rewiring layer, an electroplating metal circuit layer and a supporting frame on the first rewiring layer; and after a plurality of rewiring layers are manufactured as required, electroplating a lead frame or manufacturing solder ball bumps, and finally cutting into single packaging bodies. According to the invention, the solid support material with high modulus and low thermal expansion coefficient is embedded in the second rewiring layer, so that a local stress suppression skeleton is constructed in the packaging structure, and free shrinkage and expansion of the polymer dielectric layer in the subsequent thermal process are effectively restrained. Therefore, thermal stress generated by mismatch of thermal expansion coefficients is greatly offset, the overall bending deformation of the packaging body is fundamentally inhibited from the interior of the structure, and the overall rigidity and the anti-warping capability of the packaging body are improved.

The invention provides an alloy solder and a solder ball. The alloy solder comprises the following components in percentage by weight: 1.0 to 5.0 weight percent of silver, 0.01 to 1.0 weight percent of copper, 0.01 to 1.0 weight percent of nickel, 0.005 to 0.015 weight percent of germanium, 0.05 to 1 weight percent of bismuth, 0.01 to 1.0 weight percent of indium and the balance of tin. The silver can significantly improve the heat-resistant cycle performance and adjust the melting point characteristic. The copper can improve the wettability of the alloy. Nickel can restrain overgrowth of intermetallic compounds on a welding spot interface, and the mechanical reliability of the welding spot is improved. And germanium can improve the oxidation resistance. Bismuth can maintain high shearing force, and meanwhile, the tensile strength and the yield strength of a welding spot are remarkably improved. The indium can improve the toughness of the solder and the binding force of the interface IMC. According to the alloy solder, the alloy variety and content are controlled within the range, and the heat-resistant cycle performance and reliability of the alloy solder can be improved.

The invention provides a light-emitting diode and a manufacturing method of the light-emitting diode, and belongs to the field of light-emitting devices. The light-emitting diode comprises an epitaxial structure and an electrode bonding pad, the electrode bonding pad comprises a bonding pad body and a solder ball, the bonding pad body is located on the epitaxial structure, the solder ball is located on the bonding pad body, and the face, away from the epitaxial structure, of the solder ball is a spherical face. The electrode bonding pad is composed of the bonding pad body and the solder balls, the solder balls are located on the bonding pad body and used during welding, and the packaging cost of chip packaging can be reduced.