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4930 results about "Delamination" patented technology

Delamination is a mode of failure where a material fractures into layers. A variety of materials including laminate composites and concrete can fail by delamination. Processing can create layers in materials such as steel formed by rolling and plastics and metals from 3D printing which can fail from layer separation. Also, surface coatings such as paints and films can delaminate from the coated substrate.

Diode housing

A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and / or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas. By minimizing the area of the conductor exposed to the window, delamination brought about by the different thermal expansions of the window and conductor are minimized and / or eliminated. Likewise, with a reflective housing covering the base of the cavity that accommodates the window, internal radiation reflection is increased over that which was achieved with an exposed conductor.
Owner:OSRAM GMBH

Semiconductor package having a heat sink with an exposed surface

An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant. With this integrated circuit package, no jig is required in the assembly of the integrated circuit package. Moreover, since there is no need to use adhesives to adhere the supportive legs onto the substrate, the integrated circuit package would not suffer from delamination as in the case of the prior art. The fully-exposed heat sink allows an increased heat-dissipating efficient as compared to the prior art.
Owner:SILICONWARE PRECISION IND CO LTD

Device And Method For Processing Light-Polymerizable Material For Building Up An Object In Layers

A method and a device for processing a light-polymerizable material (5, 55) for building up an object (27) in layers, using a lithography based generative manufacture having a construction platform (12) for building up the object (27), a projecting exposure unit (10, 60) that can be controlled for locally selected exposing of a surface on the construction platform (12, 62) to an intensity pattern having a prescribed shape, and a control unit (11, 61) prepared for polymerizing overlapping layers (28) on the construction platform (12, 62) in successive exposure steps, each having a prescribed geometry, by controlling the projecting exposure unit (10, 60), in order to thus successively build up the object (27) in the desired shape, said shape resulting from the sequence of layer geometries. The invention is characterized in that a further exposure unit (16, 66) for exposing the surface of the construction platform (12, 62) is provided on the side opposite the projecting exposure unit (10, 60), and that the construction platform (12, 62) is designed to be at least partially transparent to light, and that the control unit (11, 61) is designed for controlling the further exposure unit (16, 66) at least while building up the first layer (28), said layer adhering to the construction platform (12, 62), for exposing in the prescribed geometry.
Owner:VIENNA UNIVERSITY OF TECHNOLOGY +1

Stacked chip package using warp preventing insulative material and manufacturing method thereof

In a stacked chip configuration, and manufacturing methods thereof, the gap between a lower chip and an upper chip is filled completely using a relatively simple process that eliminates voids between the lower and upper chips and the cracking and delamination problems associated with voids. The present invention is applicable to both chip-level bonding and wafer-level bonding approaches. A photosensitive polymer layer is applied to a first chip, or wafer, prior to stacking the chips or stacking the wafers. The photosensitive polymer layer is partially cured, so that the photosensitive polymer layer is made to be structurally stable, while retaining its adhesive properties. The second chip, or wafer, is stacked, aligned, and bonded to the first chip, or wafer, and the photosensitive polymer layer is then cured to fully bond the first and second chips, or wafers. In this manner, adhesion between chips / wafers is greatly improved, while providing complete fill of the gap. In addition, mechanical reliability is improved and CTE mismatch is reduced, alleviating the problems associated with warping, cracking and delamination, and leading to an improvement in device yield and device reliability.
Owner:SAMSUNG ELECTRONICS CO LTD
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