708 results about "Control unit" patented technology

A wind energy plant with a nacelle, a rotor, which features at least one rotor blade adjustable in its blade pitch angle, a central control device for controlling the wind energy plant and a control unit disposed in the rotor for controlling the blade pitch angle of the at least one rotor blade, wherein the central control device and the control unit in the rotor can exchange data with each other via a data link, which comprises at least one first sending and receiving device at the nacelle side and at least one second sending and receiving device at the rotor side, wherein a wireless network connection with a safety-oriented communication protocol is provided between the at least one first sending and receiving device and the at least one second sending and receiving device, and that one monitoring- and communication device at a time is associated to the first and / or the second sending and receiving device, which can monitor the function of the sending and receiving device and initiate a predetermined action in the case of an error.

A canteen is composed of a main body, a cover, a control unit, a valve and an annular blocker. The cover is engaged with the main body, having a jointing tube protruding into the main body and two notches cut in the jointing tube. The control unit is fixed on the cover, having a jointing portion, two grooves formed in the jointing portion and reversely shaped to correspond to the notches of the cover, and a sucker bored with an outlet. The valve is installed in the control unit, having a bar to correspond to the outlet, and a guiding rod transversely extended out from its bottom to extend through the grooves and the notches of the cover. When rotating the control unit, the valve is moved up and down to be separated from or to clog the outlet, convenient for using and preventing the suction portion from contaminated.

A valve timing control device includes: a unit for calculating a target valve timing for one of an intake valve and an exhaust valve in accordance with an operational state; a unit for detecting an actual valve timing of one of the intake valve and the exhaust valve; an actual valve timing control unit for generating a controlled variable for the VVT based on a difference between the target valve timing and the actual valve timing; a unit for learning a learning value of the controlled variable required for maintenance of the actual valve timing based on an integral correction value; and a unit for detecting a malfunction in a VVT from an amount of a shift in the actual valve timing when learning is not completed yet, and for detecting a malfunction in the VVT from the difference when learning is already completed.

A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The invention provides a safe starting method and device of a programmable logic controller, a PUF circuit, a starting control unit and a password authentication unit are integrated on a main controller chip of a PLC system, and the method comprises the following steps: responding to power-on of the PLC system, activating the PUF circuit and generating a device root key; the starting control unit activates and operates the starting state machine; under the control of the starting state machine, the starting control unit executes the following step-by-step verification and loading processes: reading a code of a first-stage boot loader from a boot read-only memory of the PLC system, and checking; in the first stage, the boot loader reads encrypted firmware data and checks the encrypted firmware data; loading an operating system component or an application program of the PLC system, and checking; and if the inspection is passed, entering an operation state, and executing a corresponding industrial control task by the PLC system. Firmware tampering and unauthorized code execution are effectively resisted, and the starting safety and the operation reliability of the PLC system are comprehensively enhanced.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

The invention relates to a PPS (pulse per second) signal synchronization FPGA (field programmable gate array) timer, which takes a full-localization Fudan micro JFM7K325T chip as a core, comprises a time synchronization unit, a main control unit and a multi-interface unit, and is matched with a real-time clock chip. Wherein the time synchronization unit comprises a synchronization processing module, a time information module and the like, a PPS signal and TOD time information are integrated to generate a PPS + TOD + millisecond timestamp, a 25MHz constant-temperature crystal oscillator is divided into a 250MHz clock in a frequency division manner, and the time sequence precision is guaranteed; through a dual mechanism of satellite master synchronization and RTC bottom compensation, a new timestamp is rapidly combined when PPS is interrupted, and the error is controlled within 4ns; the register array stores timestamps, configuration parameters and running states in a classified mode and supports extension of multiple interfaces such as 422 and IIC and event log power-down storage. According to the invention, high-precision time synchronization, stable operation and full-link localization autonomous controllability are realized, and multi-scene multi-user board card synchronization requirements are met.

A management device according to the present invention comprises a control unit. The control unit executes processing that acquires resource information that stipulates remaining amounts of resources needed to process a workpiece for respective processing systems, processing that, when input of a production plan that stipulates at least a type of workpiece to be produced and a quantity for the workpiece to be produced has been received, allocates processing of the relevant quantity of the workpiece to a plurality of processing systems and transmits a processing order that designates the type of workpiece to be processed and the quantity of the workpiece to the processing systems that are to do the processing, and processing that determines whether the resources at the processing systems that are to do the processing are insufficient on the basis of the processing order and the remaining amounts of the resources at the processing systems that are to do the processing and, when it has been determined that the resources are insufficient, outputs a warning that indicates that the resources are insufficient.

The invention relates to the technical field of artificial intelligence hardware, and provides an artificial intelligence chip and an integrated device.The artificial intelligence chip comprises a computing bare chip, a first storage control unit, a second storage control unit and a first memory; the first storage control unit is arranged in the computing bare chip, and the first storage control unit is connected with the first memory; the second storage control unit is arranged in the computing bare chip or connected with the computing bare chip, the second storage control unit is used for being connected with a second memory, and the second memory is arranged outside the artificial intelligence chip; in the event that the computing die initiates a unified memory access, the data allocation of the first memory and the second memory is determined based on the bandwidth of the first memory and the bandwidth of the second memory. According to the chip and the device provided by the invention, the heterogeneous memory system design of the artificial intelligence chip is realized, the high bandwidth advantage of the first memory and the high capacity advantage of the second memory are both played, and dual optimization of bandwidth and capacity is realized for the heterogeneous memory system of the artificial intelligence chip.

The invention discloses a Softmax operator circuit and method based on a semi-precision floating-point number, and relates to the technical field of circuits, and the method comprises the steps that the circuit comprises an addition module, a multiplication module, a reciprocal module, an index calculation module and a main control unit; the addition module is used for carrying out addition calculation on the semi-precision floating-point number; the multiplication module is used for carrying out multiplication calculation on the semi-precision floating-point number; the reciprocal calculation module is used for performing reciprocal calculation on the semi-precision floating-point number; the index calculation module is used for performing index calculation on the semi-precision floating-point number; and the main control unit is used for synchronizing the state of each module through the corresponding confirmation signal after each module completes the corresponding calculation. Based on modular and parallel design, the precision of the semi-precision floating-point number is still kept on the premise that hardware resources and the area are remarkably saved, redundant operation and resource consumption are greatly reduced, higher numerical accuracy is achieved, and efficient, high-precision and low-power-consumption calculation acceleration can be achieved under the limited hardware condition.

A method is provided for configuring an SIL simulation of a control unit running on a computer, software modules for the control unit, which have a plurality of tasks, being installed on the computer for the SIL simulation of the control unit, the tasks being processed in a predetermined clock cycle having a periodic period between the individual clock time points, and the computer including a plurality of processor cores, on which a plurality of virtual machines run, which each process predetermined tasks. A possibility is thus provided for minimizing the computing time of an SIL test.

To suppress current consumption of a processor from exceeding an upper limit when each of a plurality of cores variably controls a clock frequency and a power supply voltage.SOLUTION: In a processor comprising a plurality of cores including floating-point units, a frequency / voltage control unit provided corresponding to each core supplies the corresponding core with a clock having a variable frequency and a power-supply voltage having a variable voltage. An instruction issuance control unit provided in each core controls the issuance of floating-point operation instructions to the floating-point unit, and reduces the issuance frequency of floating-point operation instructions to the floating-point unit when the current frequency value is greater than a reference frequency value or when the current power-supply voltage value is greater than a reference power-supply voltage value. This makes it possible to prevent the current consumption of the processor from exceeding an upper limit.SELECTED DRAWING: Figure 2

This application discloses a method and electronic device for distinguishing serial hard drives in an input / output hub, relating to the field of server storage technology. The method involves first acquiring the Peripheral Component Interconnect (PCI) device information of the serial hard drive to be identified (including manufacturer identifier, device identifier, and bus device function address indicating its physical location), and simultaneously acquiring the identifier of the input / output hub (IOH) controller (including manufacturer identifier, device identifier, and the address range of the IOH in the PCI topology). By comparing these two types of information, the control unit to which the hard drive belongs is determined. If the hard drive belongs to the IOH controller, it indicates that its interface is an IOH SATA type directly associated with the IOH. If it does not belong to the IOH controller, it can be excluded as an IOH SATA hard drive, pointing to an M.2 SATA interface type. This method bypasses the consistent SATA protocol of both, utilizing the difference in physical connection and control affiliation to achieve accurate differentiation of interface types.

The performance of an adaptive microelectronic circuit is at least partly configurable by selecting a value of an operating parameter. On processing paths, data inputs of register units are coupled to outputs of respective logic units for temporarily storing output values of said logic units. A plurality of timing event monitors respond to a digital value at a data input of a monitored register unit changing later than an allowable time limit by generating a timing event observation signal. The plurality of timing event monitors form a plurality of monitor groups, each monitor group being coupled to a branch of a triggering signal tree for coupling a monitor-group-specific triggering signal to the monitor group independently of other monitor groups. A control unit selectively allows or disables the propagation of the respective triggering signals into said branches of the triggering signal tree.

The invention provides a microprocessor architecture, a clock signal generation method and a storage medium, and is applied to the technical field of computers, the microprocessor architecture comprises a control unit, a clock signal source and a function unit, and the clock signal source comprises a basic clock unit and a frequency modulation clock unit. The frequency modulation clock unit comprises a first gating unit and at least two parallel initial signal generation units, the control unit configures first configuration information and first gating information, and the basic clock unit generates a basic clock signal; each initial signal generation unit generates a respective corresponding initial clock signal according to the first configuration information and the basic clock signal, and the first gating unit determines a target clock signal in each initial clock signal according to the first gating information and outputs the target clock signal to the functional unit, so that the functional unit operates based on the target clock signal. The clock signal source provided by the invention can effectively simplify the adjustment process of the clock frequency, improve the adjustment efficiency of the clock frequency, and meet the actual application requirements.

A storage controller (for example, a storage control unit 123) can execute log creation processing of, when a write request is processed and control information or cache data is updated, adding a header to the updated data to create an update log and storing the update log in a log buffer. In the log creation processing when first-type control information (normal control information) is updated, the storage controller adds a log header to each piece of updated first-type control information to create an update log (normal log 132), and in the log creation processing when second-type control information (cache directory) is updated, the storage controller creates one consolidated log (consolidated log 137) as an update log related to a plurality of pieces of second-type control information.

The objective is to provide a gaming machine that incorporates improvements to the way jump instructions are used in the control program of the gaming machine. [Solution] The main control unit 161 is capable of executing jump instructions to change the address of the program to be executed. The jump instructions include a JP instruction that directly specifies the destination address and a JR instruction that specifies a relative value from the address of the currently executing program. The JR instruction is an instruction with a smaller program size than the JP instruction.

A control device includes an input interface configured to accept a user's language instruction, a display configured to show information to the user, and a control unit configured to, upon receiving a predetermined instruction to transition to a second operating mode that accepts a user's language instruction while in a first operating mode that terminates the acceptance of a user's language instruction, cause the display to show first information prompting the user to speak and second information different from the first, in different ways.

The invention discloses a system for realizing synchronization between processor cores and a synchronization method thereof. The system comprises two or more local control units corresponding to the processor cores, and a global control unit, wherein the local control unit is connected with the corresponding processor core and the global control unit; the local control unit is set to receive a synchronization request from the corresponding processor core in the current synchronization period and send a synchronization state query request to the global control unit; receiving a synchronized state from the global control unit, and sending a first notification of ending the sending of the synchronization request to the processor core; and the global control unit is set to receive the synchronization state query request from the local control unit and return a synchronized state to the local control unit when detecting that all the processor cores initiate synchronization requests.

This control device (1) comprises: an auxiliary storage unit (11); a main storage unit (12) including a first region (121) and a second region (122); a noise acquisition unit (13); an fault occurrence determination unit (14); and a control unit (16) that executes a program of the first region (121) and stores the execution result obtained by executing the program of the first region (121) in the first region (121) and the second region (122). When information regarding noise is acquired by the noise acquisition unit (13), and the fault occurrence determination unit (14) determines that a fault has occurred in the first region (121), the control unit (16) i) stops the execution of the program in the first region (121), and ii) using the execution result obtained by executing the program in the first region (121) and stored in the second region (122), executes the program in the second region (122) to continue operation, and stores the program in the first region (121) from the auxiliary storage unit (11) to restore the first region (121).

The present invention relates to a device that performs multiple tasks simultaneously with a single operation, and the multiple tasks are intended to apply the same load conditions to each, even under different displacement conditions. Specifically, the device comprises: an output unit (100) in which the same load is applied to each of multiple work points (P1) via output rods (110); an input unit (200) that inputs energy as displacement to the output unit; and a control unit (300) located between the output unit and the input unit, which applies the same load to the output unit.

The application discloses a batch control switching method based on dynamic recombination and decoupling, comprising the following steps: step 1, constructing an extensible control unit library, wherein the control unit library comprises a plurality of independent control modules formed by abstracting the functions of physical devices; step 2, in response to a new production task request, selecting corresponding control modules from the control unit library, and performing dynamic recombination to generate a unit combination logic matched with the production task; and step 3, providing a recipe parameter set separated from the unit combination logic. Through the implementation of the application, the modular dynamic recombination of the control logic is realized, the production line can be quickly adapted to a new production task within minutes, and the problems of low switching efficiency and poor flexibility caused by unit rigidity, process and recipe coupling and chain waiting in the traditional system are fundamentally solved, and the agility and overall equipment efficiency of batch production are significantly improved.

The processing unit 24 includes an abnormality diagnosis unit 32 for diagnosing processor abnormalities or power supply abnormalities, and a control unit 34 that executes a reset process when a processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit 32. When a processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit 32, the control unit 34 can execute a reset process while holding the abnormality information acquired by the abnormality diagnosis unit 32 in the volatile memory 36 without writing it to the non-volatile memory 38, and can perform control to write the abnormality information held in the volatile memory 36 to the non-volatile memory 38 after the reset process is completed.

A control unit (300) comprising the following: a control unit memory (120) with a configuration register (124) for defining an operating mode of the control unit (300) and a lock register (122) for storing a lock indicator, wherein, immediately after authorization information has been set during a system initialization event, the lock indicator in the lock register (122) is set to a value indicating whether at least part of the authorization information can be changed or not, and set up a controller (302) to: to receive a request for access to a first memory area of ​​a memory (308) from a request device (306) separate from the control unit (300); in response to the request to access authorization information, which contains a multitude of entries corresponding to different memory areas (110-1 to 110-n) of the memory (308), each entry of the multitude of entries comprising a multitude of indicators, the indicators comprising: a first indicator that can assume an active value, representing an execution access mode in which instructions are retrieved from the respective memory area for execution, a second indicator that can assume an active value representing a privileged access mode in which access to the respective memory area is permitted if the requester has a privileged level; and a third indicator representing a read or write mode on a memory area; and Based on the occurrence of the system initialization event and according to the metadata of the request and the authorization information, to determine whether access to the content in the first storage area is allowed.

The invention relates to the technical field of vehicle diagnosis, and discloses a multi-core chip, a vehicle diagnosis method and a vehicle diagnostic agent.The multi-core chip comprises a first kernel, a second kernel and a third kernel, the first kernel is used for establishing encrypted communication connection with a mobile terminal, and the second kernel is used for establishing encrypted communication connection with the mobile terminal; receiving a configuration data packet required by vehicle diagnosis from the mobile terminal; the second kernel is used for sending a diagnosis instruction to the vehicle-mounted control unit based on the configuration data packet, collecting diagnosis data as diagnosed information, and returning the diagnosed information to the mobile terminal through the first kernel; and the third kernel is used for establishing a bidirectional encryption channel between the first kernel and the second kernel by using the first communication key distributed to the first kernel and the second communication key distributed to the second kernel. The safety, the integration level and the communication efficiency of the vehicle diagnosis system are remarkably improved.