1401 results about "Control unit" patented technology

A wind energy plant with a nacelle, a rotor, which features at least one rotor blade adjustable in its blade pitch angle, a central control device for controlling the wind energy plant and a control unit disposed in the rotor for controlling the blade pitch angle of the at least one rotor blade, wherein the central control device and the control unit in the rotor can exchange data with each other via a data link, which comprises at least one first sending and receiving device at the nacelle side and at least one second sending and receiving device at the rotor side, wherein a wireless network connection with a safety-oriented communication protocol is provided between the at least one first sending and receiving device and the at least one second sending and receiving device, and that one monitoring- and communication device at a time is associated to the first and / or the second sending and receiving device, which can monitor the function of the sending and receiving device and initiate a predetermined action in the case of an error.

The invention discloses a control method for a cooling circulation system of a multi-core processor, and relates to the technical field of computer hardware heat dissipation, and the control method comprises the following steps: the multi-core processor is responsible for executing a calculation task; the sensor module monitors the temperature of each core; the cooling system control module is used for receiving data from the temperature sensor and the load monitoring module, calculating the cooling requirement of each core according to the data and commanding a cooling unit to adjust; the cooling unit is used for adjusting cooling equipment to reduce the temperature of the processor according to an instruction of the control unit; and the debugging interface is used for monitoring the state of the system and displaying the temperature, the load and the cooling resource distribution condition of each core. The method has the beneficial effects that the rotating speed of the fan, the liquid cooling flow and the working state of the heat pipe system can be accurately controlled by combining the accurate analysis of the load change and the temperature data, the heat dissipation efficiency of the processor is improved, and the energy waste is reduced.

The invention discloses a specific detection value identification method and device and a computer program product, and the method comprises the steps: S1, collecting the power data of a to-be-detected node of a power system, and transmitting the power data to an edge calculation layer in real time through a distributed operation system; s2, preprocessing the power data at an edge calculation layer to generate standardized time sequence data; s3, extracting time domain statistical features and frequency domain transformation features of the standardized time series data, and fusing high-dimensional features output by a pre-training deep learning model to construct a multi-dimensional feature vector; s4, performing pattern recognition on the multi-dimensional feature vector based on a pre-trained classification or clustering model, and outputting an anomaly detection result; and S5, feeding back an abnormal detection result to the power equipment control unit in real time through the distributed operating system, and triggering an alarm or executing parameter adjustment. According to the invention, efficient distribution of detection results and multi-node parallel processing can be realized, and the system performance is further optimized.

The invention relates to a rectification harmonic suppression control method for a double reverse star transformer. The method comprises the following steps: establishing a rectifier bridge arm phase characteristic parameter table in a control platform, and recording a theoretical conduction phase, winding attribution and waveform synchronization characteristics of a bridge arm; in the operation process of the rectification control unit, the output current of a transformer and the conduction state of a bridge arm are collected, and a rectification operation state data set is generated; and calculating bridge arm conduction phase deviation, and analyzing a corresponding harmonic component to obtain a mapping relation between a bridge arm state and harmonic distribution. And judging whether the current bridge arm configuration meets the phase coverage requirement of the target rectification pulse number or not according to the mapping result, and if not, selecting a standby bridge arm group with a preset phase difference and generating a switching instruction. And the rectification control unit responds to the instruction to lock the current bridge arm conduction path and release the target bridge arm group so as to realize bridge arm resource dynamic reconstruction and rectification performance optimization. Harmonic waves can be effectively suppressed, and the topology adaptability and the output quality of the rectification system are improved.

A canteen is composed of a main body, a cover, a control unit, a valve and an annular blocker. The cover is engaged with the main body, having a jointing tube protruding into the main body and two notches cut in the jointing tube. The control unit is fixed on the cover, having a jointing portion, two grooves formed in the jointing portion and reversely shaped to correspond to the notches of the cover, and a sucker bored with an outlet. The valve is installed in the control unit, having a bar to correspond to the outlet, and a guiding rod transversely extended out from its bottom to extend through the grooves and the notches of the cover. When rotating the control unit, the valve is moved up and down to be separated from or to clog the outlet, convenient for using and preventing the suction portion from contaminated.

The invention discloses a dynamic neutral position and boundary self-calibration method and system of a joystick, and belongs to the technical field of engineering machinery and mining equipment control, and the method comprises the following steps: S1, electrifying equipment, and selecting a mode; s2, calibrating a dead zone; s3, setting a threshold value; s4, data storage; and S5, exiting and applying. According to the dynamic median and boundary self-calibration method and system of the joystick, when the joystick works, a physical manipulated variable is converted into an original electric signal through a joystick sensing unit, then the original electric signal is received through a signal processing module and subjected to signal conditioning, and an analog signal is converted into a digital signal which can be processed by a microprocessor; all logical judgments are executed through the main control unit, a user issues an instruction through a user configuration interface and directly inputs the instruction to the main control unit, the main control unit and the nonvolatile memory carry out bidirectional data interaction to realize permanent storage and calling of dead zone parameters, and the main control unit generates a final control instruction to be output after processing all information. And the actuating mechanism is driven.

A valve timing control device includes: a unit for calculating a target valve timing for one of an intake valve and an exhaust valve in accordance with an operational state; a unit for detecting an actual valve timing of one of the intake valve and the exhaust valve; an actual valve timing control unit for generating a controlled variable for the VVT based on a difference between the target valve timing and the actual valve timing; a unit for learning a learning value of the controlled variable required for maintenance of the actual valve timing based on an integral correction value; and a unit for detecting a malfunction in a VVT from an amount of a shift in the actual valve timing when learning is not completed yet, and for detecting a malfunction in the VVT from the difference when learning is already completed.

A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.

The invention discloses a large-model context control system and method based on hierarchical memory and an association graph, and the method comprises the steps: constructing a tree graph mixed memory structure and a logic hierarchical memory model for a context control unit between a user and an LLM, and carrying out the self-adaptive processing of a super-long context through a self-adaptive processing engine, a single-theme persistent dialogue control mechanism, and the like. According to the method, the problem that an LLM context window is limited (including introduction of a mechanism similar to an Agent) is solved, just like an operating system helps developers / users to solve the problems that hardware standards hidden behind are not uniform, and complex resource control is caused, a reliable LLM memory (context) control service with multiple details hidden is provided for upper developers, and the method has the advantages of being high in practicability and easy to popularize and use. The final objective of the method is to approximately relieve the limitation of an LLM context window through a set of self-consistent system mechanism, so that a developer does not need to pay too much attention to the details of a bottom layer, and more energy can be focused on the implementation of an application function.

The invention discloses a lattice-based cryptographic algorithm-oriented side channel attack-resistant NTT circuit, which comprises a control unit, which is mainly used for controlling the enabling of a bottom layer component in the structure and the data flow direction among modules; the storage unit is used for storing the coefficient, the random twiddle factor address and the twiddle factor; the address generation unit is used for calculating and generating a storage RAM (Random Access Memory) address of a twiddle factor participating in operation and a read address required by the coefficient storage unit; and the coefficient transposing unit is used for realizing coefficient reading meeting the index distance among all NTT stages. According to the side channel attack resisting NTT circuit oriented to the lattice-based cryptographic algorithm, when a low delay base-4CT / GS butterfly unit is masked, the increment of modular multiplication resources is reduced, and the resource consumption is remarkably reduced while high security is kept.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

Mechanisms for unordered input / output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input / output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input / output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input / output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input / output direct memory access operation request is for a write operation.

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

To provide a game machine that is improved regarding a setting for timer interruption by a game control microcomputer and a value control microcomputer.SOLUTION: A game machine comprises a main control section 161 for controlling a game and a token number control section 171 for controlling a credit possessed by a player, microcomputers for constituting the main control section 161 and the token number control section 171 are microcomputers having the same specifications that allow interruption to occur by a first timer interruption because of expiration of a first timer circuit TM1, a second timer interruption because of expiration of a second timer circuit TM2, and the like, and the setting of the microcomputer for constituting the main control circuit 161 and the microcomputer for constituting the token number control section 171 is commonalized so as to generate a timer interruption because of expiration of the same timer circuit each.SELECTED DRAWING: Figure 46

A tile-based graphics processor performs first and second processing passes to generate a render output. The first processing pass generates data that is used in the second processing pass to determine which primitives to process for which rendering tiles. The first processing pass is performed by a geometry processing control unit assembling primitives, and one or more programmable processing units transforming geometry data defining the primitives, and processing the transformed geometry data to generate the data.

To provide a management system that improves the maintainability of a configurator.SOLUTION: A management system manages a configurator that selects candidate combinations of elements that configure a product. The management system comprises: a storage unit for storing configuration information that defines data related to the elements, data related to connections between the elements, and data related to constraints on the connections; and a control unit for selecting candidates for the combination based on a request received from a user and rules related to the combination of the elements generated from the configuration information.SELECTED DRAWING: Figure 1

The invention provides a memory test system and method, and the system comprises a test temperature box which is used for regulating and controlling the environment temperature; the processing module is used for acquiring environment temperatures and sending different read-write instructions and corresponding test data to the memory at different environment temperatures; the power consumption module is used for monitoring power consumption data of the memory; the power consumption module is also used for transmitting the power consumption data to the processing module; wherein the memory executes a read-write operation according to a read-write instruction, and transmits a master control temperature of a master control unit of the memory and a flash memory temperature of a flash memory unit to the processing module; and the processing module is also used for calculating a read-write performance value according to the test data when the memory executes the read-write operation. According to the test system and the test method for the memory, the correlation of the performance, the power consumption and the temperature of the memory in various application scenes can be rapidly tested.

The invention relates to a memory and an operating method thereof. The memory comprises a memory array and an access interface for externally accessing the memory array comprising at least one data / address multiplexing line for transmitting data and addresses. The method comprises the following steps: starting a specified fixed-number random access mode, and performing continuous read / write operation on a storage array in response to a plurality of received fixed-number random access addresses in the mode; sequentially and continuously receiving a preset fixed number of access addresses through the data / address multiplexing line; a control unit configured to sequentially and continuously output data read in response to the received access addresses via the data / address multiplexing line when the mode indicates a read operation, or sequentially and continuously receive data written in response to the received access addresses via the data / address multiplexing line when the mode indicates a write operation; and ending the mode by receiving an invalid chip enable signal. According to the scheme, the access speed of the memory can be increased.

The invention provides an automatic testing device for an electrical interface of hardware equipment, which comprises a core control unit, an AT32F415CBT7 single chip microcomputer, an RS232 serial port testing interface and an RS485 serial port testing interface, the test unit comprises eight paths of optical coupling isolation switching value input / output interfaces, a test module power supply input interface, a 24V power supply input interface of equipment to be tested, a state indication LED module and a vacancy detection module which are respectively used for host communication and equipment test, and a travel switch is adopted to detect the occupation state of the test unit, wherein the 24V power supply input interface of the equipment to be tested is powered by an ejector pin. According to the invention, the efficiency and accuracy of hardware equipment interface function testing can be improved, the labor cost is reduced, and batch detection requirements are met.

In a storage device including a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, each of the controllers includes: a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

The invention provides an instruction processing device, system and processing method based on an RISC-V. The device comprises a processor core and an instruction co-processing module, and the processor core comprises a decoding module, a distribution module and an operation module which are connected in sequence; the decoding module comprises an extension instruction interface coding unit; the decoding module is used for integrating the extension interface signals output by the extension instruction interface coding unit into an integration result and sending the integration result to the distribution module; the expansion interface signal is a pre-configured expandable interface signal; the distribution module is used for distributing the instruction to the operation module according to the integration result; an instruction control unit in the operation module is used for receiving the instruction distributed by the distribution module, executing vector processing operation to generate an operation result and sending the operation result to the instruction co-processing module; and the instruction co-processing module is used for interacting with the instruction control unit and executing corresponding processing operation. According to the scheme, constantly changing service requirements are met, and the equipment has higher flexibility.

Aspects disclosed in the detailed description include a processing unit for dynamically reconfiguring micro-architectural features of the processing unit in response to a workload being processed on the processing unit and a processing unit control unit configured to receive a plurality of signals from the processing unit. The plurality of signals are indicia of the workload being processed on the processing unit. In response, the processing unit control unit determines whether performance, power consumption, or both, of the processing unit may be improved by modifying a micro-architectural feature. In response to determining that performance or power consumption of the processing unit may be improved by modifying micro-architectural features, the processing unit control unit triggers the processing unit to modify one or more of its micro-architectural features. The processing unit, in response to being triggered by the processing unit control unit, modifies one or more of its micro-architectural features.

The embodiment of the invention discloses a storage device, a controller of the storage device and a data reading method, the storage device comprises a plurality of storage areas, each storage area comprises a plurality of storage blocks, and the controller of the storage device comprises a cache management unit, a data cache unit and a control unit. The control unit is configured to determine whether read data meets a preset pre-reading condition or not, and in response to the fact that the read data meets the pre-reading condition, pre-reading operation of the at least one storage area is started, so that the read data in the at least one storage area is sequentially read into the data cache unit, and the read data in the at least one storage area are stored in the data cache unit. And storing the cache management information to a cache management unit, wherein the cache management information comprises a logic address of a storage block of the pre-read data. Therefore, according to the embodiment, pre-reading can be started after the read data meets the pre-reading condition, so that the problems of pre-reading failure, pre-reading cutoff and the like are avoided, the cache management information is managed by adopting the cache management unit, a software record management structure is reduced, and access delay is further reduced.

A mixture-of-experts artificial intelligence model according to the present invention comprises: a CXL control unit that manages a CXL protocol; an NDP control unit that includes a memory mapping register set for communicating with a host; a memory unit composed of a plurality of memory chips that provide a memory capacity to the host; and an NDP core unit that processes MoEs existing in the memory unit, wherein the NDP core unit transmits only hot experts to a GPU accelerator while memory-based calculation is performed on cold experts that exist in the memory unit.

The invention provides a calculation module, a wafer level processor and a wafer level computer, the calculation module comprises a plurality of calculation nodes arranged in a preset arrangement mode, and each calculation node comprises a control unit and a plurality of quantum calculation units. The control unit is electrically connected with each quantum computing unit, the control unit is used for deploying computing tasks of each quantum computing unit, and the quantum computing units carry out quantum computing and information storage. The wafer-level processor comprises a plurality of calculation modules, and the wafer-level processor is arranged in a dilution refrigerator to form the wafer-level computer. According to the calculation module, the wafer-level processor and the wafer-level computer provided by the embodiment of the invention, the integration density is improved through a wafer-level integration technology, so that the calculation power of a system is improved.

The invention relates to an on-chip inter-core communication system and method, the system comprises a plurality of processor cores, a shared memory and an interrupt control unit, the shared memory is connected with the plurality of processor cores, the plurality of processor cores are respectively connected with the interrupt control unit, the plurality of processor cores are divided into data sending cores and data receiving cores, the server is responsible for executing tasks and inter-core communication; a data frame lookup table and an annular buffer area are divided in the shared memory; and the interrupt control unit is used for processing inter-core interrupt. According to the multi-core processor, the advantage that the processor core in the multi-core processor quickly accesses the on-chip shared memory is utilized, so that the time delay of data writing / reading is reduced.

In a storage device including a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, each of the controllers includes: a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

The present invention relates to the field of storage, and specifically to a PCIe dual-port SSD low-power control device and method. The device includes a load prediction unit and a power consumption control unit. The load prediction unit uses the PCIe power management module (ASPM)'s judgment result on the link idle state and the margin value of the receive / transmit buffer as input to calculate the current load state of each of the two ports and output a load level value. The power consumption control unit uses the load level output by the load prediction unit to timely adjust the operating state of each SSD module to achieve SSD power consumption control. The present invention detects the business pressure and load conditions of the two ports and adaptively adjusts the operating state of each SSD module to achieve dynamic adjustment of SSD power consumption. While ensuring timely and accurate data response, it minimizes the power consumption of the entire disk and improves the energy saving effect of the data center.

The invention discloses a multi-thread processor, a synchronization method, electronic equipment and a storage medium. The multi-thread processor comprises a plurality of computing units and a synchronous control unit which are coupled, each computing unit comprises a scheduling module and an execution module, and each scheduling module is configured to respond to a first instruction which is currently executed and needs to participate in a thread set barrier in response to a first instruction which is currently executed and needs to participate in a thread set barrier. First type information of the first instruction is sent to the synchronous control unit, the first instruction is sent to an execution module in the same calculation unit, and second type information of a first barrier instruction is sent to the synchronous control unit in response to the fact that the currently executed instruction is a first barrier instruction of a second type; each execution module is configured to send execution completion information of the first instruction to the synchronous control unit after the first instruction is executed; and the synchronization control unit is configured to control barrier synchronization among the plurality of thread sets corresponding to the plurality of computing units according to the received first type information, the second type information and the execution completion information.

The invention discloses a digital in-memory computing accelerator, an instruction set architecture and a data processing method thereof, and belongs to the technical field of in-memory computing. The digital memory computing accelerator comprises a chip-level module, a core-level module and a unit-level module, the chip-level module is used for acquiring a target calculation task, splitting the target calculation task into a plurality of core-level calculation tasks according to a load distribution strategy and distributing the core-level calculation tasks to the core-level module; the core-level module comprises a control unit, a calculation unit and a cache unit, and the control unit comprises an instruction fetching module, a decoding module and an instruction scheduler; an instruction fetching module reads a to-be-executed instruction corresponding to the core-level calculation task, a decoding module decodes the to-be-executed instruction to generate a control signal and sends the control signal to a calculation unit, and the to-be-executed instruction is an instruction of a calculation instruction set architecture in a digital memory; the calculation unit executes corresponding calculation operation according to the control signal; the cache unit caches intermediate data generated by executing the corresponding calculation operation.