1069 results about "Control unit" patented technology

A wind energy plant with a nacelle, a rotor, which features at least one rotor blade adjustable in its blade pitch angle, a central control device for controlling the wind energy plant and a control unit disposed in the rotor for controlling the blade pitch angle of the at least one rotor blade, wherein the central control device and the control unit in the rotor can exchange data with each other via a data link, which comprises at least one first sending and receiving device at the nacelle side and at least one second sending and receiving device at the rotor side, wherein a wireless network connection with a safety-oriented communication protocol is provided between the at least one first sending and receiving device and the at least one second sending and receiving device, and that one monitoring- and communication device at a time is associated to the first and / or the second sending and receiving device, which can monitor the function of the sending and receiving device and initiate a predetermined action in the case of an error.

The invention discloses a specific detection value identification method and device and a computer program product, and the method comprises the steps: S1, collecting the power data of a to-be-detected node of a power system, and transmitting the power data to an edge calculation layer in real time through a distributed operation system; s2, preprocessing the power data at an edge calculation layer to generate standardized time sequence data; s3, extracting time domain statistical features and frequency domain transformation features of the standardized time series data, and fusing high-dimensional features output by a pre-training deep learning model to construct a multi-dimensional feature vector; s4, performing pattern recognition on the multi-dimensional feature vector based on a pre-trained classification or clustering model, and outputting an anomaly detection result; and S5, feeding back an abnormal detection result to the power equipment control unit in real time through the distributed operating system, and triggering an alarm or executing parameter adjustment. According to the invention, efficient distribution of detection results and multi-node parallel processing can be realized, and the system performance is further optimized.

The invention relates to a rectification harmonic suppression control method for a double reverse star transformer. The method comprises the following steps: establishing a rectifier bridge arm phase characteristic parameter table in a control platform, and recording a theoretical conduction phase, winding attribution and waveform synchronization characteristics of a bridge arm; in the operation process of the rectification control unit, the output current of a transformer and the conduction state of a bridge arm are collected, and a rectification operation state data set is generated; and calculating bridge arm conduction phase deviation, and analyzing a corresponding harmonic component to obtain a mapping relation between a bridge arm state and harmonic distribution. And judging whether the current bridge arm configuration meets the phase coverage requirement of the target rectification pulse number or not according to the mapping result, and if not, selecting a standby bridge arm group with a preset phase difference and generating a switching instruction. And the rectification control unit responds to the instruction to lock the current bridge arm conduction path and release the target bridge arm group so as to realize bridge arm resource dynamic reconstruction and rectification performance optimization. Harmonic waves can be effectively suppressed, and the topology adaptability and the output quality of the rectification system are improved.

A canteen is composed of a main body, a cover, a control unit, a valve and an annular blocker. The cover is engaged with the main body, having a jointing tube protruding into the main body and two notches cut in the jointing tube. The control unit is fixed on the cover, having a jointing portion, two grooves formed in the jointing portion and reversely shaped to correspond to the notches of the cover, and a sucker bored with an outlet. The valve is installed in the control unit, having a bar to correspond to the outlet, and a guiding rod transversely extended out from its bottom to extend through the grooves and the notches of the cover. When rotating the control unit, the valve is moved up and down to be separated from or to clog the outlet, convenient for using and preventing the suction portion from contaminated.

The invention discloses a dynamic neutral position and boundary self-calibration method and system of a joystick, and belongs to the technical field of engineering machinery and mining equipment control, and the method comprises the following steps: S1, electrifying equipment, and selecting a mode; s2, calibrating a dead zone; s3, setting a threshold value; s4, data storage; and S5, exiting and applying. According to the dynamic median and boundary self-calibration method and system of the joystick, when the joystick works, a physical manipulated variable is converted into an original electric signal through a joystick sensing unit, then the original electric signal is received through a signal processing module and subjected to signal conditioning, and an analog signal is converted into a digital signal which can be processed by a microprocessor; all logical judgments are executed through the main control unit, a user issues an instruction through a user configuration interface and directly inputs the instruction to the main control unit, the main control unit and the nonvolatile memory carry out bidirectional data interaction to realize permanent storage and calling of dead zone parameters, and the main control unit generates a final control instruction to be output after processing all information. And the actuating mechanism is driven.

A valve timing control device includes: a unit for calculating a target valve timing for one of an intake valve and an exhaust valve in accordance with an operational state; a unit for detecting an actual valve timing of one of the intake valve and the exhaust valve; an actual valve timing control unit for generating a controlled variable for the VVT based on a difference between the target valve timing and the actual valve timing; a unit for learning a learning value of the controlled variable required for maintenance of the actual valve timing based on an integral correction value; and a unit for detecting a malfunction in a VVT from an amount of a shift in the actual valve timing when learning is not completed yet, and for detecting a malfunction in the VVT from the difference when learning is already completed.

A server delay controller includes: a sleep management unit that makes a thread sleep when no packet arrives for a predetermined period and cancels the sleep of the thread with a hardware interrupt when the packet arrives; a HW interrupt frequency management table that stores the number of times of hardware interrupt; and a HW interrupt frequency control unit that calculates a HW interrupt frequency on the basis of the number of times of hardware interrupt and controls HW interrupt permission or prohibition by sleep of the sleep management unit on the basis of the calculated HW interrupt frequency.

The invention discloses a large-model context control system and method based on hierarchical memory and an association graph, and the method comprises the steps: constructing a tree graph mixed memory structure and a logic hierarchical memory model for a context control unit between a user and an LLM, and carrying out the self-adaptive processing of a super-long context through a self-adaptive processing engine, a single-theme persistent dialogue control mechanism, and the like. According to the method, the problem that an LLM context window is limited (including introduction of a mechanism similar to an Agent) is solved, just like an operating system helps developers / users to solve the problems that hardware standards hidden behind are not uniform, and complex resource control is caused, a reliable LLM memory (context) control service with multiple details hidden is provided for upper developers, and the method has the advantages of being high in practicability and easy to popularize and use. The final objective of the method is to approximately relieve the limitation of an LLM context window through a set of self-consistent system mechanism, so that a developer does not need to pay too much attention to the details of a bottom layer, and more energy can be focused on the implementation of an application function.

Certain examples described herein relate to at least a cryptographic system and a method of operating a cryptographic system. The cryptographic system may be implemented as a co-processor for performing post-quantum cryptographic functions. The cryptographic system has a set of bus interfaces for coupling to an external computing system, a cryptographic math unit and a control unit. The cryptographic math unit in certain examples is adapted to provide one or more masked modes of operation that secure the cryptographic operations against side-channel and non-invasive attacks. The method of operating a cryptographic system involves annotating secret data and tracking those annotations through one or more arithmetic operations.

The invention relates to the technical field of chip testing, and discloses a clock reset system-level verification method and device based on general verification methodology, and the method comprises the steps: firstly analyzing a clock topological relation defined in a system control unit architecture document, and generating a clock reset information table; on the basis of the information table, an executable verification environment component and a virtual interface component are automatically generated through a script, the verification environment component comprises an excitation forwarding and processing component and can generate clock and reset signals matched with framework definition, and the virtual interface component can generate actual clock and reset waveforms; and finally, constructing a verification platform based on the components, calling the excitation sequence in the parameterized test sequence library, and carrying out system-level clock reset verification on the digital chip. And meanwhile, the parameterized test sequence library supports flexible adjustment of a verification scene and ensures that a test case fits a clock frequency defined by an architecture document, and a reset mechanism can improve the efficiency, accuracy and reliability of digital chip clock reset system-level verification.

To provide a game machine that is improved regarding a setting for timer interruption by a game control microcomputer and a value control microcomputer.SOLUTION: A game machine comprises a main control section 161 for controlling a game and a token number control section 171 for controlling a credit possessed by a player, microcomputers for constituting the main control section 161 and the token number control section 171 are microcomputers having the same specifications that allow interruption to occur by a first timer interruption because of expiration of a first timer circuit TM1, a second timer interruption because of expiration of a second timer circuit TM2, and the like, and the setting of the microcomputer for constituting the main control circuit 161 and the microcomputer for constituting the token number control section 171 is commonalized so as to generate a timer interruption because of expiration of the same timer circuit each.SELECTED DRAWING: Figure 46

To provide a management system that improves the maintainability of a configurator.SOLUTION: A management system manages a configurator that selects candidate combinations of elements that configure a product. The management system comprises: a storage unit for storing configuration information that defines data related to the elements, data related to connections between the elements, and data related to constraints on the connections; and a control unit for selecting candidates for the combination based on a request received from a user and rules related to the combination of the elements generated from the configuration information.SELECTED DRAWING: Figure 1

The invention provides an automatic testing device for an electrical interface of hardware equipment, which comprises a core control unit, an AT32F415CBT7 single chip microcomputer, an RS232 serial port testing interface and an RS485 serial port testing interface, the test unit comprises eight paths of optical coupling isolation switching value input / output interfaces, a test module power supply input interface, a 24V power supply input interface of equipment to be tested, a state indication LED module and a vacancy detection module which are respectively used for host communication and equipment test, and a travel switch is adopted to detect the occupation state of the test unit, wherein the 24V power supply input interface of the equipment to be tested is powered by an ejector pin. According to the invention, the efficiency and accuracy of hardware equipment interface function testing can be improved, the labor cost is reduced, and batch detection requirements are met.

In a storage device including a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, each of the controllers includes: a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

The invention provides a calculation module, a wafer level processor and a wafer level computer, the calculation module comprises a plurality of calculation nodes arranged in a preset arrangement mode, and each calculation node comprises a control unit and a plurality of quantum calculation units. The control unit is electrically connected with each quantum computing unit, the control unit is used for deploying computing tasks of each quantum computing unit, and the quantum computing units carry out quantum computing and information storage. The wafer-level processor comprises a plurality of calculation modules, and the wafer-level processor is arranged in a dilution refrigerator to form the wafer-level computer. According to the calculation module, the wafer-level processor and the wafer-level computer provided by the embodiment of the invention, the integration density is improved through a wafer-level integration technology, so that the calculation power of a system is improved.

The present invention relates to the field of storage, and specifically to a PCIe dual-port SSD low-power control device and method. The device includes a load prediction unit and a power consumption control unit. The load prediction unit uses the PCIe power management module (ASPM)'s judgment result on the link idle state and the margin value of the receive / transmit buffer as input to calculate the current load state of each of the two ports and output a load level value. The power consumption control unit uses the load level output by the load prediction unit to timely adjust the operating state of each SSD module to achieve SSD power consumption control. The present invention detects the business pressure and load conditions of the two ports and adaptively adjusts the operating state of each SSD module to achieve dynamic adjustment of SSD power consumption. While ensuring timely and accurate data response, it minimizes the power consumption of the entire disk and improves the energy saving effect of the data center.

The invention discloses a digital in-memory computing accelerator, an instruction set architecture and a data processing method thereof, and belongs to the technical field of in-memory computing. The digital memory computing accelerator comprises a chip-level module, a core-level module and a unit-level module, the chip-level module is used for acquiring a target calculation task, splitting the target calculation task into a plurality of core-level calculation tasks according to a load distribution strategy and distributing the core-level calculation tasks to the core-level module; the core-level module comprises a control unit, a calculation unit and a cache unit, and the control unit comprises an instruction fetching module, a decoding module and an instruction scheduler; an instruction fetching module reads a to-be-executed instruction corresponding to the core-level calculation task, a decoding module decodes the to-be-executed instruction to generate a control signal and sends the control signal to a calculation unit, and the to-be-executed instruction is an instruction of a calculation instruction set architecture in a digital memory; the calculation unit executes corresponding calculation operation according to the control signal; the cache unit caches intermediate data generated by executing the corresponding calculation operation.

The invention provides an interrupt processing method, a PCIe system and a storage medium, and the method comprises the steps: a target EP in an EP set writes a message signal interrupt MSI interrupt number into a local address of the target EP, so that the MSI interrupt number enters a storage space corresponding to the target address based on a mapping relation between the local address and the target address of host equipment; and the RC reads the MSI interrupt number from the storage space corresponding to the target address, and executes an interrupt processing task corresponding to the MSI interrupt number. Based on the scheme, hardware resource occupation and design complexity of the EP and PCIe system are effectively reduced.

According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller including first and second caches and a first controller. The first cache includes a first memory unit and a first control unit. The second cache includes a second memory unit and a second control unit. The first memory unit includes a plurality of entries each having a cache tag including a first field and a cache line. Upon receiving a first prefetch request for first data of a first logical address, the first control unit stores the first data in the cache line of a first entry included in the first memory unit, and stores a first value in the first field of the first entry. The first control unit maintains the first entry until receiving a read request or a write request for the first logical address from the host.

To provide a game machine that is improved regarding a setting for timer interruption by a game control microcomputer and a value control microcomputer.SOLUTION: A game machine comprises a main control section 161 for controlling a game and a token number control section 171 for controlling a credit possessed by a player, microcomputers for constituting the main control section 161 and the token number control section 171 are microcomputers having the same specifications that allow interruption to occur by a first timer interruption because of expiration of a first timer circuit TM1, a second timer interruption because of expiration of a second timer circuit TM2, and the like, and the setting of the microcomputer for constituting the main control circuit 161 and the microcomputer for constituting the token number control section 171 is commonalized so as to generate a timer interruption because of expiration of the same timer circuit each.SELECTED DRAWING: Figure 46

To improve the convenience relating to generation of content including an itinerary or the like.SOLUTION: A program executed by a server communicating with a first terminal and a second terminal causes the server to execute: generating, by a control unit of the server, a talk room including (i) a first account of a first terminal, (ii) a second account of a second terminal, and (iii) an AI account, on the basis of first information transmitted from the first terminal; generating, by the control unit, second content on the basis of first content transmitted to the talk room from the first account or the second account; and performing, by the control unit, control for associating the generated second content with the AI account in the talk room.SELECTED DRAWING: Figure 1-1

The embodiment of the invention provides a data processing device, a processor and a data processing method. The data processing apparatus includes an instruction distribution unit, an instruction information recording unit, an instruction processing unit, and a write-back control unit, the instruction distribution unit being configured to split a vector instruction into a plurality of microinstructions, and to distribute the plurality of microinstructions to the instruction processing unit; the instruction information recording unit is configured to record instruction state information corresponding to a plurality of microinstructions respectively; the instruction processing unit is configured to receive a plurality of micro-instructions, process each of the plurality of micro-instructions to obtain a corresponding execution result, and feed back a processing progress to the instruction information recording unit; and the write-back control unit is configured to select at least one to-be-written-back microinstruction from the instruction information recording unit to perform write-back operation based on the instruction state information, and the write-back operation is used for writing an execution result of the to-be-written-back microinstruction back to the register. The device can realize out-of-order write-back of the instruction and improve the execution efficiency of the instruction.

The embodiment of the invention provides cross-chip NVMe write channel data replication, and relates to the technical field of storage. The storage device provided by the embodiment of the invention comprises a master control component and a slave control component, the master control component comprises a DMA data replication unit, and the slave control component comprises a bus data replication unit; under the condition that the host command indicates that the data is transferred to the first NVM chip, the DMA data copying unit transfers the data of the host to the first static random access memory and the first dynamic random access memory; under the condition that the host command indicates that the data is moved to the second NVM chip, the DMA data replication unit generates a bus write transaction for accessing the special address space and transmits the bus write transaction to the bus data replication unit; the bus data replication unit generates two bus write transactions in response to the received bus write transaction accessing the special address space, and transfers the data of the host to the second static random access memory and the second dynamic random access memory through the two bus write transactions.

The present application relates to the technical field of peripheral component interconnect express (PCIe) devices, and discloses a PCIe device detection system, method and apparatus, and a product. The PCIe device detection system at least includes a complex programmable logic device (CPLD), where the CPLD includes a control unit, configured to obtain presence information transmitted by a PCIe device during a detection cycle, the presence information including presence signals of all presence detection pins on the PCIe device; a parsing unit, configured to obtain all presence signals from the presence information, and determine an actual bandwidth of the PCIe device based on the presence signals; and a determination unit, configured to determine whether the PCIe device tilts according to a preset bandwidth and the actual bandwidth.

The invention discloses a PCIE (Peripheral Component Interface Express) link fault three-layer early warning and automatic repairing method and system, and the method comprises the following specific steps: hardware deployment and initialization: setting a PCIE switch with a link fault processing function between a PCIE control unit RC of a CPU (Central Processing Unit) and PCIE endpoint equipment; analyzing the direction of the error data, namely analyzing the transmission direction of the error data through PCIEswitch when the PCIEendpoint equipment has a link error; executing a third-level early warning mechanism, and performing third-level early warning based on an electrical layer, a protocol layer and a service layer, wherein the electrical layer collects BER, signal swing and clock jitter parameters; the protocol layer triggers early warning through TLP packet CRC error counting; according to the invention, hot plug deployment is realized through a hardware straight-through mode, a CPU drive or equipment firmware does not need to be modified, the repair process is completely and independently completed by switch, and link reset and equipment restart caused by intervention of an operating system in a traditional scheme are avoided. The total actually-measured repair time consumption is controlled at a microsecond level.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

To provide a game machine that is improved regarding a setting for timer interruption by a game control microcomputer and a value control microcomputer.SOLUTION: A game machine comprises a main control section 161 for controlling a game and a token number control section 171 for controlling a credit possessed by a player, microcomputers for constituting the main control section 161 and the token number control section 171 are microcomputers having the same specifications that allow interruption to occur by a first timer interruption because of expiration of a first timer circuit TM1, a second timer interruption because of expiration of a second timer circuit TM2, and the like, and the setting of the microcomputer for constituting the main control circuit 161 and the microcomputer for constituting the token number control section 171 is commonalized so as to generate a timer interruption because of expiration of the same timer circuit each.SELECTED DRAWING: Figure 46

The invention provides a safe starting method and device of a programmable logic controller, a PUF circuit, a starting control unit and a password authentication unit are integrated on a main controller chip of a PLC system, and the method comprises the following steps: responding to power-on of the PLC system, activating the PUF circuit and generating a device root key; the starting control unit activates and operates the starting state machine; under the control of the starting state machine, the starting control unit executes the following step-by-step verification and loading processes: reading a code of a first-stage boot loader from a boot read-only memory of the PLC system, and checking; in the first stage, the boot loader reads encrypted firmware data and checks the encrypted firmware data; loading an operating system component or an application program of the PLC system, and checking; and if the inspection is passed, entering an operation state, and executing a corresponding industrial control task by the PLC system. Firmware tampering and unauthorized code execution are effectively resisted, and the starting safety and the operation reliability of the PLC system are comprehensively enhanced.

The invention provides a scalar processor, a high-performance processor and electronic equipment, and the scalar processor comprises an instruction fetching unit, a register renaming unit, an operation reservation stack unit, a storage reservation stack unit, a scalar operation unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit and a register file unit, a special vector register file unit; wherein the synchronization unit is used for synchronizing the scalar processor and the vector processor. According to the scalar processor provided by the invention, the synchronization of the scalar processor and the vector processor is realized through the synchronization unit, so that an instruction is efficiently executed.